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/drivers/staging/media/atomisp/pci/css_2401_system/hive/
Dia_css_isp_params.c72 const struct ia_css_pipeline_stage *stage, in ia_css_process_aa() argument
76 stage->binary->info->mem_offsets.offsets.param->dmem.aa.size; in ia_css_process_aa()
78 stage->binary->info->mem_offsets.offsets.param->dmem.aa.offset; in ia_css_process_aa()
82 … &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset]; in ia_css_process_aa()
92 const struct ia_css_pipeline_stage *stage, in ia_css_process_anr() argument
99 stage->binary->info->mem_offsets.offsets.param->dmem.anr.size; in ia_css_process_anr()
102 stage->binary->info->mem_offsets.offsets.param->dmem.anr.offset; in ia_css_process_anr()
109 &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], in ia_css_process_anr()
113 params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = in ia_css_process_anr()
127 const struct ia_css_pipeline_stage *stage, in ia_css_process_anr2() argument
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/drivers/staging/media/atomisp/pci/runtime/pipeline/src/
Dpipeline.c49 static void pipeline_stage_destroy(struct ia_css_pipeline_stage *stage);
275 struct ia_css_pipeline_stage **stage) in ia_css_pipeline_create_and_add_stage() argument
328 if (stage) in ia_css_pipeline_create_and_add_stage()
329 *stage = new_stage; in ia_css_pipeline_create_and_add_stage()
340 struct ia_css_pipeline_stage *stage; in ia_css_pipeline_finalize_stages() local
343 for (stage = pipeline->stages; stage; stage = stage->next) { in ia_css_pipeline_finalize_stages()
344 stage->stage_num = i; in ia_css_pipeline_finalize_stages()
355 struct ia_css_pipeline_stage **stage) in ia_css_pipeline_get_stage() argument
360 assert(stage); in ia_css_pipeline_get_stage()
365 *stage = s; in ia_css_pipeline_get_stage()
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/drivers/staging/media/atomisp/pci/css_2400_system/hive/
Dia_css_isp_params.c71 const struct ia_css_pipeline_stage *stage, in ia_css_process_aa() argument
75 stage->binary->info->mem_offsets.offsets.param->dmem.aa.size; in ia_css_process_aa()
77 stage->binary->info->mem_offsets.offsets.param->dmem.aa.offset; in ia_css_process_aa()
81 … &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset]; in ia_css_process_aa()
85 params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = in ia_css_process_aa()
94 const struct ia_css_pipeline_stage *stage, in ia_css_process_anr() argument
101 stage->binary->info->mem_offsets.offsets.param->dmem.anr.size; in ia_css_process_anr()
104 stage->binary->info->mem_offsets.offsets.param->dmem.anr.offset; in ia_css_process_anr()
111 &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], in ia_css_process_anr()
115 params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = in ia_css_process_anr()
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/drivers/watchdog/
Dkempld_wdt.c77 struct kempld_wdt_stage stage[KEMPLD_WDT_MAX_STAGES]; member
105 struct kempld_wdt_stage *stage, in kempld_wdt_set_stage_action() argument
111 if (!stage || !stage->mask) in kempld_wdt_set_stage_action()
115 stage_cfg = kempld_read8(pld, KEMPLD_WDT_STAGE_CFG(stage->id)); in kempld_wdt_set_stage_action()
124 kempld_write8(pld, KEMPLD_WDT_STAGE_CFG(stage->id), stage_cfg); in kempld_wdt_set_stage_action()
131 struct kempld_wdt_stage *stage, in kempld_wdt_set_stage_timeout() argument
143 if (!stage) in kempld_wdt_set_stage_timeout()
151 if (stage_timeout64 > stage->mask) in kempld_wdt_set_stage_timeout()
154 stage_timeout = stage_timeout64 & stage->mask; in kempld_wdt_set_stage_timeout()
157 stage_cfg = kempld_read8(pld, KEMPLD_WDT_STAGE_CFG(stage->id)); in kempld_wdt_set_stage_timeout()
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/drivers/thermal/qcom/
Dqcom-spmi-temp-alarm.c77 unsigned int stage; member
117 static long qpnp_tm_decode_temp(struct qpnp_tm_chip *chip, unsigned int stage) in qpnp_tm_decode_temp() argument
119 if (!chip->temp_map || chip->thresh >= THRESH_COUNT || stage == 0 || in qpnp_tm_decode_temp()
120 stage > STAGE_COUNT) in qpnp_tm_decode_temp()
123 return (*chip->temp_map)[chip->thresh][stage - 1]; in qpnp_tm_decode_temp()
155 unsigned int stage, stage_new, stage_old; in qpnp_tm_update_temp_no_adc() local
163 stage = ret; in qpnp_tm_update_temp_no_adc()
166 stage_new = stage; in qpnp_tm_update_temp_no_adc()
167 stage_old = chip->stage; in qpnp_tm_update_temp_no_adc()
169 stage_new = alarm_state_map[stage]; in qpnp_tm_update_temp_no_adc()
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/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_lm.c54 static inline int _stage_offset(struct dpu_hw_mixer *ctx, enum dpu_stage stage) in _stage_offset() argument
57 if (stage != DPU_STAGE_BASE && stage <= sblk->maxblendstages) in _stage_offset()
58 return sblk->blendstage_base[stage - DPU_STAGE_0]; in _stage_offset()
100 u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) in dpu_hw_lm_setup_blend_config_sdm845() argument
106 if (stage == DPU_STAGE_BASE) in dpu_hw_lm_setup_blend_config_sdm845()
109 stage_off = _stage_offset(ctx, stage); in dpu_hw_lm_setup_blend_config_sdm845()
119 u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) in dpu_hw_lm_setup_blend_config() argument
124 if (stage == DPU_STAGE_BASE) in dpu_hw_lm_setup_blend_config()
127 stage_off = _stage_offset(ctx, stage); in dpu_hw_lm_setup_blend_config()
Ddpu_crtc.c178 lm->ops.setup_blend_config(lm, pstate->stage, in _dpu_crtc_setup_blend_cfg()
244 pstate->stage, in _dpu_crtc_blend_setup_mixer()
251 if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) in _dpu_crtc_blend_setup_mixer()
254 stage_idx = zpos_cnt[pstate->stage]++; in _dpu_crtc_blend_setup_mixer()
255 stage_cfg->stage[pstate->stage][stage_idx] = in _dpu_crtc_blend_setup_mixer()
257 stage_cfg->multirect_index[pstate->stage][stage_idx] = in _dpu_crtc_blend_setup_mixer()
277 1 << pstate->stage; in _dpu_crtc_blend_setup_mixer()
903 int stage; member
992 pstates[cnt].stage = pstate->normalized_zpos; in dpu_crtc_atomic_check()
1038 if (pstates[i].stage != z_pos) { in dpu_crtc_atomic_check()
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/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_ctl.c289 enum mdp_mixer_stage_id stage) in mdp_ctl_blend_mask() argument
292 case SSPP_VIG0: return MDP5_CTL_LAYER_REG_VIG0(stage); in mdp_ctl_blend_mask()
293 case SSPP_VIG1: return MDP5_CTL_LAYER_REG_VIG1(stage); in mdp_ctl_blend_mask()
294 case SSPP_VIG2: return MDP5_CTL_LAYER_REG_VIG2(stage); in mdp_ctl_blend_mask()
295 case SSPP_RGB0: return MDP5_CTL_LAYER_REG_RGB0(stage); in mdp_ctl_blend_mask()
296 case SSPP_RGB1: return MDP5_CTL_LAYER_REG_RGB1(stage); in mdp_ctl_blend_mask()
297 case SSPP_RGB2: return MDP5_CTL_LAYER_REG_RGB2(stage); in mdp_ctl_blend_mask()
298 case SSPP_DMA0: return MDP5_CTL_LAYER_REG_DMA0(stage); in mdp_ctl_blend_mask()
299 case SSPP_DMA1: return MDP5_CTL_LAYER_REG_DMA1(stage); in mdp_ctl_blend_mask()
300 case SSPP_VIG3: return MDP5_CTL_LAYER_REG_VIG3(stage); in mdp_ctl_blend_mask()
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Dmdp5_crtc.c184 static inline u32 mdp5_lm_use_fg_alpha_mask(enum mdp_mixer_stage_id stage) in mdp5_lm_use_fg_alpha_mask() argument
186 switch (stage) { in mdp5_lm_use_fg_alpha_mask()
228 enum mdp5_pipe stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } }; in blend_setup() enum
234 #define blender(stage) ((stage) - STAGE0) in blend_setup() argument
251 pstates[pstate->stage] = pstate; in blend_setup()
252 stage[pstate->stage][PIPE_LEFT] = mdp5_plane_pipe(plane); in blend_setup()
258 r_stage[pstate->stage][PIPE_LEFT] = in blend_setup()
267 stage[pstate->stage][PIPE_RIGHT] = right_pipe; in blend_setup()
268 r_stage[pstate->stage][PIPE_RIGHT] = right_pipe; in blend_setup()
357 mdp5_ctl_blend(ctl, pipeline, stage, r_stage, plane_cnt, in blend_setup()
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Dmdp5_kms.h102 enum mdp_mixer_stage_id stage; member
184 static inline const char *stage2name(enum mdp_mixer_stage_id stage) in stage2name() argument
193 return names[stage]; in stage2name()
/drivers/staging/media/atomisp/pci/
Dsh_css_sp.c123 unsigned int stage) in store_sp_stage_data() argument
131 sh_css_store_isp_stage_to_ddr(pipe_num, stage); in store_sp_stage_data()
132 sh_css_sp_group.pipe[thread_id].sp_stage_addr[stage] = in store_sp_stage_data()
133 sh_css_store_sp_stage_to_ddr(pipe_num, stage); in store_sp_stage_data()
809 is_sp_stage(struct ia_css_pipeline_stage *stage) in is_sp_stage() argument
811 assert(stage); in is_sp_stage()
812 return stage->sp_func != IA_CSS_PIPELINE_NO_FUNC; in is_sp_stage()
897 unsigned int stage, in sh_css_sp_init_stage() argument
935 sh_css_sp_group.pipe[thread_id].sp_stage_addr[stage] = mmgr_NULL; in sh_css_sp_init_stage()
943 sh_css_sp_stage.deinterleaved = ((stage == 0) && continuous); in sh_css_sp_init_stage()
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Dsh_css_params.c711 const struct ia_css_pipeline_stage *stage,
877 const struct ia_css_pipeline_stage *stage, in ia_css_process_kernel() argument
885 struct ia_css_pipeline_stage *stage; in ia_css_process_kernel() local
888 for (stage = pipeline->stages; stage; stage = stage->next) { in ia_css_process_kernel()
889 if (!stage || !stage->binary) continue; in ia_css_process_kernel()
890 process(pipeline->pipe_id, stage, params); in ia_css_process_kernel()
1091 const struct ia_css_pipeline_stage *stage, in ia_css_params_alloc_convert_sctbl() argument
1094 const struct ia_css_binary *binary = stage->binary; in ia_css_params_alloc_convert_sctbl()
1138 const struct ia_css_pipeline_stage *stage, in ia_css_params_store_sctbl() argument
1151 isp_sc_tbl = ia_css_params_alloc_convert_sctbl(stage, sc_config); in ia_css_params_store_sctbl()
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Dsh_css_params.h159 const struct ia_css_pipeline_stage *stage,
165 const struct ia_css_pipeline_stage *stage,
/drivers/gpu/drm/msm/disp/mdp4/
Dmdp4_kms.h102 enum mdp4_pipe pipe, enum mdp_mixer_stage_id stage) in mixercfg() argument
108 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE0(stage) | in mixercfg()
114 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE1(stage) | in mixercfg()
120 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE2(stage) | in mixercfg()
126 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE3(stage) | in mixercfg()
132 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE4(stage) | in mixercfg()
138 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE5(stage) | in mixercfg()
144 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE6(stage) | in mixercfg()
/drivers/media/radio/wl128x/
Dfmdrv_common.c172 fmdev->irq_info.handlers[fmdev->irq_info.stage](fmdev); in fm_irq_call()
176 static inline void fm_irq_call_stage(struct fmdev *fmdev, u8 stage) in fm_irq_call_stage() argument
178 fmdev->irq_info.stage = stage; in fm_irq_call_stage()
182 static inline void fm_irq_timeout_stage(struct fmdev *fmdev, u8 stage) in fm_irq_timeout_stage() argument
184 fmdev->irq_info.stage = stage; in fm_irq_timeout_stage()
278 if (irq_info->stage != 0) { in recv_tasklet()
280 irq_info->stage = 0; in recv_tasklet()
287 irq_info->handlers[irq_info->stage](fmdev); in recv_tasklet()
314 irq_info->handlers[irq_info->stage](fmdev); in recv_tasklet()
525 static inline void fm_irq_common_cmd_resp_helper(struct fmdev *fmdev, u8 stage) in fm_irq_common_cmd_resp_helper() argument
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/drivers/net/wwan/iosm/
Diosm_ipc_mmio.c51 static bool ipc_mmio_is_valid_exec_stage(enum ipc_mem_exec_stage stage) in ipc_mmio_is_valid_exec_stage() argument
53 switch (stage) { in ipc_mmio_is_valid_exec_stage()
85 enum ipc_mem_exec_stage stage; in ipc_mmio_init() local
100 stage = ipc_mmio_get_exec_stage(ipc_mmio); in ipc_mmio_init()
101 if (ipc_mmio_is_valid_exec_stage(stage)) in ipc_mmio_init()
108 dev_err(ipc_mmio->dev, "invalid exec stage %X", stage); in ipc_mmio_init()
/drivers/gpu/drm/tiny/
Drepaper.c201 enum repaper_stage stage) in repaper_even_pixels() argument
216 switch (stage) { in repaper_even_pixels()
247 enum repaper_stage stage) in repaper_odd_pixels() argument
261 switch (stage) { in repaper_odd_pixels()
297 enum repaper_stage stage) in repaper_all_pixels() argument
313 switch (stage) { in repaper_all_pixels()
341 enum repaper_stage stage) in repaper_one_line() argument
353 repaper_odd_pixels(epd, &p, data, fixed_value, mask, stage); in repaper_one_line()
364 repaper_even_pixels(epd, &p, data, fixed_value, mask, stage); in repaper_one_line()
378 repaper_all_pixels(epd, &p, data, fixed_value, mask, stage); in repaper_one_line()
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/drivers/staging/media/atomisp/pci/runtime/pipeline/interface/
Dia_css_pipeline.h165 struct ia_css_pipeline_stage **stage);
185 struct ia_css_pipeline_stage **stage);
199 struct ia_css_pipeline_stage **stage);
224 struct ia_css_pipeline_stage **stage);
/drivers/input/misc/
Dkeyspan_remote.c117 int stage; member
185 switch(remote->stage) { in keyspan_check_data()
199 remote->stage = 1; in keyspan_check_data()
215 remote->stage = 0; in keyspan_check_data()
232 remote->stage = 0; in keyspan_check_data()
235 remote->stage = 2; in keyspan_check_data()
264 remote->stage = 0; in keyspan_check_data()
285 remote->stage = 0; in keyspan_check_data()
303 remote->stage = 0; in keyspan_check_data()
326 remote->stage = 0; in keyspan_check_data()
/drivers/staging/octeon-usb/
Docteon-hcd.c287 enum cvmx_usb_stage stage; member
1367 switch (transaction->stage) { in cvmx_usb_start_channel_control()
1609 if ((transaction->stage & 1) == 0) { in cvmx_usb_start_channel()
1623 usbc_hcsplt.s.compsplt = (transaction->stage == in cvmx_usb_start_channel()
2086 transaction->stage = CVMX_USB_STAGE_NON_CONTROL; in cvmx_usb_complete()
2155 transaction->stage = CVMX_USB_STAGE_SETUP; in cvmx_usb_submit_transaction()
2157 transaction->stage = CVMX_USB_STAGE_NON_CONTROL; in cvmx_usb_submit_transaction()
2402 switch (transaction->stage) { in cvmx_usb_transfer_control()
2412 transaction->stage = in cvmx_usb_transfer_control()
2418 transaction->stage = CVMX_USB_STAGE_DATA; in cvmx_usb_transfer_control()
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/drivers/staging/media/atomisp/pci/runtime/debug/src/
Dia_css_debug.c2238 struct ia_css_pipeline_stage *stage; in findf_dmem_params() local
2240 for (stage = pipeline->stages; stage; stage = stage->next) { in findf_dmem_params()
2241 struct ia_css_binary *binary = stage->binary; in findf_dmem_params()
2646 struct ia_css_pipeline_stage *stage, in ia_css_debug_pipe_graph_dump_stage() argument
2653 assert(stage); in ia_css_debug_pipe_graph_dump_stage()
2654 if (stage->sp_func != IA_CSS_PIPELINE_NO_FUNC) in ia_css_debug_pipe_graph_dump_stage()
2662 if (stage->binary) { in ia_css_debug_pipe_graph_dump_stage()
2664 if (stage->binary->info->blob) in ia_css_debug_pipe_graph_dump_stage()
2666 stage->binary->info->blob->name, stage->stage_num); in ia_css_debug_pipe_graph_dump_stage()
2667 } else if (stage->firmware) { in ia_css_debug_pipe_graph_dump_stage()
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/drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/
Dia_css_s3a.host.c115 const struct ia_css_pipeline_stage *stage,
118 short dmem_offset = stage->binary->info->mem_offsets->dmem.s3a;
124 &stage->isp_mem_params[IA_CSS_ISP_DMEM0].address[dmem_offset],
127 &stage->isp_mem_params[IA_CSS_ISP_DMEM0].address[dmem_offset],
130 params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM0] =
/drivers/crypto/vmx/
Daesp8-ppc.pl122 my ($stage,$outperm,$outmask,$outhead,$outtail)=map("v$_",(7..11));
204 vsel $stage,$outhead,$outtail,$outmask
207 stvx $stage,0,$out
224 vsel $stage,$outhead,$outtail,$outmask
227 stvx $stage,0,$out
241 vsel $stage,$outhead,$outtail,$outmask
244 stvx $stage,0,$out
254 vsel $stage,$outhead,$outtail,$outmask
256 stvx $stage,0,$out
269 vsel $stage,$outhead,$outtail,$outmask
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/drivers/staging/greybus/
Dbootrom.c144 static int find_firmware(struct gb_bootrom *bootrom, u8 stage) in find_firmware() argument
155 if (stage != 2) { in find_firmware()
157 stage); in find_firmware()
210 ret = find_firmware(bootrom, size_request->stage); in gb_bootrom_firmware_size_request()
/drivers/acpi/
Dsleep.c912 static int acpi_hibernation_begin(pm_message_t stage) in acpi_hibernation_begin() argument
920 if (stage.event == PM_EVENT_HIBERNATE) in acpi_hibernation_begin()
984 static int acpi_hibernation_begin_old(pm_message_t stage) in acpi_hibernation_begin_old() argument
1004 if (stage.event == PM_EVENT_HIBERNATE) in acpi_hibernation_begin_old()

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