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Searched refs:status_page (Results 1 – 23 of 23) sorted by relevance

/drivers/gpu/drm/i915/gt/
Dintel_engine.h135 return READ_ONCE(engine->status_page.addr[reg]); in intel_read_status_page()
148 clflush(&engine->status_page.addr[reg]); in intel_write_status_page()
149 engine->status_page.addr[reg] = value; in intel_write_status_page()
150 clflush(&engine->status_page.addr[reg]); in intel_write_status_page()
153 WRITE_ONCE(engine->status_page.addr[reg], value); in intel_write_status_page()
Dintel_ring_submission.c54 static struct page *status_page(struct intel_engine_cs *engine) in status_page() function
56 struct drm_i915_gem_object *obj = engine->status_page.vma->obj; in status_page()
64 set_hws_pga(engine, PFN_PHYS(page_to_pfn(status_page(engine)))); in ring_setup_phys_status_page()
129 set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma)); in ring_setup_status_page()
269 list_for_each_entry(tl, &engine->status_page.timelines, engine_link) in sanitize_hwsp()
285 memset(engine->status_page.addr, POISON_INUSE, PAGE_SIZE); in xcs_sanitize()
295 drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE); in xcs_sanitize()
1372 GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma); in intel_ring_submission_setup()
Dselftest_lrc.c76 i915_ggtt_offset(ce->engine->status_page.vma) + in emit_semaphore_signal()
525 i915_ggtt_offset(ce->engine->status_page.vma) + in __gpr_read()
580 u32 *slot = memset32(engine->status_page.addr + 1000, 0, 4); in __live_lrc_gpr()
702 i915_ggtt_offset(ce->engine->status_page.vma) + in create_timestamp()
761 u32 *slot = memset32(arg->engine->status_page.addr + 1000, 0, 4); in __lrc_timestamp()
1050 *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) + in record_registers()
1170 *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) + in poison_registers()
1297 u32 *sema = memset32(engine->status_page.addr + 1000, 0, 1); in __lrc_isolation()
Dselftest_engine_pm.c75 u32 *sema = memset32(engine->status_page.addr + 1000, 0, 5); in __measure_timestamps()
76 u32 offset = i915_ggtt_offset(engine->status_page.vma); in __measure_timestamps()
Dgen6_engine_cs.c376 GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); in gen6_emit_breadcrumb_xcs()
396 GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); in gen7_emit_breadcrumb_xcs()
Dintel_engine_cs.c651 vma = fetch_and_zero(&engine->status_page.vma); in cleanup_status_page()
695 INIT_LIST_HEAD(&engine->status_page.timelines); in init_status_page()
733 engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE); in init_status_page()
734 engine->status_page.vma = vma; in init_status_page()
895 struct i915_vma *hwsp = engine->status_page.vma; in intel_engine_destroy_pinned_context()
1535 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX]; in intel_engine_print_registers()
1843 hexdump(m, engine->status_page.addr, PAGE_SIZE); in intel_engine_dump()
Dintel_timeline.c167 struct i915_vma *hwsp = engine->status_page.vma; in intel_timeline_create_from_engine()
176 list_add_tail(&tl->engine_link, &engine->status_page.timelines); in intel_timeline_create_from_engine()
Dmock_engine.c345 engine->base.status_page.addr = (void *)(engine + 1); in mock_engine()
399 engine->status_page.vma = ce->timeline->hwsp_ggtt; in mock_engine_init()
Dintel_engine_pm.c170 GEM_BUG_ON(ce->timeline->hwsp_ggtt != engine->status_page.vma); in switch_to_kernel_context()
Dgen2_engine_cs.c145 GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); in __gen2_emit_breadcrumb()
Dintel_engine_types.h382 struct intel_hw_status_page status_page; member
Dintel_execlists_submission.c241 engine->status_page.addr[I915_GEM_HWS_PREEMPT] = state; in ring_set_paused()
2778 list_for_each_entry(tl, &engine->status_page.timelines, engine_link) in sanitize_hwsp()
2796 memset(engine->status_page.addr, POISON_INUSE, PAGE_SIZE); in execlists_sanitize()
2808 clflush_cache_range(engine->status_page.addr, PAGE_SIZE); in execlists_sanitize()
2874 i915_ggtt_offset(engine->status_page.vma)); in enable_execlists()
3446 (u64 *)&engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX]; in intel_execlists_submission_setup()
3449 &engine->status_page.addr[intel_hws_csb_write_index(i915)]; in intel_execlists_submission_setup()
Dgen8_engine_cs.c334 return (i915_ggtt_offset(engine->status_page.vma) + in preempt_address()
Dselftest_execlists.c1055 i915_ggtt_offset(ce->engine->status_page.vma) + in create_rewinder()
1154 slot = memset32(engine->status_page.addr + 1000, 0, 4); in live_timeslice_rewind()
/drivers/infiniband/hw/cxgb4/
Ddevice.c871 rdev->status_page = (struct t4_dev_status_page *) in c4iw_rdev_open()
873 if (!rdev->status_page) { in c4iw_rdev_open()
877 rdev->status_page->qp_start = rdev->lldi.vr->qp.start; in c4iw_rdev_open()
878 rdev->status_page->qp_size = rdev->lldi.vr->qp.size; in c4iw_rdev_open()
879 rdev->status_page->cq_start = rdev->lldi.vr->cq.start; in c4iw_rdev_open()
880 rdev->status_page->cq_size = rdev->lldi.vr->cq.size; in c4iw_rdev_open()
881 rdev->status_page->write_cmpl_supported = rdev->lldi.write_cmpl_support; in c4iw_rdev_open()
899 rdev->status_page->db_off = 0; in c4iw_rdev_open()
910 free_page((unsigned long)rdev->status_page); in c4iw_rdev_open()
926 free_page((unsigned long)rdev->status_page); in c4iw_rdev_close()
[all …]
Dprovider.c113 mm->addr = virt_to_phys(rhp->rdev.status_page); in c4iw_alloc_ucontext()
Diw_cxgb4.h187 struct t4_dev_status_page *status_page; member
Dqp.c1251 if (!rhp->rdev.status_page->db_off) { in c4iw_post_send()
1331 if (!qhp->rhp->rdev.status_page->db_off) { in c4iw_post_receive()
/drivers/infiniband/hw/qib/
Dqib_init.c310 u64 *status_page; in init_pioavailregs() local
326 status_page = (u64 *) in init_pioavailregs()
331 dd->devstatusp = status_page; in init_pioavailregs()
332 *status_page++ = 0; in init_pioavailregs()
334 dd->pport[pidx].statusp = status_page; in init_pioavailregs()
335 *status_page++ = 0; in init_pioavailregs()
342 dd->freezemsg = (char *) status_page; in init_pioavailregs()
345 ret = (char *) status_page - (char *) dd->pioavailregs_dma; in init_pioavailregs()
/drivers/gpu/drm/i915/selftests/
Di915_perf.c354 store = memset32(rq->engine->status_page.addr + 512, 0, 32); in live_noa_gpr()
372 *cs++ = i915_ggtt_offset(rq->engine->status_page.vma) + in live_noa_gpr()
Di915_request.c1862 return memset32(ce->engine->status_page.addr + 1000, 0, 21); in hwsp_scratch()
1867 return (i915_ggtt_offset(ce->engine->status_page.vma) + in hwsp_offset()
2097 i915_ggtt_offset(engine->status_page.vma) + in plug()
/drivers/gpu/drm/i915/gt/uc/
Dintel_guc_submission.c2323 list_for_each_entry(tl, &engine->status_page.timelines, engine_link) in sanitize_hwsp()
2339 memset(engine->status_page.addr, POISON_INUSE, PAGE_SIZE); in guc_sanitize()
2349 clflush_cache_range(engine->status_page.addr, PAGE_SIZE); in guc_sanitize()
2360 i915_ggtt_offset(engine->status_page.vma)); in setup_hwsp()
/drivers/gpu/drm/i915/
Di915_gpu_error.c1424 engine->status_page.vma, in intel_engine_coredump_add_vma()