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Searched refs:tc_port (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.c152 static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id) in icl_pll_id_to_tc_port()
157 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port) in icl_tc_port_to_pll_id() argument
159 return tc_port - TC_PORT_1 + DPLL_ID_ICL_MGPLL1; in icl_tc_port_to_pll_id()
179 enum tc_port tc_port = icl_pll_id_to_tc_port(id); in intel_tc_pll_enable_reg() local
182 return ADLP_PORTTC_PLL_ENABLE(tc_port); in intel_tc_pll_enable_reg()
184 return MG_PLL_ENABLE(tc_port); in intel_tc_pll_enable_reg()
3343 enum tc_port tc_port = icl_pll_id_to_tc_port(id); in mg_pll_get_hw_state() local
3360 MG_REFCLKIN_CTL(tc_port)); in mg_pll_get_hw_state()
3364 intel_de_read(dev_priv, MG_CLKTOP2_CORECLKCTL1(tc_port)); in mg_pll_get_hw_state()
3369 intel_de_read(dev_priv, MG_CLKTOP2_HSCLKCTL(tc_port)); in mg_pll_get_hw_state()
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Dintel_ddi.c1155 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); in icl_mg_phy_ddi_vswing_sequence() local
1171 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port)); in icl_mg_phy_ddi_vswing_sequence()
1173 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val); in icl_mg_phy_ddi_vswing_sequence()
1175 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port)); in icl_mg_phy_ddi_vswing_sequence()
1177 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val); in icl_mg_phy_ddi_vswing_sequence()
1182 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port)); in icl_mg_phy_ddi_vswing_sequence()
1186 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val); in icl_mg_phy_ddi_vswing_sequence()
1188 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port)); in icl_mg_phy_ddi_vswing_sequence()
1192 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val); in icl_mg_phy_ddi_vswing_sequence()
1197 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port)); in icl_mg_phy_ddi_vswing_sequence()
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Dintel_tc.c242 enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); in adl_tc_port_live_status_mask() local
247 val = intel_uncore_read(uncore, TCSS_DDI_STATUS(tc_port)); in adl_tc_port_live_status_mask()
294 enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); in adl_tc_phy_status_complete() local
298 val = intel_uncore_read(uncore, TCSS_DDI_STATUS(tc_port)); in adl_tc_phy_status_complete()
771 enum tc_port tc_port = intel_port_to_tc(i915, port); in tc_port_load_fia_params() local
778 dig_port->tc_phy_fia = tc_port / 2; in tc_port_load_fia_params()
779 dig_port->tc_phy_fia_idx = tc_port % 2; in tc_port_load_fia_params()
782 dig_port->tc_phy_fia_idx = tc_port; in tc_port_load_fia_params()
790 enum tc_port tc_port = intel_port_to_tc(i915, port); in intel_tc_port_init() local
792 if (drm_WARN_ON(&i915->drm, tc_port == TC_PORT_NONE)) in intel_tc_port_init()
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Dintel_dpll_mgr.h418 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
Dintel_display.h259 enum tc_port { enum
565 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
Dintel_display_power.c638 enum tc_port tc_port; in icl_tc_phy_aux_power_well_enable() local
640 tc_port = TGL_AUX_PW_TO_TC_PORT(power_well->desc->hsw.idx); in icl_tc_phy_aux_power_well_enable()
641 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), in icl_tc_phy_aux_power_well_enable()
642 HIP_INDEX_VAL(tc_port, 0x2)); in icl_tc_phy_aux_power_well_enable()
644 if (intel_de_wait_for_set(dev_priv, DKL_CMN_UC_DW_27(tc_port), in icl_tc_phy_aux_power_well_enable()
Dintel_display.c3602 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) in intel_port_to_tc()
/drivers/gpu/drm/i915/
Di915_reg.h2043 #define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \ argument
2044 _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
2054 #define MG_TX1_LINK_PARAMS(ln, tc_port) \ argument
2055 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
2067 #define MG_TX2_LINK_PARAMS(ln, tc_port) \ argument
2068 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
2081 #define MG_TX1_PISO_READLOAD(ln, tc_port) \ argument
2082 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
2094 #define MG_TX2_PISO_READLOAD(ln, tc_port) \ argument
2095 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
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