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Searched refs:tf_regs (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dpp.c42 dpp->tf_regs->reg
418 const struct dcn2_dpp_registers *tf_regs, in dpp2_construct() argument
428 dpp->tf_regs = tf_regs; in dpp2_construct()
Ddcn20_resource.c769 #define tf_regs(id)\ macro
775 static const struct dcn2_dpp_registers tf_regs[] = { variable
776 tf_regs(0),
777 tf_regs(1),
778 tf_regs(2),
779 tf_regs(3),
780 tf_regs(4),
781 tf_regs(5),
1115 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn20_dpp_create()
Ddcn20_dpp.h681 const struct dcn2_dpp_registers *tf_regs; member
771 const struct dcn2_dpp_registers *tf_regs,
Ddcn20_dpp_cm.c37 dpp->tf_regs->reg
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dpp.c42 dpp->tf_regs->reg
554 const struct dcn_dpp_registers *tf_regs, in dpp1_construct() argument
564 dpp->tf_regs = tf_regs; in dpp1_construct()
Ddcn10_resource.c408 #define tf_regs(id)\ macro
413 static const struct dcn_dpp_registers tf_regs[] = { variable
414 tf_regs(0),
415 tf_regs(1),
416 tf_regs(2),
417 tf_regs(3),
652 &tf_regs[inst], &tf_shift, &tf_mask); in dcn10_dpp_create()
Ddcn10_dpp_dscl.c43 dpp->tf_regs->reg
207 if (dpp->tf_regs->DSCL_MEM_PWR_CTRL) { in dpp1_power_on_dscl()
Ddcn10_dpp_cm.c43 dpp->tf_regs->reg
Ddcn10_dpp.h1355 const struct dcn_dpp_registers *tf_regs; member
1517 const struct dcn_dpp_registers *tf_regs,
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.c654 #define tf_regs(id)\ macro
660 static const struct dcn2_dpp_registers tf_regs[] = { variable
661 tf_regs(0),
662 tf_regs(1),
663 tf_regs(2),
664 tf_regs(3),
741 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn21_dpp_create()
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dpp.c34 dpp->tf_regs->reg
1425 const struct dcn3_dpp_registers *tf_regs, in dpp3_construct() argument
1435 dpp->tf_regs = tf_regs; in dpp3_construct()
Ddcn30_dpp.h561 const struct dcn3_dpp_registers *tf_regs; member
580 const struct dcn3_dpp_registers *tf_regs,
Ddcn30_dpp_cm.c34 dpp->tf_regs->reg