/drivers/gpu/drm/amd/display/dc/core/ |
D | dc_hw_sequencer.c | 308 struct pipe_ctx *top_pipe = pipe_ctx; in get_mpctree_visual_confirm_color() local 310 while (top_pipe->top_pipe) in get_mpctree_visual_confirm_color() 311 top_pipe = top_pipe->top_pipe; in get_mpctree_visual_confirm_color() 313 *color = pipe_colors[top_pipe->pipe_idx]; in get_mpctree_visual_confirm_color() 375 while (top_pipe_ctx->top_pipe != NULL) in get_hdr_visual_confirm_color() 376 top_pipe_ctx = top_pipe_ctx->top_pipe; in get_hdr_visual_confirm_color()
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D | dc_resource.c | 666 other_pipe = pipe->top_pipe; in get_num_mpc_splits() 669 other_pipe = other_pipe->top_pipe; in get_num_mpc_splits() 697 struct pipe_ctx *split_pipe = pipe_ctx->top_pipe; in calculate_split_count_and_index() 702 split_pipe = split_pipe->top_pipe; in calculate_split_count_and_index() 1116 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == plane_state) { in resource_build_scaling_params() 1248 && !res_ctx->pipe_ctx[i].top_pipe in resource_get_head_pipe_for_stream() 1316 if (split_pipe->top_pipe && in acquire_first_split_pipe() 1317 split_pipe->top_pipe->plane_state == split_pipe->plane_state) { in acquire_first_split_pipe() 1318 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe; in acquire_first_split_pipe() 1320 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe; in acquire_first_split_pipe() [all …]
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D | dc.c | 420 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe) in dc_stream_forward_dmcu_crc_window() 454 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe) in dc_stream_stop_dmcu_crc_win_update() 499 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe) in dc_stream_configure_crc() 956 if (!pipe_ctx->top_pipe && in apply_ctx_interdependent_lock() 1240 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe) in program_timing_sync() 1859 if (cur_pipe->top_pipe) in dc_copy_state() 1860 cur_pipe->top_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx]; in dc_copy_state() 2692 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) { in commit_planes_do_stream_update() 2832 if (!pipe_ctx->top_pipe && in commit_planes_for_stream() 2930 if (!pipe_ctx->top_pipe && in commit_planes_for_stream()
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D | dc_link_hwss.c | 335 !pipes[i].top_pipe && !pipes[i].prev_odm_pipe && in dp_retrain_link_dp_test()
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D | dc_link_dp.c | 2995 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) { in dp_test_send_link_test_pattern() 4377 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) { in dc_link_dp_set_test_pattern()
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/drivers/gpu/drm/amd/display/dc/basics/ |
D | dc_common.c | 65 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) in is_upper_pipe_tree_visible() 74 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) in is_pipe_tree_visible()
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/drivers/gpu/drm/amd/display/dc/dcn20/ |
D | dcn20_resource.c | 1759 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) { in remove_dsc_from_stream_resource() 1889 if (prev_odm_pipe->top_pipe && prev_odm_pipe->top_pipe->next_odm_pipe) { in dcn20_split_stream_for_odm() 1890 prev_odm_pipe->top_pipe->next_odm_pipe->bottom_pipe = next_odm_pipe; in dcn20_split_stream_for_odm() 1891 next_odm_pipe->top_pipe = prev_odm_pipe->top_pipe->next_odm_pipe; in dcn20_split_stream_for_odm() 1894 prev_odm_pipe->bottom_pipe->next_odm_pipe->top_pipe = next_odm_pipe; in dcn20_split_stream_for_odm() 1936 if (!next_odm_pipe->top_pipe) in dcn20_split_stream_for_odm() 1939 next_odm_pipe->stream_res.opp = next_odm_pipe->top_pipe->stream_res.opp; in dcn20_split_stream_for_odm() 1940 if (next_odm_pipe->stream->timing.flags.DSC == 1 && !next_odm_pipe->top_pipe) { in dcn20_split_stream_for_odm() 1973 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe; in dcn20_split_stream_for_mpc() 1976 secondary_pipe->top_pipe = primary_pipe; in dcn20_split_stream_for_mpc() [all …]
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D | dcn20_hwseq.c | 596 pipe_ctx->top_pipe = NULL; in dcn20_plane_atomic_disable() 660 if (pipe_ctx->top_pipe != NULL) in dcn20_enable_stream_timing() 808 if (pipe_ctx->top_pipe == NULL in dcn20_set_output_transfer_func() 1150 if (!pipe_ctx->top_pipe in dcn20_enable_plane() 1172 if (!pipe || pipe->top_pipe) in dcn20_pipe_control_lock() 1274 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { in dcn20_detect_pipe_changes() 1291 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { in dcn20_detect_pipe_changes() 1577 for (other_pipe = pipe->top_pipe; other_pipe != NULL; other_pipe = other_pipe->top_pipe) { in calculate_vready_offset_for_group() 1601 && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe) in dcn20_program_pipe() 1605 if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe in dcn20_program_pipe() [all …]
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/drivers/gpu/drm/amd/display/dc/dcn30/ |
D | dcn30_resource.c | 1785 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) { in dcn30_split_stream_for_mpc_or_odm() 1786 pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe; in dcn30_split_stream_for_mpc_or_odm() 1787 sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe; in dcn30_split_stream_for_mpc_or_odm() 1790 pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe; in dcn30_split_stream_for_mpc_or_odm() 1796 if (!sec_pipe->top_pipe) in dcn30_split_stream_for_mpc_or_odm() 1799 sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp; in dcn30_split_stream_for_mpc_or_odm() 1810 sec_pipe->bottom_pipe->top_pipe = sec_pipe; in dcn30_split_stream_for_mpc_or_odm() 1813 sec_pipe->top_pipe = pri_pipe; in dcn30_split_stream_for_mpc_or_odm() 1836 if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL in dcn30_find_split_pipe() 1969 pipe->top_pipe = NULL; in dcn30_internal_validate_bw() [all …]
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D | dcn30_hwseq.c | 197 if (pipe_ctx->top_pipe == NULL) { in dcn30_set_output_transfer_func()
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/drivers/gpu/drm/amd/display/dc/dcn10/ |
D | dcn10_hw_sequencer.c | 109 if (pipe_ctx->top_pipe || in dcn10_lock_all_pipes() 817 for (other_pipe = pipe->top_pipe; other_pipe != NULL; other_pipe = other_pipe->top_pipe) { in calculate_vready_offset_for_group() 846 if (pipe_ctx->top_pipe != NULL) in dcn10_enable_stream_timing() 971 if (pipe_ctx->top_pipe == NULL) { in dcn10_reset_back_end_for_pipe() 1203 pipe_ctx->top_pipe = NULL; in dcn10_plane_atomic_disable() 1591 if (pipe_ctx_old->top_pipe) in dcn10_reset_hw_ctx_wrap() 1611 bool sec_split = pipe_ctx->top_pipe && in patch_address_for_sbs_tb_stereo() 1612 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo() 1790 if (!pipe || pipe->top_pipe) in dcn10_pipe_control_lock() 1873 if (!pipe || pipe->top_pipe) in dcn10_cursor_lock() [all …]
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/drivers/gpu/drm/amd/display/dc/calcs/ |
D | dcn_calcs.c | 312 } else if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state) { in pipe_ctx_to_e2e_pipe_params() 543 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe; in split_stream_across_pipes() 546 secondary_pipe->top_pipe = primary_pipe; in split_stream_across_pipes() 915 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) in dcn_validate_bandwidth() 1222 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) in dcn_validate_bandwidth() 1287 hsplit_pipe->bottom_pipe->top_pipe = pipe; in dcn_validate_bandwidth() 1290 hsplit_pipe->top_pipe = NULL; in dcn_validate_bandwidth()
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D | dce_calcs.c | 3018 if (!pipe[i].stream || pipe[i].top_pipe) in all_displays_in_sync()
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/drivers/gpu/drm/amd/display/dc/dcn31/ |
D | dcn31_hwseq.c | 513 ASSERT(!pipe_ctx->top_pipe); in dcn31_reset_back_end_for_pipe() 583 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) in dcn31_reset_hw_ctx_wrap()
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/drivers/gpu/drm/amd/display/dc/dce110/ |
D | dce110_hw_sequencer.c | 2030 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) in dce110_reset_hw_ctx_wrap() 2112 if (pipe_ctx->top_pipe) in dce110_setup_audio_dto() 2159 if (pipe_ctx->top_pipe) in dce110_setup_audio_dto() 2208 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) in dce110_apply_ctx_to_hw() 2244 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe) in dce110_apply_ctx_to_hw() 2864 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) in dce110_set_cursor_position()
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/drivers/gpu/drm/amd/display/dc/inc/ |
D | core_types.h | 359 struct pipe_ctx *top_pipe; member
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/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/ |
D | dce_clk_mgr.c | 177 if (pipe_ctx->top_pipe) in dce_get_max_pixel_clock_for_all_paths()
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/drivers/gpu/drm/amd/display/dc/dcn21/ |
D | dcn21_resource.c | 1268 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw() 1282 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state) in dcn21_fast_validate_bw()
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/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
D | dcn31_clk_mgr.c | 115 if (pipe->top_pipe || pipe->prev_odm_pipe) in dcn31_disable_otg_wa()
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/drivers/gpu/drm/amd/display/dc/dce/ |
D | dce_clk_mgr.c | 196 if (pipe_ctx->top_pipe) in get_max_pixel_clock_for_all_paths()
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