| /drivers/net/wireless/broadcom/brcm80211/brcmsmac/ |
| D | ucode_loader.c | 40 int brcms_ucode_data_init(struct brcms_info *wl, struct brcms_ucode *ucode) in brcms_ucode_data_init() argument
47 brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn0bsinitvals24, in brcms_ucode_data_init()
50 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn0initvals24, in brcms_ucode_data_init()
53 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn1bsinitvals24, in brcms_ucode_data_init()
56 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn1initvals24, in brcms_ucode_data_init()
59 brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn2bsinitvals24, in brcms_ucode_data_init()
62 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn2initvals24, in brcms_ucode_data_init()
65 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11n0absinitvals16, in brcms_ucode_data_init()
68 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11n0bsinitvals16, in brcms_ucode_data_init()
71 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11n0initvals16, in brcms_ucode_data_init()
[all …]
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| D | ucode_loader.h | 46 int brcms_ucode_data_init(struct brcms_info *wl, struct brcms_ucode *ucode);
48 void brcms_ucode_data_free(struct brcms_ucode *ucode);
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_ucode.c | 567 struct amdgpu_firmware_info *ucode, in amdgpu_ucode_init_single_fw() argument
576 if (NULL == ucode->fw) in amdgpu_ucode_init_single_fw()
579 ucode->mc_addr = mc_addr; in amdgpu_ucode_init_single_fw()
580 ucode->kaddr = kptr; in amdgpu_ucode_init_single_fw()
582 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE) in amdgpu_ucode_init_single_fw()
585 header = (const struct common_firmware_header *)ucode->fw->data; in amdgpu_ucode_init_single_fw()
586 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; in amdgpu_ucode_init_single_fw()
587 dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data; in amdgpu_ucode_init_single_fw()
588 dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data; in amdgpu_ucode_init_single_fw()
589 mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data; in amdgpu_ucode_init_single_fw()
[all …]
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| D | amdgpu_cgs.c | 213 struct amdgpu_firmware_info *ucode; in amdgpu_cgs_get_firmware_info() local
216 ucode = &adev->firmware.ucode[id]; in amdgpu_cgs_get_firmware_info()
217 if (ucode->fw == NULL) in amdgpu_cgs_get_firmware_info()
220 gpu_addr = ucode->mc_addr; in amdgpu_cgs_get_firmware_info()
221 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; in amdgpu_cgs_get_firmware_info()
230 info->kptr = ucode->kaddr; in amdgpu_cgs_get_firmware_info()
248 struct amdgpu_firmware_info *ucode = NULL; in amdgpu_cgs_get_firmware_info() local
429 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; in amdgpu_cgs_get_firmware_info()
430 ucode->ucode_id = AMDGPU_UCODE_ID_SMC; in amdgpu_cgs_get_firmware_info()
431 ucode->fw = adev->pm.fw; in amdgpu_cgs_get_firmware_info()
[all …]
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| D | amdgpu_psp.c | 454 struct amdgpu_firmware_info *ucode, in psp_cmd_submit_buf() argument
510 if (ucode) in psp_cmd_submit_buf()
512 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); in psp_cmd_submit_buf()
522 if (ucode) { in psp_cmd_submit_buf()
523 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; in psp_cmd_submit_buf()
524 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; in psp_cmd_submit_buf()
2279 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, in psp_get_fw_type() argument
2282 switch (ucode->ucode_id) { in psp_get_fw_type()
2394 struct amdgpu_firmware_info *ucode) in psp_print_fw_hdr() argument
2399 switch (ucode->ucode_id) { in psp_print_fw_hdr()
[all …]
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| D | aldebaran.c | 201 struct amdgpu_firmware_info *ucode; in aldebaran_mode2_restore_ip() local
208 ucode = &adev->firmware.ucode[i]; in aldebaran_mode2_restore_ip()
209 if (!ucode->fw) in aldebaran_mode2_restore_ip()
211 switch (ucode->ucode_id) { in aldebaran_mode2_restore_ip()
226 ucode_list[ucode_count++] = ucode; in aldebaran_mode2_restore_ip()
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| /drivers/crypto/marvell/octeontx/ |
| D | otx_cptpf_ucode.c | 97 static void set_ucode_filename(struct otx_cpt_ucode *ucode, in set_ucode_filename() argument
100 strlcpy(ucode->filename, filename, OTX_CPT_UCODE_NAME_LENGTH); in set_ucode_filename()
188 eng_grp->g->grp[eng_grp->mirror.idx].ucode[0].align_dma; in cpt_set_ucode_base()
190 dma_addr = eng_grp->ucode[0].align_dma; in cpt_set_ucode_base()
325 set_ucode_filename(&tar_info->ucode, filename); in process_tar_file()
326 memcpy(tar_info->ucode.ver_str, ucode_hdr->ver_str, in process_tar_file()
328 tar_info->ucode.ver_num = ucode_hdr->ver_num; in process_tar_file()
329 tar_info->ucode.type = ucode_type; in process_tar_file()
330 tar_info->ucode.size = ucode_size; in process_tar_file()
360 if (!is_eng_type(curr->ucode.type, ucode_type)) in get_uc_from_tar_archive()
[all …]
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| D | otx_cptpf_mbox.c | 140 struct otx_cpt_ucode *ucode; in otx_cpt_bind_vq_to_grp() local
165 ucode = &eng_grp->g->grp[eng_grp->mirror.idx].ucode[0]; in otx_cpt_bind_vq_to_grp()
167 ucode = &eng_grp->ucode[0]; in otx_cpt_bind_vq_to_grp()
169 if (otx_cpt_uc_supports_eng_type(ucode, OTX_CPT_SE_TYPES)) in otx_cpt_bind_vq_to_grp()
171 else if (otx_cpt_uc_supports_eng_type(ucode, OTX_CPT_AE_TYPES)) in otx_cpt_bind_vq_to_grp()
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| D | otx_cptpf_ucode.h | 97 struct otx_cpt_ucode ucode;/* microcode information */ member
115 struct otx_cpt_ucode *ucode; /* ucode used by these engines */ member
141 struct otx_cpt_ucode ucode[OTX_CPT_MAX_ETYPES_PER_GRP]; member
176 int otx_cpt_uc_supports_eng_type(struct otx_cpt_ucode *ucode, int eng_type);
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| /drivers/crypto/marvell/octeontx2/ |
| D | otx2_cptpf_ucode.c | 62 if (eng_grp->ucode[1].type) in is_2nd_ucode_used()
68 static void set_ucode_filename(struct otx2_cpt_ucode *ucode, in set_ucode_filename() argument
71 strlcpy(ucode->filename, filename, OTX2_CPT_NAME_LENGTH); in set_ucode_filename()
185 dma_addr = engs->ucode->dma; in cptx_set_ucode_base()
389 set_ucode_filename(&uc_info->ucode, filename); in load_fw()
390 memcpy(uc_info->ucode.ver_str, ucode_hdr->ver_str, in load_fw()
392 uc_info->ucode.ver_num = ucode_hdr->ver_num; in load_fw()
393 uc_info->ucode.type = ucode_type; in load_fw()
394 uc_info->ucode.size = ucode_size; in load_fw()
426 if (!is_eng_type(curr->ucode.type, ucode_type)) in get_ucode()
[all …]
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| D | otx2_cptpf_ucode.h | 90 struct otx2_cpt_ucode ucode;/* microcode information */ member
110 struct otx2_cpt_ucode *ucode; /* ucode used by these engines */ member
135 struct otx2_cpt_ucode ucode[OTX2_CPT_MAX_ETYPES_PER_GRP]; member
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| /drivers/soc/fsl/qe/ |
| D | qe.c | 405 const struct qe_microcode *ucode) in qe_upload_microcode() argument
407 const __be32 *code = base + be32_to_cpu(ucode->code_offset); in qe_upload_microcode()
410 if (ucode->major || ucode->minor || ucode->revision) in qe_upload_microcode()
413 ucode->id, ucode->major, ucode->minor, ucode->revision); in qe_upload_microcode()
416 "uploading microcode '%s'\n", ucode->id); in qe_upload_microcode()
419 iowrite32be(be32_to_cpu(ucode->iram_offset) | QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR, in qe_upload_microcode()
422 for (i = 0; i < be32_to_cpu(ucode->count); i++) in qe_upload_microcode()
534 const struct qe_microcode *ucode = &firmware->microcode[i]; in qe_upload_firmware() local
537 if (ucode->code_offset) in qe_upload_firmware()
538 qe_upload_microcode(firmware, ucode); in qe_upload_firmware()
[all …]
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| /drivers/crypto/cavium/nitrox/ |
| D | nitrox_main.c | 60 struct ucode { struct
114 struct ucode *ucode; in nitrox_load_fw() local
132 ucode = (struct ucode *)fw->data; in nitrox_load_fw()
134 ucode_size = be32_to_cpu(ucode->code_size) * 2; in nitrox_load_fw()
141 ucode_data = ucode->code; in nitrox_load_fw()
144 memcpy(&ndev->hw.fw_name[0][0], ucode->version, (VERSION_LEN - 2)); in nitrox_load_fw()
183 ucode = (struct ucode *)fw->data; in nitrox_load_fw()
185 ucode_size = be32_to_cpu(ucode->code_size) * 2; in nitrox_load_fw()
192 ucode_data = ucode->code; in nitrox_load_fw()
195 memcpy(&ndev->hw.fw_name[1][0], ucode->version, (VERSION_LEN - 2)); in nitrox_load_fw()
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| /drivers/input/touchscreen/ |
| D | hideep.c | 412 const __be32 *ucode, size_t xfer_count) in hideep_program_page() argument
438 val = be32_to_cpu(ucode[0]); in hideep_program_page()
442 ucode, xfer_count); in hideep_program_page()
444 val = be32_to_cpu(ucode[xfer_count - 1]); in hideep_program_page()
461 const __be32 *ucode, size_t ucode_len) in hideep_program_nvm() argument
476 xfer_count = xfer_len / sizeof(*ucode); in hideep_program_nvm()
488 if (memcmp(ucode, current_ucode, xfer_len)) { in hideep_program_nvm()
490 ucode, xfer_count); in hideep_program_nvm()
501 ucode += xfer_count; in hideep_program_nvm()
510 const __be32 *ucode, size_t ucode_len) in hideep_verify_nvm() argument
[all …]
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| /drivers/net/wireless/intel/iwlwifi/ |
| D | iwl-drv.c | 461 struct iwl_ucode_header *ucode = (void *)ucode_raw->data; in iwl_parse_v1_v2_firmware() local
466 drv->fw.ucode_ver = le32_to_cpu(ucode->ver); in iwl_parse_v1_v2_firmware()
476 build = le32_to_cpu(ucode->u.v2.build); in iwl_parse_v1_v2_firmware()
478 le32_to_cpu(ucode->u.v2.inst_size)); in iwl_parse_v1_v2_firmware()
480 le32_to_cpu(ucode->u.v2.data_size)); in iwl_parse_v1_v2_firmware()
482 le32_to_cpu(ucode->u.v2.init_size)); in iwl_parse_v1_v2_firmware()
484 le32_to_cpu(ucode->u.v2.init_data_size)); in iwl_parse_v1_v2_firmware()
485 src = ucode->u.v2.data; in iwl_parse_v1_v2_firmware()
497 le32_to_cpu(ucode->u.v1.inst_size)); in iwl_parse_v1_v2_firmware()
499 le32_to_cpu(ucode->u.v1.data_size)); in iwl_parse_v1_v2_firmware()
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| D | ctxnv40.h | 13 u32 *ucode; member
27 u32 *ctxprog = ctx->ucode; in cp_out()
61 u32 *ctxprog = ctx->ucode; in cp_name()
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| D | gf104.c | 133 .fecs.ucode = &gf100_gr_fecs_ucode,
134 .gpccs.ucode = &gf100_gr_gpccs_ucode,
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| D | gf110.c | 105 .fecs.ucode = &gf100_gr_fecs_ucode,
106 .gpccs.ucode = &gf100_gr_gpccs_ucode,
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| D | gk110b.c | 124 .fecs.ucode = &gk110_gr_fecs_ucode,
125 .gpccs.ucode = &gk110_gr_gpccs_ucode,
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| D | gf119.c | 196 .fecs.ucode = &gf100_gr_fecs_ucode,
197 .gpccs.ucode = &gf100_gr_gpccs_ucode,
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| D | gf108.c | 131 .fecs.ucode = &gf100_gr_fecs_ucode,
132 .gpccs.ucode = &gf100_gr_gpccs_ucode,
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| D | gk208.c | 182 .fecs.ucode = &gk208_gr_fecs_ucode,
183 .gpccs.ucode = &gk208_gr_gpccs_ucode,
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| D | gf117.c | 169 .fecs.ucode = &gf117_gr_fecs_ucode,
170 .gpccs.ucode = &gf117_gr_gpccs_ucode,
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| /drivers/gpu/drm/nouveau/nvkm/subdev/acr/ |
| D | gm200.c | 340 hsfw->image_size, 0x1000, false, &hsf->ucode); in gm200_acr_hsfw_load()
344 nvkm_kmap(hsf->ucode); in gm200_acr_hsfw_load()
345 nvkm_wobj(hsf->ucode, 0, hsfw->image, hsfw->image_size); in gm200_acr_hsfw_load()
346 nvkm_done(hsf->ucode); in gm200_acr_hsfw_load()
348 ret = nvkm_vmm_get(acr->vmm, 12, nvkm_memory_size(hsf->ucode), in gm200_acr_hsfw_load()
353 ret = nvkm_memory_map(hsf->ucode, 0, acr->vmm, hsf->vma, NULL, 0); in gm200_acr_hsfw_load()
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| /drivers/tty/serial/ |
| D | rp2.c | 185 void __iomem *ucode; member
368 up->ucode + RP2_TX_SWFLOW); in __rp2_uart_set_termios()
370 up->ucode + RP2_RX_SWFLOW); in __rp2_uart_set_termios()
643 writeb(fw->data[i], up->ucode + i); in rp2_init_port()
648 writeb(RP2_RX_FIFO_ena, up->ucode + RP2_RX_FIFO); in rp2_init_port()
678 rp->ucode = card->bar1 + RP2_UCODE_BASE + j*RP2_UCODE_SPACING; in rp2_load_firmware()
698 rp->ucode += RP2_ASIC_SPACING; in rp2_load_firmware()
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