/drivers/gpu/drm/amd/display/dc/dcn30/ |
D | dcn30_optc.c | 63 uint32_t v_blank_start = 0; in optc3_lock_doublebuffer_enable() local 69 OTG_V_BLANK_START, &v_blank_start, in optc3_lock_doublebuffer_enable() 76 MASTER_UPDATE_LOCK_DB_START_Y, v_blank_start, in optc3_lock_doublebuffer_enable() 80 DIG_UPDATE_POSITION_Y, v_blank_start); in optc3_lock_doublebuffer_enable()
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/drivers/gpu/drm/amd/display/dc/dcn10/ |
D | dcn10_optc.c | 1248 uint32_t *v_blank_start, in optc1_get_crtc_scanoutpos() argument 1257 OTG_V_BLANK_START, v_blank_start, in optc1_get_crtc_scanoutpos() 1340 hw_crtc_timing->v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end); in optc1_get_hw_timing() 1341 hw_crtc_timing->v_front_porch = s.v_total + 1 - s.v_blank_start; in optc1_get_hw_timing() 1355 OTG_V_BLANK_START, &s->v_blank_start, in optc1_read_otg_state() 1409 uint32_t v_blank_start; in optc1_get_otg_active_size() local 1423 OTG_V_BLANK_START, &v_blank_start, in optc1_get_otg_active_size() 1430 *otg_active_width = v_blank_start - v_blank_end; in optc1_get_otg_active_size()
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D | dcn10_dpp_dscl.c | 121 uint32_t v_blank_start = data->v_active; in dpp1_dscl_set_otg_blank() local 129 OTG_V_BLANK_START, v_blank_start, in dpp1_dscl_set_otg_blank()
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D | dcn10_optc.h | 562 uint32_t v_blank_start; member 634 uint32_t *v_blank_start,
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D | dcn10_hw_sequencer_debug.c | 440 s.v_blank_start, in dcn10_get_otg_states()
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D | dcn10_hw_sequencer.c | 373 s.v_blank_start, in dcn10_log_hw_state()
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/drivers/gpu/drm/amd/display/dc/dce120/ |
D | dce120_timing_generator.c | 594 uint32_t *v_blank_start, in dce120_timing_generator_get_crtc_scanoutpos() argument 607 *v_blank_start = get_reg_field_value(v_blank_start_end, in dce120_timing_generator_get_crtc_scanoutpos() 1059 uint32_t v_blank_start, v_blank_end, h_position, v_position; in dce120_arm_vert_intr() local 1063 &v_blank_start, in dce120_arm_vert_intr() 1068 if (v_blank_start == 0 || v_blank_end == 0) in dce120_arm_vert_intr() 1073 CRTC_VERTICAL_INTERRUPT0_LINE_START, v_blank_start, in dce120_arm_vert_intr() 1074 CRTC_VERTICAL_INTERRUPT0_LINE_END, v_blank_start + width); in dce120_arm_vert_intr()
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/drivers/gpu/drm/amd/display/dc/dcn20/ |
D | dcn20_optc.c | 453 uint32_t v_blank_start = 0; in optc2_lock_doublebuffer_enable() local 461 REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start); in optc2_lock_doublebuffer_enable() 469 v_blank_start - 1); in optc2_lock_doublebuffer_enable()
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/drivers/gpu/drm/amd/display/dc/dce110/ |
D | dce110_timing_generator.c | 571 uint32_t *v_blank_start, in dce110_timing_generator_get_crtc_scanoutpos() argument 582 *v_blank_start = get_reg_field_value(value, in dce110_timing_generator_get_crtc_scanoutpos() 2051 uint32_t v_blank_start = 0; in dce110_arm_vert_intr() local 2058 &v_blank_start, in dce110_arm_vert_intr() 2063 if (v_blank_start == 0 || v_blank_end == 0) in dce110_arm_vert_intr() 2068 v_blank_start, in dce110_arm_vert_intr() 2075 v_blank_start + width, in dce110_arm_vert_intr()
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D | dce110_timing_generator.h | 239 uint32_t *v_blank_start,
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/drivers/gpu/drm/amd/display/dc/core/ |
D | dc_stream.c | 610 uint32_t *v_blank_start, in dc_stream_get_scanoutpos() argument 628 v_blank_start, in dc_stream_get_scanoutpos()
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/drivers/gpu/drm/amd/display/dc/inc/hw/ |
D | timing_generator.h | 184 uint32_t *v_blank_start,
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/drivers/gpu/drm/amd/display/dc/ |
D | dc_stream.h | 351 uint32_t *v_blank_start,
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/drivers/video/fbdev/ |
D | smscufx.c | 663 u16 v_total, v_active, v_blank_start, v_blank_end, v_sync_start, v_sync_end; in ufx_set_vid_mode() local 707 v_blank_start = var->yres + var->lower_margin; in ufx_set_vid_mode() 716 temp = ((v_blank_start - 1) << 16) | (v_blank_end - 1); in ufx_set_vid_mode()
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/drivers/gpu/drm/amd/display/amdgpu_dm/ |
D | amdgpu_dm.c | 257 uint32_t v_blank_start, v_blank_end, h_position, v_position; in dm_crtc_get_scanoutpos() local 275 &v_blank_start, in dm_crtc_get_scanoutpos() 281 *vbl = v_blank_start | (v_blank_end << 16); in dm_crtc_get_scanoutpos() 399 uint32_t vpos, hpos, v_blank_start, v_blank_end; in dm_pflip_high_irq() local 433 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start, in dm_pflip_high_irq() 435 (vpos < v_blank_start)) { in dm_pflip_high_irq()
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