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Searched refs:v_table (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/radeon/
Dradeon_legacy_tv.c368 uint16_t v_table; in radeon_get_vtiming_tables_addr() local
372 v_table = ((tv_uv_adr & RADEON_MAX_UV_ADR_MASK) >> RADEON_MAX_UV_ADR_SHIFT) * 2 + 1; in radeon_get_vtiming_tables_addr()
375 v_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2 + 1; in radeon_get_vtiming_tables_addr()
378 v_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2 + 1; in radeon_get_vtiming_tables_addr()
381 v_table = 0; in radeon_get_vtiming_tables_addr()
384 return v_table; in radeon_get_vtiming_tables_addr()
392 uint16_t h_table, v_table; in radeon_restore_tv_timing_tables() local
398 v_table = radeon_get_vtiming_tables_addr(tv_dac->tv.tv_uv_adr); in radeon_restore_tv_timing_tables()
406 for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2, v_table++) { in radeon_restore_tv_timing_tables()
408 radeon_legacy_tv_write_fifo(radeon_encoder, v_table, tmp); in radeon_restore_tv_timing_tables()
/drivers/regulator/
Dhi6421v530-regulator.c73 #define HI6421V530_LDO(_ID, v_table, vreg, vmask, ereg, emask, \ argument
83 .n_voltages = ARRAY_SIZE(v_table), \
84 .volt_table = v_table, \
Dhi6421-regulator.c129 #define HI6421_LDO(_id, _match, v_table, vreg, vmask, ereg, emask, \ argument
140 .n_voltages = ARRAY_SIZE(v_table), \
141 .volt_table = v_table, \
282 #define HI6421_BUCK345(_id, _match, v_table, vreg, vmask, ereg, emask, \ argument
293 .n_voltages = ARRAY_SIZE(v_table), \
294 .volt_table = v_table, \