| /drivers/gpu/drm/i915/display/ |
| D | intel_crt.c | 688 u32 vblank, vblank_start, vblank_end; in intel_crt_load_detect() local
712 vblank_end = ((vblank >> 16) & 0xfff) + 1; in intel_crt_load_detect()
740 if (vblank_start <= vactive && vblank_end >= vtotal) { in intel_crt_load_detect()
748 ((vblank_end - 1) << 16)); in intel_crt_load_detect()
752 if (vblank_start - vactive >= vtotal - vblank_end) in intel_crt_load_detect()
755 vsample = (vtotal + vblank_end) >> 1; in intel_crt_load_detect()
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | display_rq_dlg_calc_20.c | 810 unsigned int vblank_end = dst->vblank_end; in dml20_rq_dlg_get_dlg_params() local
933 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml20_rq_dlg_get_dlg_params()
1040 <= vblank_end / 2.0) in dml20_rq_dlg_get_dlg_params()
1047 <= vblank_end) in dml20_rq_dlg_get_dlg_params()
1062 vblank_end); in dml20_rq_dlg_get_dlg_params()
|
| D | display_rq_dlg_calc_20v2.c | 810 unsigned int vblank_end = dst->vblank_end; in dml20v2_rq_dlg_get_dlg_params() local
933 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml20v2_rq_dlg_get_dlg_params()
1041 <= vblank_end / 2.0) in dml20v2_rq_dlg_get_dlg_params()
1048 <= vblank_end) in dml20v2_rq_dlg_get_dlg_params()
1063 vblank_end); in dml20v2_rq_dlg_get_dlg_params()
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| D | display_rq_dlg_calc_21.c | 856 unsigned int vblank_end = dst->vblank_end; in dml_rq_dlg_get_dlg_params() local
979 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml_rq_dlg_get_dlg_params()
1080 <= vblank_end / 2.0) in dml_rq_dlg_get_dlg_params()
1087 <= vblank_end) in dml_rq_dlg_get_dlg_params()
1103 vblank_end); in dml_rq_dlg_get_dlg_params()
|
| /drivers/video/fbdev/ |
| D | gbefb.c | 522 timing->vblank_end = timing->vtotal; in compute_gbe_timing()
561 SET_GBE_FIELD(VT_VBLANK, VBLANK_OFF, val, timing->vblank_end); in gbe_set_timing_info()
573 SET_GBE_FIELD(VT_VCMAP, VCMAP_OFF, val, timing->vblank_end); in gbe_set_timing_info()
581 temp = timing->vblank_start - timing->vblank_end - 1; in gbe_set_timing_info()
625 SET_GBE_FIELD(VT_VPIXEN, VPIXEN_ON, val, timing->vblank_end); in gbe_set_timing_info()
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | display_rq_dlg_calc_30.c | 1010 unsigned int vblank_end = dst->vblank_end; in dml_rq_dlg_get_dlg_params() local
1138 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml_rq_dlg_get_dlg_params()
1229 <= vblank_end / 2.0) in dml_rq_dlg_get_dlg_params()
1236 <= vblank_end) in dml_rq_dlg_get_dlg_params()
1251 vblank_end); in dml_rq_dlg_get_dlg_params()
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | display_rq_dlg_calc_31.c | 969 unsigned int vblank_end = dst->vblank_end; in dml_rq_dlg_get_dlg_params() local
1075 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml_rq_dlg_get_dlg_params()
1143 …art / 2.0 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end / 2.0) in dml_rq_dlg_get_dlg_params()
1148 …(vstartup_start - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end) in dml_rq_dlg_get_dlg_params()
|
| /drivers/gpu/drm/amd/display/dc/dml/ |
| D | dml1_display_rq_dlg_calc.c | 1013 unsigned int vblank_end = e2e_pipe_param.pipe.dest.vblank_end; in dml1_rq_dlg_get_dlg_params() local
1160 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; /* 15 bits */ in dml1_rq_dlg_get_dlg_params()
1262 vblank_end); in dml1_rq_dlg_get_dlg_params()
|
| D | display_mode_structs.h | 345 unsigned int vblank_end; member
|
| D | display_mode_lib.c | 203 dml_print("DML PARAMS: vblank_end = %d\n", pipe_dest->vblank_end); in dml_log_pipe_params()
|
| /drivers/video/fbdev/intelfb/ |
| D | intelfbhw.c | 1048 u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive; in intelfbhw_mode_to_hw() local
1191 vblank_end = vsync_end + 1; in intelfbhw_mode_to_hw()
1195 vblank_end); in intelfbhw_mode_to_hw()
1232 vblank_end--; in intelfbhw_mode_to_hw()
1233 if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end")) in intelfbhw_mode_to_hw()
1243 (vblank_end << VSYNCEND_SHIFT); in intelfbhw_mode_to_hw()
|
| /drivers/video/fbdev/vermilion/ |
| D | vermilion.c | 770 u32 vtotal, vactive, vblank_start, vblank_end, vsync_start, vsync_end; in vmlfb_set_par_locked() local
793 vblank_end = vtotal; in vmlfb_set_par_locked()
838 ((vblank_end - 1) << 16) | (vblank_start - 1)); in vmlfb_set_par_locked()
|
| /drivers/gpu/drm/amd/display/dc/calcs/ |
| D | dcn_calcs.c | 440 input->dest.vblank_end = input->dest.vblank_start in pipe_ctx_to_e2e_pipe_params()
1248 pipe->pipe_dlg_param.vblank_end = asic_blank_end; in dcn_validate_bandwidth()
1274 hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end; in dcn_validate_bandwidth()
|
| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hubp.c | 132 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { in hubp1_vready_workaround()
|
| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hubp.c | 186 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { in hubp2_vready_at_or_After_vsync()
|
| D | dcn20_resource.c | 2057 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start in dcn20_populate_dml_pipes_from_context()
|