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Searched refs:vcn (Results 1 – 21 of 21) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Damdgpu_vcn.c82 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); in amdgpu_vcn_sw_init()
83 mutex_init(&adev->vcn.vcn_pg_lock); in amdgpu_vcn_sw_init()
84 mutex_init(&adev->vcn.vcn1_jpeg1_workaround); in amdgpu_vcn_sw_init()
85 atomic_set(&adev->vcn.total_submission_cnt, 0); in amdgpu_vcn_sw_init()
86 for (i = 0; i < adev->vcn.num_vcn_inst; i++) in amdgpu_vcn_sw_init()
87 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0); in amdgpu_vcn_sw_init()
102 adev->vcn.indirect_sram = true; in amdgpu_vcn_sw_init()
112 adev->vcn.indirect_sram = true; in amdgpu_vcn_sw_init()
118 adev->vcn.indirect_sram = true; in amdgpu_vcn_sw_init()
124 adev->vcn.indirect_sram = true; in amdgpu_vcn_sw_init()
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Dvcn_v2_5.c80 adev->vcn.num_vcn_inst = 2; in vcn_v2_5_early_init()
81 adev->vcn.harvest_config = 0; in vcn_v2_5_early_init()
82 adev->vcn.num_enc_rings = 1; in vcn_v2_5_early_init()
86 adev->vcn.num_vcn_inst = VCN25_MAX_HW_INSTANCES_ARCTURUS; in vcn_v2_5_early_init()
87 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v2_5_early_init()
90 adev->vcn.harvest_config |= 1 << i; in vcn_v2_5_early_init()
92 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | in vcn_v2_5_early_init()
97 adev->vcn.num_enc_rings = 2; in vcn_v2_5_early_init()
120 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { in vcn_v2_5_sw_init()
121 if (adev->vcn.harvest_config & (1 << j)) in vcn_v2_5_sw_init()
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Dvcn_v2_0.c72 adev->vcn.num_vcn_inst = 1; in vcn_v2_0_early_init()
74 adev->vcn.num_enc_rings = 1; in vcn_v2_0_early_init()
76 adev->vcn.num_enc_rings = 2; in vcn_v2_0_early_init()
102 &adev->vcn.inst->irq); in vcn_v2_0_sw_init()
107 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_0_sw_init()
110 &adev->vcn.inst->irq); in vcn_v2_0_sw_init()
121 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; in vcn_v2_0_sw_init()
123 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; in vcn_v2_0_sw_init()
133 ring = &adev->vcn.inst->ring_dec; in vcn_v2_0_sw_init()
136 ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1; in vcn_v2_0_sw_init()
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Dvcn_v3_0.c93 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; in vcn_v3_0_early_init()
94 adev->vcn.harvest_config = 0; in vcn_v3_0_early_init()
95 adev->vcn.num_enc_rings = 1; in vcn_v3_0_early_init()
101 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; in vcn_v3_0_early_init()
102 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v3_0_early_init()
105 adev->vcn.harvest_config |= 1 << i; in vcn_v3_0_early_init()
108 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | in vcn_v3_0_early_init()
113 adev->vcn.num_vcn_inst = 1; in vcn_v3_0_early_init()
116 adev->vcn.num_enc_rings = 0; in vcn_v3_0_early_init()
118 adev->vcn.num_enc_rings = 2; in vcn_v3_0_early_init()
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Dvcn_v1_0.c69 adev->vcn.num_vcn_inst = 1; in vcn_v1_0_early_init()
70 adev->vcn.num_enc_rings = 2; in vcn_v1_0_early_init()
96 VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq); in vcn_v1_0_sw_init()
101 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v1_0_sw_init()
103 &adev->vcn.inst->irq); in vcn_v1_0_sw_init()
113 adev->vcn.idle_work.work.func = vcn_v1_0_idle_work_handler; in vcn_v1_0_sw_init()
117 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; in vcn_v1_0_sw_init()
119 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; in vcn_v1_0_sw_init()
129 ring = &adev->vcn.inst->ring_dec; in vcn_v1_0_sw_init()
131 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, in vcn_v1_0_sw_init()
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Dvega10_reg_init.c83 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_DOORBELL64_VCN0_1; in vega10_doorbell_index_init()
84 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_DOORBELL64_VCN2_3; in vega10_doorbell_index_init()
85 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_DOORBELL64_VCN4_5; in vega10_doorbell_index_init()
86 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_DOORBELL64_VCN6_7; in vega10_doorbell_index_init()
Dvega20_reg_init.c89 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_VEGA20_DOORBELL64_VCN0_1; in vega20_doorbell_index_init()
90 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_VEGA20_DOORBELL64_VCN2_3; in vega20_doorbell_index_init()
91 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_VEGA20_DOORBELL64_VCN4_5; in vega20_doorbell_index_init()
92 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_VEGA20_DOORBELL64_VCN6_7; in vega20_doorbell_index_init()
Djpeg_v1_0.c599 bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work); in jpeg_v1_0_ring_begin_use()
602 mutex_lock(&adev->vcn.vcn1_jpeg1_workaround); in jpeg_v1_0_ring_begin_use()
604 if (amdgpu_fence_wait_empty(&adev->vcn.inst->ring_dec)) in jpeg_v1_0_ring_begin_use()
607 for (cnt = 0; cnt < adev->vcn.num_enc_rings; cnt++) { in jpeg_v1_0_ring_begin_use()
608 if (amdgpu_fence_wait_empty(&adev->vcn.inst->ring_enc[cnt])) in jpeg_v1_0_ring_begin_use()
Djpeg_v3_0.c97 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; in jpeg_v3_0_sw_init()
144 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0); in jpeg_v3_0_hw_init()
166 cancel_delayed_work_sync(&adev->vcn.idle_work); in jpeg_v3_0_hw_fini()
Damdgpu_vcn.h153 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = offset; \
154 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = value; \
Djpeg_v2_5.c115 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8 * i; in jpeg_v2_5_sw_init()
168 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i, i); in jpeg_v2_5_hw_init()
192 cancel_delayed_work_sync(&adev->vcn.idle_work); in jpeg_v2_5_hw_fini()
Djpeg_v2_0.c108 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; in jpeg_v2_0_sw_init()
155 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0); in jpeg_v2_0_hw_init()
175 cancel_delayed_work_sync(&adev->vcn.idle_work); in jpeg_v2_0_hw_fini()
Damdgpu_kms.c300 fw_info->ver = adev->vcn.fw_version; in amdgpu_firmware_info()
484 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_hw_ip_info()
488 if (adev->vcn.inst[i].ring_dec.sched.ready) in amdgpu_hw_ip_info()
496 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_hw_ip_info()
500 for (j = 0; j < adev->vcn.num_enc_rings; j++) in amdgpu_hw_ip_info()
501 if (adev->vcn.inst[i].ring_enc[j].sched.ready) in amdgpu_hw_ip_info()
Damdgpu_doorbell.h64 } vcn; member
Dnv.c978 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; in nv_init_doorbell_index()
979 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; in nv_init_doorbell_index()
980 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; in nv_init_doorbell_index()
981 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; in nv_init_doorbell_index()
Damdgpu_discovery.c303 adev->vcn.num_vcn_inst++; in amdgpu_discovery_reg_base_init()
412 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { in amdgpu_discovery_harvest_ip()
Damdgpu_virt.c542 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCN, adev->vcn.fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
Damdgpu_ucode.c534 FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version);
Damdgpu.h983 struct amdgpu_vcn vcn; member
/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dsienna_cichlid_ppt.c815 if (adev->vcn.num_vcn_inst > 1) { in sienna_cichlid_set_default_dpm_table()
854 if (adev->vcn.num_vcn_inst > 1) { in sienna_cichlid_set_default_dpm_table()
960 if (adev->vcn.num_vcn_inst > 1) { in sienna_cichlid_dpm_set_vcn_enable()
972 if (adev->vcn.num_vcn_inst > 1) { in sienna_cichlid_dpm_set_vcn_enable()
/drivers/gpu/drm/amd/pm/swsmu/
Damdgpu_smu.c1484 adev->vcn.cur_state = AMD_PG_STATE_GATE; in smu_hw_fini()