| /drivers/gpu/drm/panel/ |
| D | panel-simple.c | 251 m->hdisplay, m->vdisplay, in panel_simple_get_display_modes()
855 .vdisplay = 800,
881 .vdisplay = 272,
905 .vdisplay = 480,
955 .vdisplay = 600,
1002 .vdisplay = 768,
1025 .vdisplay = 768,
1053 .vdisplay = 768,
1082 .vdisplay = 768,
1104 .vdisplay = 1080,
[all …]
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| D | panel-arm-versatile.c | 142 .vdisplay = 240,
165 .vdisplay = 480,
187 .vdisplay = 220,
210 .vdisplay = 320,
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| D | panel-tpo-tpg110.c | 110 .vdisplay = 480,
126 .vdisplay = 480,
142 .vdisplay = 272,
158 .vdisplay = 640,
174 .vdisplay = 240,
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| D | panel-ilitek-ili9322.c | 547 .vdisplay = 240,
560 .vdisplay = 240,
574 .vdisplay = 240,
588 .vdisplay = 320,
601 .vdisplay = 360,
615 .vdisplay = 480,
629 .vdisplay = 480,
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| /drivers/gpu/drm/ |
| D | drm_modes.c | 141 int vdisplay, int vrefresh, in drm_cvt_mode() argument
161 if (!hdisplay || !vdisplay) in drm_cvt_mode()
195 vdisplay_rnd = vdisplay / 2; in drm_cvt_mode()
197 vdisplay_rnd = vdisplay; in drm_cvt_mode()
204 drm_mode->vdisplay = vdisplay + 2 * vmargin; in drm_cvt_mode()
213 if (!(vdisplay % 3) && ((vdisplay * 4 / 3) == hdisplay)) in drm_cvt_mode()
215 else if (!(vdisplay % 9) && ((vdisplay * 16 / 9) == hdisplay)) in drm_cvt_mode()
217 else if (!(vdisplay % 10) && ((vdisplay * 16 / 10) == hdisplay)) in drm_cvt_mode()
219 else if (!(vdisplay % 4) && ((vdisplay * 5 / 4) == hdisplay)) in drm_cvt_mode()
221 else if (!(vdisplay % 9) && ((vdisplay * 15 / 9) == hdisplay)) in drm_cvt_mode()
[all …]
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| /drivers/gpu/drm/tve200/ |
| D | tve200_display.c | 81 if (!(mode->hdisplay == 352 && mode->vdisplay == 240) && /* SIF(525) */ in tve200_display_check()
82 !(mode->hdisplay == 352 && mode->vdisplay == 288) && /* CIF(625) */ in tve200_display_check()
83 !(mode->hdisplay == 640 && mode->vdisplay == 480) && /* VGA */ in tve200_display_check()
84 !(mode->hdisplay == 720 && mode->vdisplay == 480) && /* D1 */ in tve200_display_check()
85 !(mode->hdisplay == 720 && mode->vdisplay == 576)) { /* D1 */ in tve200_display_check()
87 mode->hdisplay, mode->vdisplay); in tve200_display_check()
170 if ((mode->hdisplay == 352 && mode->vdisplay == 240) || /* SIF(525) */ in tve200_display_enable()
171 (mode->hdisplay == 352 && mode->vdisplay == 288)) { /* CIF(625) */ in tve200_display_enable()
174 } else if (mode->hdisplay == 640 && mode->vdisplay == 480) { in tve200_display_enable()
177 } else if ((mode->hdisplay == 720 && mode->vdisplay == 480) || in tve200_display_enable()
[all …]
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| /drivers/gpu/drm/mgag200/ |
| D | mgag200_mode.c | 357 unsigned int vdisplay, vsyncstart, vsyncend, vtotal; in mgag200_set_mode_regs() local
369 vdisplay = mode->vdisplay - 1; in mgag200_set_mode_regs()
395 ((vdisplay & 0x400) >> 8) | in mgag200_set_mode_regs()
396 ((vdisplay & 0xc00) >> 7) | in mgag200_set_mode_regs()
398 ((vdisplay & 0x400) >> 3); in mgag200_set_mode_regs()
409 ((vdisplay & 0x100) >> 7) | in mgag200_set_mode_regs()
411 ((vdisplay & 0x100) >> 5) | in mgag200_set_mode_regs()
412 ((vdisplay & 0x100) >> 4) | /* linecomp */ in mgag200_set_mode_regs()
414 ((vdisplay & 0x200) >> 3) | in mgag200_set_mode_regs()
416 WREG_CRT(9, ((vdisplay & 0x200) >> 4) | in mgag200_set_mode_regs()
[all …]
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| /drivers/gpu/drm/i915/display/ |
| D | intel_tv.c | 1020 mode->vdisplay = intel_tv_mode_vdisplay(tv_mode); in intel_tv_mode_to_mode()
1022 mode->vsync_start = mode->vdisplay + in intel_tv_mode_to_mode()
1026 mode->vtotal = mode->vdisplay + in intel_tv_mode_to_mode()
1029 mode->vsync_start = mode->vdisplay + in intel_tv_mode_to_mode()
1034 mode->vtotal = mode->vdisplay + in intel_tv_mode_to_mode()
1044 mode->hdisplay, mode->vdisplay, in intel_tv_mode_to_mode()
1067 int vdisplay, int top_margin, in intel_tv_scale_mode_vert() argument
1070 int vsync_start = mode->vsync_start - mode->vdisplay + bottom_margin; in intel_tv_scale_mode_vert()
1071 int vsync_end = mode->vsync_end - mode->vdisplay + bottom_margin; in intel_tv_scale_mode_vert()
1072 int new_vtotal = mode->vtotal * vdisplay / in intel_tv_scale_mode_vert()
[all …]
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| D | dvo_ns2501.c | 532 mode->hdisplay, mode->htotal, mode->vdisplay, mode->vtotal); in ns2501_mode_valid()
540 if ((mode->hdisplay == 640 && mode->vdisplay == 480 && mode->clock == 25175) || in ns2501_mode_valid()
541 (mode->hdisplay == 800 && mode->vdisplay == 600 && mode->clock == 40000) || in ns2501_mode_valid()
542 (mode->hdisplay == 1024 && mode->vdisplay == 768 && mode->clock == 65000)) { in ns2501_mode_valid()
559 mode->hdisplay, mode->htotal, mode->vdisplay, mode->vtotal); in ns2501_mode_set()
591 if (mode->hdisplay == 640 && mode->vdisplay == 480) in ns2501_mode_set()
593 else if (mode->hdisplay == 800 && mode->vdisplay == 600) in ns2501_mode_set()
595 else if (mode->hdisplay == 1024 && mode->vdisplay == 768) in ns2501_mode_set()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_encoders.c | 170 unsigned vblank = native_mode->vtotal - native_mode->vdisplay; in amdgpu_panel_mode_fixup()
172 unsigned vover = native_mode->vsync_start - native_mode->vdisplay; in amdgpu_panel_mode_fixup()
180 adjusted_mode->vdisplay = native_mode->vdisplay; in amdgpu_panel_mode_fixup()
186 adjusted_mode->vtotal = native_mode->vdisplay + vblank; in amdgpu_panel_mode_fixup()
187 adjusted_mode->vsync_start = native_mode->vdisplay + vover; in amdgpu_panel_mode_fixup()
193 adjusted_mode->crtc_vdisplay = native_mode->vdisplay; in amdgpu_panel_mode_fixup()
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| D | amdgpu_connectors.c | 389 native_mode->vdisplay != 0 && in amdgpu_connector_lcd_native_mode()
400 native_mode->vdisplay != 0) { in amdgpu_connector_lcd_native_mode()
408 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); in amdgpu_connector_lcd_native_mode()
457 common_modes[i].h > native_mode->vdisplay || in amdgpu_connector_add_common_modes()
459 common_modes[i].h == native_mode->vdisplay)) in amdgpu_connector_add_common_modes()
627 mode->vdisplay != native_mode->vdisplay) in amdgpu_connector_fixup_lcd_native_mode()
636 mode->vdisplay == native_mode->vdisplay) { in amdgpu_connector_fixup_lcd_native_mode()
693 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) in amdgpu_connector_lvds_mode_valid()
704 (mode->vdisplay > native_mode->vdisplay)) in amdgpu_connector_lvds_mode_valid()
710 (mode->vdisplay != native_mode->vdisplay)) in amdgpu_connector_lvds_mode_valid()
[all …]
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| /drivers/gpu/drm/nouveau/dispnv04/ |
| D | tvnv17.c | 220 mode->vdisplay == tv_norm->tv_enc_mode.vdisplay) in nv17_tv_get_ld_modes()
238 int vdisplay; in nv17_tv_get_hd_modes() member
254 modes[i].vdisplay > output_mode->vdisplay) in nv17_tv_get_hd_modes()
258 modes[i].vdisplay == output_mode->vdisplay) { in nv17_tv_get_hd_modes()
264 modes[i].vdisplay, 60, false, in nv17_tv_get_hd_modes()
278 if (output_mode->vdisplay >= 1024) { in nv17_tv_get_hd_modes()
316 mode->vdisplay > output_mode->vdisplay) in nv17_tv_mode_valid()
486 if (tv_norm->tv_enc_mode.vdisplay == 576) { in nv17_tv_mode_set()
490 } else if (tv_norm->tv_enc_mode.vdisplay == 480) { in nv17_tv_mode_set()
501 if (tv_norm->tv_enc_mode.vdisplay == 576) { in nv17_tv_mode_set()
[all …]
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| D | dfp.c | 193 mode->vdisplay > nv_connector->native_mode->vdisplay) { in nv04_dfp_mode_fixup()
314 regp->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1; in nv04_dfp_mode_set()
320 regp->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - 1; in nv04_dfp_mode_set()
336 adjusted_mode->vdisplay == output_mode->vdisplay) /* native mode */ in nv04_dfp_mode_set()
375 mode_ratio = (1 << 12) * adjusted_mode->hdisplay / adjusted_mode->vdisplay; in nv04_dfp_mode_set()
376 panel_ratio = (1 << 12) * output_mode->hdisplay / output_mode->vdisplay; in nv04_dfp_mode_set()
389 scale = (1 << 12) * adjusted_mode->vdisplay / output_mode->vdisplay; in nv04_dfp_mode_set()
395 output_mode->vdisplay * mode_ratio / (1 << 12); in nv04_dfp_mode_set()
410 diff = output_mode->vdisplay - in nv04_dfp_mode_set()
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| D | tvmodesnv17.c | 326 mode->vdisplay * id3}; in tv_setup_filter()
329 do_div(rs[1], overscan * tv_norm->tv_enc_mode.vdisplay); in tv_setup_filter()
560 vmargin = (output_mode->vdisplay - crtc_mode->vdisplay) / 2; in nv17_ctv_update_rescaler()
564 vmargin = interpolate(0, min(vmargin, output_mode->vdisplay/20), in nv17_ctv_update_rescaler()
569 vratio = crtc_mode->vdisplay * 0x800 / in nv17_ctv_update_rescaler()
570 (output_mode->vdisplay - 2*vmargin) & ~3; in nv17_ctv_update_rescaler()
575 regs->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - vmargin - 1; in nv17_ctv_update_rescaler()
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| /drivers/gpu/drm/exynos/ |
| D | exynos_hdmi.c | 933 mode->hdisplay, mode->vdisplay, in hdmi_mode_valid()
1029 m->hdisplay, m->vdisplay, in hdmi_mode_fixup()
1235 val = ((m->vsync_end - m->vdisplay) / 2); in hdmi_v13_mode_apply()
1236 val |= ((m->vsync_start - m->vdisplay) / 2) << 12; in hdmi_v13_mode_apply()
1240 val |= ((m->vtotal - m->vdisplay) / 2) << 11; in hdmi_v13_mode_apply()
1258 (m->vtotal - m->vdisplay) / 2); in hdmi_v13_mode_apply()
1259 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay / 2); in hdmi_v13_mode_apply()
1264 val |= (m->vtotal - m->vdisplay) << 11; in hdmi_v13_mode_apply()
1269 val = (m->vsync_end - m->vdisplay); in hdmi_v13_mode_apply()
1270 val |= ((m->vsync_start - m->vdisplay) << 12); in hdmi_v13_mode_apply()
[all …]
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| /drivers/gpu/drm/sun4i/ |
| D | sun4i_tv.c | 155 u32 vdisplay; member
231 .vdisplay = 480,
257 .vdisplay = 576,
313 mode->vdisplay, tv_mode->vdisplay); in sun4i_tv_find_tv_by_mode()
315 if (mode->vdisplay == tv_mode->vdisplay) in sun4i_tv_find_tv_by_mode()
336 mode->vdisplay = tv_mode->vdisplay; in sun4i_tv_mode_to_drm_mode()
337 mode->vsync_start = mode->vdisplay + tv_mode->vfront_porch; in sun4i_tv_mode_to_drm_mode()
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| /drivers/gpu/drm/radeon/ |
| D | radeon_encoders.c | 325 unsigned vblank = native_mode->vtotal - native_mode->vdisplay; in radeon_panel_mode_fixup()
327 unsigned vover = native_mode->vsync_start - native_mode->vdisplay; in radeon_panel_mode_fixup()
336 adjusted_mode->vdisplay = native_mode->vdisplay; in radeon_panel_mode_fixup()
343 adjusted_mode->vtotal = native_mode->vdisplay + vblank; in radeon_panel_mode_fixup()
344 adjusted_mode->vsync_start = native_mode->vdisplay + vover; in radeon_panel_mode_fixup()
351 adjusted_mode->crtc_vdisplay = native_mode->vdisplay; in radeon_panel_mode_fixup()
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| D | radeon_connectors.c | 473 native_mode->vdisplay != 0 && in radeon_fp_native_mode()
483 native_mode->vdisplay != 0) { in radeon_fp_native_mode()
491 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); in radeon_fp_native_mode()
538 common_modes[i].h > native_mode->vdisplay || in radeon_add_common_modes()
540 common_modes[i].h == native_mode->vdisplay)) in radeon_add_common_modes()
783 mode->vdisplay != native_mode->vdisplay) in radeon_fixup_lvds_native_mode()
792 mode->vdisplay == native_mode->vdisplay) { in radeon_fixup_lvds_native_mode()
849 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) in radeon_lvds_mode_valid()
860 (mode->vdisplay > native_mode->vdisplay)) in radeon_lvds_mode_valid()
866 (mode->vdisplay != native_mode->vdisplay)) in radeon_lvds_mode_valid()
[all …]
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| /drivers/gpu/drm/gma500/ |
| D | oaktrail_lvds.c | 134 if ((mode->vdisplay != adjusted_mode->crtc_vdisplay) || in oaktrail_lvds_mode_set()
136 if ((adjusted_mode->crtc_hdisplay * mode->vdisplay) == in oaktrail_lvds_mode_set()
140 mode->vdisplay) > (mode->hdisplay * in oaktrail_lvds_mode_set()
230 mode->vdisplay = (ti->vactive_hi << 8) | ti->vactive_lo; in oaktrail_lvds_get_configuration_mode()
240 mode->vdisplay + ((ti->vsync_offset_hi << 4) | \ in oaktrail_lvds_get_configuration_mode()
245 mode->vtotal = mode->vdisplay + \ in oaktrail_lvds_get_configuration_mode()
250 pr_info("vdisplay is %d\n", mode->vdisplay); in oaktrail_lvds_get_configuration_mode()
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| D | cdv_intel_lvds.c | 172 if (mode->vdisplay > fixed_mode->vdisplay) in cdv_intel_lvds_mode_valid()
209 adjusted_mode->vdisplay = panel_fixed_mode->vdisplay; in cdv_intel_lvds_mode_fixup()
279 mode->vdisplay != adjusted_mode->vdisplay) in cdv_intel_lvds_mode_set()
375 crtc->saved_mode.vdisplay != 0) { in cdv_intel_lvds_set_property()
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| D | psb_intel_lvds.c | 357 if (mode->vdisplay > fixed_mode->vdisplay) in psb_intel_lvds_mode_valid()
408 adjusted_mode->vdisplay = panel_fixed_mode->vdisplay; in psb_intel_lvds_mode_fixup()
477 mode->vdisplay != adjusted_mode->vdisplay) in psb_intel_lvds_mode_set()
577 crtc->saved_mode.vdisplay != 0) { in psb_intel_lvds_set_property()
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| /drivers/gpu/drm/gud/ |
| D | gud_internal.h | 127 dst->vdisplay = cpu_to_le16(src->vdisplay); in gud_from_display_mode()
145 dst->vdisplay = le16_to_cpu(src->vdisplay); in gud_to_display_mode()
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| /drivers/gpu/drm/tiny/ |
| D | simpledrm.c | 461 mode.clock = mode.hdisplay * mode.vdisplay * 60 / 1000 /* kHz */; in simpledrm_mode()
624 mode->vdisplay != sdev->mode.vdisplay) in simpledrm_simple_display_pipe_mode_valid()
628 else if (mode->vdisplay != sdev->mode.vdisplay) in simpledrm_simple_display_pipe_mode_valid()
668 memset_io(sdev->screen_base, 0, sdev->pitch * sdev->mode.vdisplay); in simpledrm_simple_display_pipe_disable()
771 dev->mode_config.min_height = mode->vdisplay; in simpledrm_device_init_modeset()
772 dev->mode_config.max_height = mode->vdisplay; in simpledrm_device_init_modeset()
784 mode->hdisplay, mode->vdisplay); in simpledrm_device_init_modeset()
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| /drivers/gpu/drm/virtio/ |
| D | virtgpu_display.c | 93 crtc->mode.vdisplay, 0, 0); in virtio_gpu_crtc_mode_set_nofb()
204 if (mode->hdisplay == XRES_DEF && mode->vdisplay == YRES_DEF) in virtio_gpu_conn_mode_valid()
207 mode->vdisplay <= height && mode->vdisplay >= height - 16) in virtio_gpu_conn_mode_valid()
210 DRM_DEBUG("del mode: %dx%d\n", mode->hdisplay, mode->vdisplay); in virtio_gpu_conn_mode_valid()
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| /drivers/gpu/drm/hisilicon/hibmc/ |
| D | hibmc_drm_de.c | 34 u64 vdisplay; member
89 crtc_state->adjusted_mode.vdisplay) { in hibmc_plane_atomic_check()
225 hibmc_pll_table[i].vdisplay == mode->vdisplay) in hibmc_crtc_mode_valid()
291 hibmc_pll_table[i].vdisplay == y) { in get_pll_config()
320 y = mode->vdisplay; in display_ctrl_adjust()
379 HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_DISP_END, mode->vdisplay - 1), in hibmc_crtc_mode_set_nofb()
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