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Searched refs:vsc (Results 1 – 25 of 32) sorted by relevance

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/drivers/net/dsa/
Dvitesse-vsc73xx-core.c376 static int vsc73xx_read(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, in vsc73xx_read() argument
379 return vsc->ops->read(vsc, block, subblock, reg, val); in vsc73xx_read()
382 static int vsc73xx_write(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, in vsc73xx_write() argument
385 return vsc->ops->write(vsc, block, subblock, reg, val); in vsc73xx_write()
388 static int vsc73xx_update_bits(struct vsc73xx *vsc, u8 block, u8 subblock, in vsc73xx_update_bits() argument
395 ret = vsc73xx_read(vsc, block, subblock, reg, &orig); in vsc73xx_update_bits()
400 return vsc73xx_write(vsc, block, subblock, reg, tmp); in vsc73xx_update_bits()
403 static int vsc73xx_detect(struct vsc73xx *vsc) in vsc73xx_detect() argument
412 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, in vsc73xx_detect()
415 dev_err(vsc->dev, "unable to read mailbox (%d)\n", ret); in vsc73xx_detect()
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Dvitesse-vsc73xx-platform.c37 struct vsc73xx vsc; member
55 static int vsc73xx_platform_read(struct vsc73xx *vsc, u8 block, u8 subblock, in vsc73xx_platform_read() argument
58 struct vsc73xx_platform *vsc_platform = vsc->priv; in vsc73xx_platform_read()
73 static int vsc73xx_platform_write(struct vsc73xx *vsc, u8 block, u8 subblock, in vsc73xx_platform_write() argument
76 struct vsc73xx_platform *vsc_platform = vsc->priv; in vsc73xx_platform_write()
100 vsc_platform->vsc.dev = dev; in vsc73xx_platform_probe()
101 vsc_platform->vsc.priv = vsc_platform; in vsc73xx_platform_probe()
102 vsc_platform->vsc.ops = &vsc73xx_platform_ops; in vsc73xx_platform_probe()
112 return vsc73xx_probe(&vsc_platform->vsc); in vsc73xx_platform_probe()
122 vsc73xx_remove(&vsc_platform->vsc); in vsc73xx_platform_remove()
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Dvitesse-vsc73xx-spi.c35 struct vsc73xx vsc; member
52 static int vsc73xx_spi_read(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, in vsc73xx_spi_read() argument
55 struct vsc73xx_spi *vsc_spi = vsc->priv; in vsc73xx_spi_read()
94 static int vsc73xx_spi_write(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, in vsc73xx_spi_write() argument
97 struct vsc73xx_spi *vsc_spi = vsc->priv; in vsc73xx_spi_write()
146 vsc_spi->vsc.dev = dev; in vsc73xx_spi_probe()
147 vsc_spi->vsc.priv = vsc_spi; in vsc73xx_spi_probe()
148 vsc_spi->vsc.ops = &vsc73xx_spi_ops; in vsc73xx_spi_probe()
159 return vsc73xx_probe(&vsc_spi->vsc); in vsc73xx_spi_probe()
169 vsc73xx_remove(&vsc_spi->vsc); in vsc73xx_spi_remove()
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Dvitesse-vsc73xx.h21 int (*read)(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg,
23 int (*write)(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg,
28 int vsc73xx_probe(struct vsc73xx *vsc);
29 int vsc73xx_remove(struct vsc73xx *vsc);
30 void vsc73xx_shutdown(struct vsc73xx *vsc);
/drivers/gpu/drm/i915/display/
Dintel_dp.c1466 struct drm_dp_vsc_sdp *vsc) in intel_dp_compute_vsc_colorimetry() argument
1476 vsc->revision = 0x5; in intel_dp_compute_vsc_colorimetry()
1477 vsc->length = 0x13; in intel_dp_compute_vsc_colorimetry()
1482 vsc->pixelformat = DP_PIXELFORMAT_YUV444; in intel_dp_compute_vsc_colorimetry()
1485 vsc->pixelformat = DP_PIXELFORMAT_YUV420; in intel_dp_compute_vsc_colorimetry()
1489 vsc->pixelformat = DP_PIXELFORMAT_RGB; in intel_dp_compute_vsc_colorimetry()
1494 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; in intel_dp_compute_vsc_colorimetry()
1497 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601; in intel_dp_compute_vsc_colorimetry()
1500 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709; in intel_dp_compute_vsc_colorimetry()
1503 vsc->colorimetry = DP_COLORIMETRY_SYCC_601; in intel_dp_compute_vsc_colorimetry()
[all …]
Dintel_dp.h87 struct drm_dp_vsc_sdp *vsc);
90 struct drm_dp_vsc_sdp *vsc);
Dintel_display_types.h1169 struct drm_dp_vsc_sdp vsc; member
1534 struct drm_dp_vsc_sdp vsc; member
/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_reg.c952 struct dp_sdp *vsc, bool blocking) in analogix_dp_send_psr_spd() argument
968 writel(vsc->sdp_header.HB0, dp->reg_base + ANALOGIX_DP_SPD_HB0); in analogix_dp_send_psr_spd()
969 writel(vsc->sdp_header.HB1, dp->reg_base + ANALOGIX_DP_SPD_HB1); in analogix_dp_send_psr_spd()
970 writel(vsc->sdp_header.HB2, dp->reg_base + ANALOGIX_DP_SPD_HB2); in analogix_dp_send_psr_spd()
971 writel(vsc->sdp_header.HB3, dp->reg_base + ANALOGIX_DP_SPD_HB3); in analogix_dp_send_psr_spd()
980 writel(vsc->db[0], dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB0); in analogix_dp_send_psr_spd()
981 writel(vsc->db[1], dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB1); in analogix_dp_send_psr_spd()
1012 ((vsc->db[1] && psr_status == DP_PSR_SINK_ACTIVE_RFB) || in analogix_dp_send_psr_spd()
1013 (!vsc->db[1] && (psr_status == DP_PSR_SINK_ACTIVE_RESYNC || in analogix_dp_send_psr_spd()
Danalogix_dp_core.h255 struct dp_sdp *vsc, bool blocking);
/drivers/gpu/drm/
Ddrm_dp_helper.c2559 const struct drm_dp_vsc_sdp *vsc) in drm_dp_vsc_sdp_log() argument
2563 vsc->revision, vsc->length); in drm_dp_vsc_sdp_log()
2565 dp_pixelformat_get_name(vsc->pixelformat)); in drm_dp_vsc_sdp_log()
2567 dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry)); in drm_dp_vsc_sdp_log()
2568 DP_SDP_LOG(" bpc: %u\n", vsc->bpc); in drm_dp_vsc_sdp_log()
2570 dp_dynamic_range_get_name(vsc->dynamic_range)); in drm_dp_vsc_sdp_log()
2572 dp_content_type_get_name(vsc->content_type)); in drm_dp_vsc_sdp_log()
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dio_stream_encoder.c428 if (info_frame->vsc.valid) { in enc3_stream_encoder_update_dp_info_packets()
432 &info_frame->vsc); in enc3_stream_encoder_update_dp_info_packets()
453 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); in enc3_stream_encoder_update_dp_info_packets()
/drivers/gpu/drm/amd/display/dc/inc/hw/
Dstream_encoder.h83 struct dc_info_packet vsc; member
/drivers/gpu/drm/amd/amdgpu/
Ddce_v8_0.c640 fixed20_12 vsc; /* vertical scale ratio */ member
811 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce_v8_0_average_bandwidth()
846 if ((wm->vsc.full > a.full) || in dce_v8_0_latency_watermark()
847 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce_v8_0_latency_watermark()
849 ((wm->vsc.full >= a.full) && wm->interlaced)) in dce_v8_0_latency_watermark()
934 if (wm->vsc.full > a.full) in dce_v8_0_check_latency_hiding()
998 wm_high.vsc = amdgpu_crtc->vsc; in dce_v8_0_program_watermarks()
1037 wm_low.vsc = amdgpu_crtc->vsc; in dce_v8_0_program_watermarks()
Ddce_v6_0.c503 fixed20_12 vsc; /* vertical scale ratio */ member
674 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce_v6_0_average_bandwidth()
709 if ((wm->vsc.full > a.full) || in dce_v6_0_latency_watermark()
710 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce_v6_0_latency_watermark()
712 ((wm->vsc.full >= a.full) && wm->interlaced)) in dce_v6_0_latency_watermark()
797 if (wm->vsc.full > a.full) in dce_v6_0_check_latency_hiding()
870 wm_high.vsc = amdgpu_crtc->vsc; in dce_v6_0_program_watermarks()
897 wm_low.vsc = amdgpu_crtc->vsc; in dce_v6_0_program_watermarks()
Ddce_v10_0.c705 fixed20_12 vsc; /* vertical scale ratio */ member
876 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce_v10_0_average_bandwidth()
911 if ((wm->vsc.full > a.full) || in dce_v10_0_latency_watermark()
912 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce_v10_0_latency_watermark()
914 ((wm->vsc.full >= a.full) && wm->interlaced)) in dce_v10_0_latency_watermark()
999 if (wm->vsc.full > a.full) in dce_v10_0_check_latency_hiding()
1063 wm_high.vsc = amdgpu_crtc->vsc; in dce_v10_0_program_watermarks()
1102 wm_low.vsc = amdgpu_crtc->vsc; in dce_v10_0_program_watermarks()
Ddce_v11_0.c731 fixed20_12 vsc; /* vertical scale ratio */ member
902 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce_v11_0_average_bandwidth()
937 if ((wm->vsc.full > a.full) || in dce_v11_0_latency_watermark()
938 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce_v11_0_latency_watermark()
940 ((wm->vsc.full >= a.full) && wm->interlaced)) in dce_v11_0_latency_watermark()
1025 if (wm->vsc.full > a.full) in dce_v11_0_check_latency_hiding()
1089 wm_high.vsc = amdgpu_crtc->vsc; in dce_v11_0_program_watermarks()
1128 wm_low.vsc = amdgpu_crtc->vsc; in dce_v11_0_program_watermarks()
Damdgpu_mode.h403 fixed20_12 vsc; member
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_stream_encoder.c723 if (info_frame->vsc.valid) in enc1_stream_encoder_update_dp_info_packets()
727 &info_frame->vsc); in enc1_stream_encoder_update_dp_info_packets()
748 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); in enc1_stream_encoder_update_dp_info_packets()
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_stream_encoder.c857 if (info_frame->vsc.valid) in dce110_stream_encoder_update_dp_info_packets()
861 &info_frame->vsc); in dce110_stream_encoder_update_dp_info_packets()
878 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); in dce110_stream_encoder_update_dp_info_packets()
/drivers/gpu/drm/radeon/
Drs690.c305 if (crtc->vsc.full > dfixed_const(2)) in rs690_crtc_bandwidth_compute()
333 if (crtc->vsc.full > b.full) in rs690_crtc_bandwidth_compute()
334 b.full = crtc->vsc.full; in rs690_crtc_bandwidth_compute()
Devergreen.c1941 fixed20_12 vsc; /* vertical scale ratio */ member
2056 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in evergreen_average_bandwidth()
2081 if ((wm->vsc.full > a.full) || in evergreen_latency_watermark()
2082 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in evergreen_latency_watermark()
2084 ((wm->vsc.full >= a.full) && wm->interlaced)) in evergreen_latency_watermark()
2136 if (wm->vsc.full > a.full) in evergreen_check_latency_hiding()
2198 wm_high.vsc = radeon_crtc->vsc; in evergreen_program_watermarks()
2225 wm_low.vsc = radeon_crtc->vsc; in evergreen_program_watermarks()
Drv515.c953 if (crtc->vsc.full > dfixed_const(2)) in rv515_crtc_bandwidth_compute()
981 if (crtc->vsc.full > b.full) in rv515_crtc_bandwidth_compute()
982 b.full = crtc->vsc.full; in rv515_crtc_bandwidth_compute()
Dsi.c2061 fixed20_12 vsc; /* vertical scale ratio */ member
2193 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce6_average_bandwidth()
2219 if ((wm->vsc.full > a.full) || in dce6_latency_watermark()
2220 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce6_latency_watermark()
2222 ((wm->vsc.full >= a.full) && wm->interlaced)) in dce6_latency_watermark()
2276 if (wm->vsc.full > a.full) in dce6_check_latency_hiding()
2341 wm_high.vsc = radeon_crtc->vsc; in dce6_program_watermarks()
2368 wm_low.vsc = radeon_crtc->vsc; in dce6_program_watermarks()
Dcik.c8907 fixed20_12 vsc; /* vertical scale ratio */ member
9078 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce8_average_bandwidth()
9113 if ((wm->vsc.full > a.full) || in dce8_latency_watermark()
9114 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce8_latency_watermark()
9116 ((wm->vsc.full >= a.full) && wm->interlaced)) in dce8_latency_watermark()
9201 if (wm->vsc.full > a.full) in dce8_check_latency_hiding()
9266 wm_high.vsc = radeon_crtc->vsc; in dce8_program_watermarks()
9306 wm_low.vsc = radeon_crtc->vsc; in dce8_program_watermarks()
/drivers/video/fbdev/
Dcg14.c123 u16 vsc; /* Vert Sync Clear */ member

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