Home
last modified time | relevance | path

Searched refs:wb_info (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_hwseq.c221 struct dc_writeback_info *wb_info, in dcn30_set_writeback() argument
227 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); in dcn30_set_writeback()
228 ASSERT(wb_info->wb_enabled); in dcn30_set_writeback()
229 ASSERT(wb_info->mpcc_inst >= 0); in dcn30_set_writeback()
230 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count); in dcn30_set_writeback()
231 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; in dcn30_set_writeback()
232 mcif_buf_params = &wb_info->mcif_buf_params; in dcn30_set_writeback()
236 wb_info->dwb_pipe_inst, wb_info->mpcc_inst); in dcn30_set_writeback()
238 mcif_wb->funcs->config_mcif_buf(mcif_wb, mcif_buf_params, wb_info->dwb_params.dest_height); in dcn30_set_writeback()
239 …mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info-… in dcn30_set_writeback()
[all …]
Ddcn30_hwseq.h40 struct dc_writeback_info *wb_info,
44 struct dc_writeback_info *wb_info,
53 struct dc_writeback_info *wb_info);
Ddcn30_resource.c1499 struct dc_writeback_info *wb_info = &stream->writeback_info[j]; in dcn30_populate_dml_writeback_from_context() local
1501 if (wb_info->wb_enabled && wb_info->writeback_source_plane && in dcn30_populate_dml_writeback_from_context()
1502 (wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) { in dcn30_populate_dml_writeback_from_context()
1505 dout_wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_en ? in dcn30_populate_dml_writeback_from_context()
1506 wb_info->dwb_params.cnv_params.crop_height : in dcn30_populate_dml_writeback_from_context()
1507 wb_info->dwb_params.cnv_params.src_height; in dcn30_populate_dml_writeback_from_context()
1508 dout_wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_en ? in dcn30_populate_dml_writeback_from_context()
1509 wb_info->dwb_params.cnv_params.crop_width : in dcn30_populate_dml_writeback_from_context()
1510 wb_info->dwb_params.cnv_params.src_width; in dcn30_populate_dml_writeback_from_context()
1511 dout_wb.wb_dst_width = wb_info->dwb_params.dest_width; in dcn30_populate_dml_writeback_from_context()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn2x/
Ddcn2x.c73 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0]; in dcn20_populate_dml_writeback_from_context() local
79 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0; in dcn20_populate_dml_writeback_from_context()
81 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height; in dcn20_populate_dml_writeback_from_context()
82 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width; in dcn20_populate_dml_writeback_from_context()
83 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width; in dcn20_populate_dml_writeback_from_context()
84 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height; in dcn20_populate_dml_writeback_from_context()
87 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c; in dcn20_populate_dml_writeback_from_context()
88 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c; in dcn20_populate_dml_writeback_from_context()
91 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) { in dcn20_populate_dml_writeback_from_context()
92 if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC) in dcn20_populate_dml_writeback_from_context()
/drivers/gpu/drm/amd/display/dc/core/
Ddc_stream.c429 struct dc_writeback_info *wb_info) in dc_stream_add_writeback() argument
440 if (wb_info == NULL) { in dc_stream_add_writeback()
445 if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) { in dc_stream_add_writeback()
450 wb_info->dwb_params.out_transfer_func = stream->out_transfer_func; in dc_stream_add_writeback()
452 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
460 stream->writeback_info[i].dwb_pipe_inst == wb_info->dwb_pipe_inst) { in dc_stream_add_writeback()
461 stream->writeback_info[i] = *wb_info; in dc_stream_add_writeback()
467 stream->writeback_info[stream->num_wb_info++] = *wb_info; in dc_stream_add_writeback()
472 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
483 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
[all …]
/drivers/gpu/drm/amd/display/dc/inc/
Dhw_sequencer.h170 struct dc_writeback_info *wb_info,
173 struct dc_writeback_info *wb_info,
180 struct dc_writeback_info *wb_info);
/drivers/gpu/drm/amd/display/dc/
Ddc_stream.h393 struct dc_writeback_info *wb_info);
405 struct dc_writeback_info *wb_info);
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hwseq.h106 struct dc_writeback_info *wb_info,
Ddcn20_hwseq.c1931 struct dc_writeback_info *wb_info, in dcn20_enable_writeback() argument
1938 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); in dcn20_enable_writeback()
1939 ASSERT(wb_info->wb_enabled); in dcn20_enable_writeback()
1940 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn20_enable_writeback()
1941 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; in dcn20_enable_writeback()
1945 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); in dcn20_enable_writeback()
1947 …mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_heigh… in dcn20_enable_writeback()
1948 …mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info-… in dcn20_enable_writeback()
1952 dwb->funcs->enable(dwb, &wb_info->dwb_params); in dcn20_enable_writeback()