Searched refs:wm_clk_ranges (Results 1 – 4 of 4) sorted by relevance
1000 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; in bw_calcs_data_update_from_pplib()1001 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = in bw_calcs_data_update_from_pplib()1003 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = in bw_calcs_data_update_from_pplib()1005 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz = in bw_calcs_data_update_from_pplib()1007 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = in bw_calcs_data_update_from_pplib()1010 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; in bw_calcs_data_update_from_pplib()1011 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = in bw_calcs_data_update_from_pplib()1014 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; in bw_calcs_data_update_from_pplib()1015 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz = in bw_calcs_data_update_from_pplib()1017 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = in bw_calcs_data_update_from_pplib()[all …]
1163 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; in bw_calcs_data_update_from_pplib()1164 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = in bw_calcs_data_update_from_pplib()1166 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = in bw_calcs_data_update_from_pplib()1168 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz = in bw_calcs_data_update_from_pplib()1170 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = in bw_calcs_data_update_from_pplib()1173 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; in bw_calcs_data_update_from_pplib()1174 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = in bw_calcs_data_update_from_pplib()1177 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; in bw_calcs_data_update_from_pplib()1178 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz = in bw_calcs_data_update_from_pplib()1180 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = in bw_calcs_data_update_from_pplib()[all …]
154 struct dm_pp_clock_range_for_wm_set wm_clk_ranges[MAX_WM_SETS]; member
5294 if (dep_sclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_eng_clk_in_khz / 10 && in smu7_set_watermarks_for_clocks_ranges()5295 dep_sclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_eng_clk_in_khz / 10 && in smu7_set_watermarks_for_clocks_ranges()5296 dep_mclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_mem_clk_in_khz / 10 && in smu7_set_watermarks_for_clocks_ranges()5297 dep_mclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_mem_clk_in_khz / 10) { in smu7_set_watermarks_for_clocks_ranges()5299 table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k].wm_set_id; in smu7_set_watermarks_for_clocks_ranges()5305 table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k - 1].wm_set_id); in smu7_set_watermarks_for_clocks_ranges()