1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Definitions for the NVM Express interface
4 * Copyright (c) 2011-2014, Intel Corporation.
5 */
6
7 #ifndef _LINUX_NVME_H
8 #define _LINUX_NVME_H
9
10 #include <linux/bits.h>
11 #include <linux/types.h>
12 #include <linux/uuid.h>
13
14 /* NQN names in commands fields specified one size */
15 #define NVMF_NQN_FIELD_LEN 256
16
17 /* However the max length of a qualified name is another size */
18 #define NVMF_NQN_SIZE 223
19
20 #define NVMF_TRSVCID_SIZE 32
21 #define NVMF_TRADDR_SIZE 256
22 #define NVMF_TSAS_SIZE 256
23
24 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
25
26 #define NVME_RDMA_IP_PORT 4420
27
28 #define NVME_NSID_ALL 0xffffffff
29
30 enum nvme_subsys_type {
31 NVME_NQN_DISC = 1, /* Discovery type target subsystem */
32 NVME_NQN_NVME = 2, /* NVME type target subsystem */
33 };
34
35 /* Address Family codes for Discovery Log Page entry ADRFAM field */
36 enum {
37 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
38 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
39 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
40 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
41 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
42 NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */
43 NVMF_ADDR_FAMILY_MAX,
44 };
45
46 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
47 enum {
48 NVMF_TRTYPE_RDMA = 1, /* RDMA */
49 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
50 NVMF_TRTYPE_TCP = 3, /* TCP/IP */
51 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
52 NVMF_TRTYPE_MAX,
53 };
54
55 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
56 enum {
57 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
58 NVMF_TREQ_REQUIRED = 1, /* Required */
59 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
60 #define NVME_TREQ_SECURE_CHANNEL_MASK \
61 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
62
63 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
64 };
65
66 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
67 * RDMA_QPTYPE field
68 */
69 enum {
70 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
71 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
72 };
73
74 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
75 * RDMA_QPTYPE field
76 */
77 enum {
78 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
79 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
80 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
81 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
82 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
83 };
84
85 /* RDMA Connection Management Service Type codes for Discovery Log Page
86 * entry TSAS RDMA_CMS field
87 */
88 enum {
89 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
90 };
91
92 #define NVME_AQ_DEPTH 32
93 #define NVME_NR_AEN_COMMANDS 1
94 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
95
96 /*
97 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
98 * NVM-Express 1.2 specification, section 4.1.2.
99 */
100 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
101
102 enum {
103 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
104 NVME_REG_VS = 0x0008, /* Version */
105 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
106 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
107 NVME_REG_CC = 0x0014, /* Controller Configuration */
108 NVME_REG_CSTS = 0x001c, /* Controller Status */
109 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
110 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
111 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
112 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
113 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
114 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
115 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
116 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
117 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
118 * Location
119 */
120 NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory
121 * Space Control
122 */
123 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
124 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
125 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
126 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
127 * Buffer Size
128 */
129 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
130 * Write Throughput
131 */
132 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
133 };
134
135 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
136 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
137 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
138 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
139 #define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff)
140 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
141 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
142 #define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1)
143
144 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
145 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
146
147 enum {
148 NVME_CMBSZ_SQS = 1 << 0,
149 NVME_CMBSZ_CQS = 1 << 1,
150 NVME_CMBSZ_LISTS = 1 << 2,
151 NVME_CMBSZ_RDS = 1 << 3,
152 NVME_CMBSZ_WDS = 1 << 4,
153
154 NVME_CMBSZ_SZ_SHIFT = 12,
155 NVME_CMBSZ_SZ_MASK = 0xfffff,
156
157 NVME_CMBSZ_SZU_SHIFT = 8,
158 NVME_CMBSZ_SZU_MASK = 0xf,
159 };
160
161 /*
162 * Submission and Completion Queue Entry Sizes for the NVM command set.
163 * (In bytes and specified as a power of two (2^n)).
164 */
165 #define NVME_ADM_SQES 6
166 #define NVME_NVM_IOSQES 6
167 #define NVME_NVM_IOCQES 4
168
169 enum {
170 NVME_CC_ENABLE = 1 << 0,
171 NVME_CC_EN_SHIFT = 0,
172 NVME_CC_CSS_SHIFT = 4,
173 NVME_CC_MPS_SHIFT = 7,
174 NVME_CC_AMS_SHIFT = 11,
175 NVME_CC_SHN_SHIFT = 14,
176 NVME_CC_IOSQES_SHIFT = 16,
177 NVME_CC_IOCQES_SHIFT = 20,
178 NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT,
179 NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT,
180 NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT,
181 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
182 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
183 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
184 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
185 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
186 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
187 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
188 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
189 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
190 NVME_CAP_CSS_NVM = 1 << 0,
191 NVME_CAP_CSS_CSI = 1 << 6,
192 NVME_CSTS_RDY = 1 << 0,
193 NVME_CSTS_CFS = 1 << 1,
194 NVME_CSTS_NSSRO = 1 << 4,
195 NVME_CSTS_PP = 1 << 5,
196 NVME_CSTS_SHST_NORMAL = 0 << 2,
197 NVME_CSTS_SHST_OCCUR = 1 << 2,
198 NVME_CSTS_SHST_CMPLT = 2 << 2,
199 NVME_CSTS_SHST_MASK = 3 << 2,
200 NVME_CMBMSC_CRE = 1 << 0,
201 NVME_CMBMSC_CMSE = 1 << 1,
202 };
203
204 struct nvme_id_power_state {
205 __le16 max_power; /* centiwatts */
206 __u8 rsvd2;
207 __u8 flags;
208 __le32 entry_lat; /* microseconds */
209 __le32 exit_lat; /* microseconds */
210 __u8 read_tput;
211 __u8 read_lat;
212 __u8 write_tput;
213 __u8 write_lat;
214 __le16 idle_power;
215 __u8 idle_scale;
216 __u8 rsvd19;
217 __le16 active_power;
218 __u8 active_work_scale;
219 __u8 rsvd23[9];
220 };
221
222 enum {
223 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
224 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
225 };
226
227 enum nvme_ctrl_attr {
228 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
229 NVME_CTRL_ATTR_TBKAS = (1 << 6),
230 };
231
232 struct nvme_id_ctrl {
233 __le16 vid;
234 __le16 ssvid;
235 char sn[20];
236 char mn[40];
237 char fr[8];
238 __u8 rab;
239 __u8 ieee[3];
240 __u8 cmic;
241 __u8 mdts;
242 __le16 cntlid;
243 __le32 ver;
244 __le32 rtd3r;
245 __le32 rtd3e;
246 __le32 oaes;
247 __le32 ctratt;
248 __u8 rsvd100[28];
249 __le16 crdt1;
250 __le16 crdt2;
251 __le16 crdt3;
252 __u8 rsvd134[122];
253 __le16 oacs;
254 __u8 acl;
255 __u8 aerl;
256 __u8 frmw;
257 __u8 lpa;
258 __u8 elpe;
259 __u8 npss;
260 __u8 avscc;
261 __u8 apsta;
262 __le16 wctemp;
263 __le16 cctemp;
264 __le16 mtfa;
265 __le32 hmpre;
266 __le32 hmmin;
267 __u8 tnvmcap[16];
268 __u8 unvmcap[16];
269 __le32 rpmbs;
270 __le16 edstt;
271 __u8 dsto;
272 __u8 fwug;
273 __le16 kas;
274 __le16 hctma;
275 __le16 mntmt;
276 __le16 mxtmt;
277 __le32 sanicap;
278 __le32 hmminds;
279 __le16 hmmaxd;
280 __u8 rsvd338[4];
281 __u8 anatt;
282 __u8 anacap;
283 __le32 anagrpmax;
284 __le32 nanagrpid;
285 __u8 rsvd352[160];
286 __u8 sqes;
287 __u8 cqes;
288 __le16 maxcmd;
289 __le32 nn;
290 __le16 oncs;
291 __le16 fuses;
292 __u8 fna;
293 __u8 vwc;
294 __le16 awun;
295 __le16 awupf;
296 __u8 nvscc;
297 __u8 nwpc;
298 __le16 acwu;
299 __u8 rsvd534[2];
300 __le32 sgls;
301 __le32 mnan;
302 __u8 rsvd544[224];
303 char subnqn[256];
304 __u8 rsvd1024[768];
305 __le32 ioccsz;
306 __le32 iorcsz;
307 __le16 icdoff;
308 __u8 ctrattr;
309 __u8 msdbd;
310 __u8 rsvd1804[244];
311 struct nvme_id_power_state psd[32];
312 __u8 vs[1024];
313 };
314
315 enum {
316 NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1,
317 NVME_CTRL_CMIC_ANA = 1 << 3,
318 NVME_CTRL_ONCS_COMPARE = 1 << 0,
319 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
320 NVME_CTRL_ONCS_DSM = 1 << 2,
321 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
322 NVME_CTRL_ONCS_RESERVATIONS = 1 << 5,
323 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
324 NVME_CTRL_VWC_PRESENT = 1 << 0,
325 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
326 NVME_CTRL_OACS_NS_MNGT_SUPP = 1 << 3,
327 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
328 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
329 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
330 NVME_CTRL_CTRATT_128_ID = 1 << 0,
331 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
332 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
333 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
334 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
335 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
336 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
337 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
338 };
339
340 struct nvme_lbaf {
341 __le16 ms;
342 __u8 ds;
343 __u8 rp;
344 };
345
346 struct nvme_id_ns {
347 __le64 nsze;
348 __le64 ncap;
349 __le64 nuse;
350 __u8 nsfeat;
351 __u8 nlbaf;
352 __u8 flbas;
353 __u8 mc;
354 __u8 dpc;
355 __u8 dps;
356 __u8 nmic;
357 __u8 rescap;
358 __u8 fpi;
359 __u8 dlfeat;
360 __le16 nawun;
361 __le16 nawupf;
362 __le16 nacwu;
363 __le16 nabsn;
364 __le16 nabo;
365 __le16 nabspf;
366 __le16 noiob;
367 __u8 nvmcap[16];
368 __le16 npwg;
369 __le16 npwa;
370 __le16 npdg;
371 __le16 npda;
372 __le16 nows;
373 __u8 rsvd74[18];
374 __le32 anagrpid;
375 __u8 rsvd96[3];
376 __u8 nsattr;
377 __le16 nvmsetid;
378 __le16 endgid;
379 __u8 nguid[16];
380 __u8 eui64[8];
381 struct nvme_lbaf lbaf[16];
382 __u8 rsvd192[192];
383 __u8 vs[3712];
384 };
385
386 struct nvme_zns_lbafe {
387 __le64 zsze;
388 __u8 zdes;
389 __u8 rsvd9[7];
390 };
391
392 struct nvme_id_ns_zns {
393 __le16 zoc;
394 __le16 ozcs;
395 __le32 mar;
396 __le32 mor;
397 __le32 rrl;
398 __le32 frl;
399 __u8 rsvd20[2796];
400 struct nvme_zns_lbafe lbafe[16];
401 __u8 rsvd3072[768];
402 __u8 vs[256];
403 };
404
405 struct nvme_id_ctrl_zns {
406 __u8 zasl;
407 __u8 rsvd1[4095];
408 };
409
410 struct nvme_id_ctrl_nvm {
411 __u8 vsl;
412 __u8 wzsl;
413 __u8 wusl;
414 __u8 dmrl;
415 __le32 dmrsl;
416 __le64 dmsl;
417 __u8 rsvd16[4080];
418 };
419
420 enum {
421 NVME_ID_CNS_NS = 0x00,
422 NVME_ID_CNS_CTRL = 0x01,
423 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
424 NVME_ID_CNS_NS_DESC_LIST = 0x03,
425 NVME_ID_CNS_CS_NS = 0x05,
426 NVME_ID_CNS_CS_CTRL = 0x06,
427 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
428 NVME_ID_CNS_NS_PRESENT = 0x11,
429 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
430 NVME_ID_CNS_CTRL_LIST = 0x13,
431 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
432 NVME_ID_CNS_NS_GRANULARITY = 0x16,
433 NVME_ID_CNS_UUID_LIST = 0x17,
434 };
435
436 enum {
437 NVME_CSI_NVM = 0,
438 NVME_CSI_ZNS = 2,
439 };
440
441 enum {
442 NVME_DIR_IDENTIFY = 0x00,
443 NVME_DIR_STREAMS = 0x01,
444 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
445 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
446 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
447 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
448 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
449 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
450 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
451 NVME_DIR_ENDIR = 0x01,
452 };
453
454 enum {
455 NVME_NS_FEAT_THIN = 1 << 0,
456 NVME_NS_FEAT_ATOMICS = 1 << 1,
457 NVME_NS_FEAT_IO_OPT = 1 << 4,
458 NVME_NS_ATTR_RO = 1 << 0,
459 NVME_NS_FLBAS_LBA_MASK = 0xf,
460 NVME_NS_FLBAS_META_EXT = 0x10,
461 NVME_NS_NMIC_SHARED = 1 << 0,
462 NVME_LBAF_RP_BEST = 0,
463 NVME_LBAF_RP_BETTER = 1,
464 NVME_LBAF_RP_GOOD = 2,
465 NVME_LBAF_RP_DEGRADED = 3,
466 NVME_NS_DPC_PI_LAST = 1 << 4,
467 NVME_NS_DPC_PI_FIRST = 1 << 3,
468 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
469 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
470 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
471 NVME_NS_DPS_PI_FIRST = 1 << 3,
472 NVME_NS_DPS_PI_MASK = 0x7,
473 NVME_NS_DPS_PI_TYPE1 = 1,
474 NVME_NS_DPS_PI_TYPE2 = 2,
475 NVME_NS_DPS_PI_TYPE3 = 3,
476 };
477
478 /* Identify Namespace Metadata Capabilities (MC): */
479 enum {
480 NVME_MC_EXTENDED_LBA = (1 << 0),
481 NVME_MC_METADATA_PTR = (1 << 1),
482 };
483
484 struct nvme_ns_id_desc {
485 __u8 nidt;
486 __u8 nidl;
487 __le16 reserved;
488 };
489
490 #define NVME_NIDT_EUI64_LEN 8
491 #define NVME_NIDT_NGUID_LEN 16
492 #define NVME_NIDT_UUID_LEN 16
493 #define NVME_NIDT_CSI_LEN 1
494
495 enum {
496 NVME_NIDT_EUI64 = 0x01,
497 NVME_NIDT_NGUID = 0x02,
498 NVME_NIDT_UUID = 0x03,
499 NVME_NIDT_CSI = 0x04,
500 };
501
502 struct nvme_smart_log {
503 __u8 critical_warning;
504 __u8 temperature[2];
505 __u8 avail_spare;
506 __u8 spare_thresh;
507 __u8 percent_used;
508 __u8 endu_grp_crit_warn_sumry;
509 __u8 rsvd7[25];
510 __u8 data_units_read[16];
511 __u8 data_units_written[16];
512 __u8 host_reads[16];
513 __u8 host_writes[16];
514 __u8 ctrl_busy_time[16];
515 __u8 power_cycles[16];
516 __u8 power_on_hours[16];
517 __u8 unsafe_shutdowns[16];
518 __u8 media_errors[16];
519 __u8 num_err_log_entries[16];
520 __le32 warning_temp_time;
521 __le32 critical_comp_time;
522 __le16 temp_sensor[8];
523 __le32 thm_temp1_trans_count;
524 __le32 thm_temp2_trans_count;
525 __le32 thm_temp1_total_time;
526 __le32 thm_temp2_total_time;
527 __u8 rsvd232[280];
528 };
529
530 struct nvme_fw_slot_info_log {
531 __u8 afi;
532 __u8 rsvd1[7];
533 __le64 frs[7];
534 __u8 rsvd64[448];
535 };
536
537 enum {
538 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
539 NVME_CMD_EFFECTS_LBCC = 1 << 1,
540 NVME_CMD_EFFECTS_NCC = 1 << 2,
541 NVME_CMD_EFFECTS_NIC = 1 << 3,
542 NVME_CMD_EFFECTS_CCC = 1 << 4,
543 NVME_CMD_EFFECTS_CSE_MASK = GENMASK(18, 16),
544 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
545 };
546
547 struct nvme_effects_log {
548 __le32 acs[256];
549 __le32 iocs[256];
550 __u8 resv[2048];
551 };
552
553 enum nvme_ana_state {
554 NVME_ANA_OPTIMIZED = 0x01,
555 NVME_ANA_NONOPTIMIZED = 0x02,
556 NVME_ANA_INACCESSIBLE = 0x03,
557 NVME_ANA_PERSISTENT_LOSS = 0x04,
558 NVME_ANA_CHANGE = 0x0f,
559 };
560
561 struct nvme_ana_group_desc {
562 __le32 grpid;
563 __le32 nnsids;
564 __le64 chgcnt;
565 __u8 state;
566 __u8 rsvd17[15];
567 __le32 nsids[];
568 };
569
570 /* flag for the log specific field of the ANA log */
571 #define NVME_ANA_LOG_RGO (1 << 0)
572
573 struct nvme_ana_rsp_hdr {
574 __le64 chgcnt;
575 __le16 ngrps;
576 __le16 rsvd10[3];
577 };
578
579 struct nvme_zone_descriptor {
580 __u8 zt;
581 __u8 zs;
582 __u8 za;
583 __u8 rsvd3[5];
584 __le64 zcap;
585 __le64 zslba;
586 __le64 wp;
587 __u8 rsvd32[32];
588 };
589
590 enum {
591 NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2,
592 };
593
594 struct nvme_zone_report {
595 __le64 nr_zones;
596 __u8 resv8[56];
597 struct nvme_zone_descriptor entries[];
598 };
599
600 enum {
601 NVME_SMART_CRIT_SPARE = 1 << 0,
602 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
603 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
604 NVME_SMART_CRIT_MEDIA = 1 << 3,
605 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
606 };
607
608 enum {
609 NVME_AER_ERROR = 0,
610 NVME_AER_SMART = 1,
611 NVME_AER_NOTICE = 2,
612 NVME_AER_CSS = 6,
613 NVME_AER_VS = 7,
614 };
615
616 enum {
617 NVME_AER_ERROR_PERSIST_INT_ERR = 0x03,
618 };
619
620 enum {
621 NVME_AER_NOTICE_NS_CHANGED = 0x00,
622 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
623 NVME_AER_NOTICE_ANA = 0x03,
624 NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
625 };
626
627 enum {
628 NVME_AEN_BIT_NS_ATTR = 8,
629 NVME_AEN_BIT_FW_ACT = 9,
630 NVME_AEN_BIT_ANA_CHANGE = 11,
631 NVME_AEN_BIT_DISC_CHANGE = 31,
632 };
633
634 enum {
635 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
636 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
637 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
638 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
639 };
640
641 struct nvme_lba_range_type {
642 __u8 type;
643 __u8 attributes;
644 __u8 rsvd2[14];
645 __le64 slba;
646 __le64 nlb;
647 __u8 guid[16];
648 __u8 rsvd48[16];
649 };
650
651 enum {
652 NVME_LBART_TYPE_FS = 0x01,
653 NVME_LBART_TYPE_RAID = 0x02,
654 NVME_LBART_TYPE_CACHE = 0x03,
655 NVME_LBART_TYPE_SWAP = 0x04,
656
657 NVME_LBART_ATTRIB_TEMP = 1 << 0,
658 NVME_LBART_ATTRIB_HIDE = 1 << 1,
659 };
660
661 struct nvme_reservation_status {
662 __le32 gen;
663 __u8 rtype;
664 __u8 regctl[2];
665 __u8 resv5[2];
666 __u8 ptpls;
667 __u8 resv10[13];
668 struct {
669 __le16 cntlid;
670 __u8 rcsts;
671 __u8 resv3[5];
672 __le64 hostid;
673 __le64 rkey;
674 } regctl_ds[];
675 };
676
677 enum nvme_async_event_type {
678 NVME_AER_TYPE_ERROR = 0,
679 NVME_AER_TYPE_SMART = 1,
680 NVME_AER_TYPE_NOTICE = 2,
681 };
682
683 /* I/O commands */
684
685 enum nvme_opcode {
686 nvme_cmd_flush = 0x00,
687 nvme_cmd_write = 0x01,
688 nvme_cmd_read = 0x02,
689 nvme_cmd_write_uncor = 0x04,
690 nvme_cmd_compare = 0x05,
691 nvme_cmd_write_zeroes = 0x08,
692 nvme_cmd_dsm = 0x09,
693 nvme_cmd_verify = 0x0c,
694 nvme_cmd_resv_register = 0x0d,
695 nvme_cmd_resv_report = 0x0e,
696 nvme_cmd_resv_acquire = 0x11,
697 nvme_cmd_resv_release = 0x15,
698 nvme_cmd_zone_mgmt_send = 0x79,
699 nvme_cmd_zone_mgmt_recv = 0x7a,
700 nvme_cmd_zone_append = 0x7d,
701 };
702
703 #define nvme_opcode_name(opcode) { opcode, #opcode }
704 #define show_nvm_opcode_name(val) \
705 __print_symbolic(val, \
706 nvme_opcode_name(nvme_cmd_flush), \
707 nvme_opcode_name(nvme_cmd_write), \
708 nvme_opcode_name(nvme_cmd_read), \
709 nvme_opcode_name(nvme_cmd_write_uncor), \
710 nvme_opcode_name(nvme_cmd_compare), \
711 nvme_opcode_name(nvme_cmd_write_zeroes), \
712 nvme_opcode_name(nvme_cmd_dsm), \
713 nvme_opcode_name(nvme_cmd_resv_register), \
714 nvme_opcode_name(nvme_cmd_resv_report), \
715 nvme_opcode_name(nvme_cmd_resv_acquire), \
716 nvme_opcode_name(nvme_cmd_resv_release), \
717 nvme_opcode_name(nvme_cmd_zone_mgmt_send), \
718 nvme_opcode_name(nvme_cmd_zone_mgmt_recv), \
719 nvme_opcode_name(nvme_cmd_zone_append))
720
721
722
723 /*
724 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
725 *
726 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
727 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
728 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
729 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
730 * request subtype
731 */
732 enum {
733 NVME_SGL_FMT_ADDRESS = 0x00,
734 NVME_SGL_FMT_OFFSET = 0x01,
735 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
736 NVME_SGL_FMT_INVALIDATE = 0x0f,
737 };
738
739 /*
740 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
741 *
742 * For struct nvme_sgl_desc:
743 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
744 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
745 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
746 *
747 * For struct nvme_keyed_sgl_desc:
748 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
749 *
750 * Transport-specific SGL types:
751 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
752 */
753 enum {
754 NVME_SGL_FMT_DATA_DESC = 0x00,
755 NVME_SGL_FMT_SEG_DESC = 0x02,
756 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
757 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
758 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
759 };
760
761 struct nvme_sgl_desc {
762 __le64 addr;
763 __le32 length;
764 __u8 rsvd[3];
765 __u8 type;
766 };
767
768 struct nvme_keyed_sgl_desc {
769 __le64 addr;
770 __u8 length[3];
771 __u8 key[4];
772 __u8 type;
773 };
774
775 union nvme_data_ptr {
776 struct {
777 __le64 prp1;
778 __le64 prp2;
779 };
780 struct nvme_sgl_desc sgl;
781 struct nvme_keyed_sgl_desc ksgl;
782 };
783
784 /*
785 * Lowest two bits of our flags field (FUSE field in the spec):
786 *
787 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
788 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
789 *
790 * Highest two bits in our flags field (PSDT field in the spec):
791 *
792 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
793 * If used, MPTR contains addr of single physical buffer (byte aligned).
794 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
795 * If used, MPTR contains an address of an SGL segment containing
796 * exactly 1 SGL descriptor (qword aligned).
797 */
798 enum {
799 NVME_CMD_FUSE_FIRST = (1 << 0),
800 NVME_CMD_FUSE_SECOND = (1 << 1),
801
802 NVME_CMD_SGL_METABUF = (1 << 6),
803 NVME_CMD_SGL_METASEG = (1 << 7),
804 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
805 };
806
807 struct nvme_common_command {
808 __u8 opcode;
809 __u8 flags;
810 __u16 command_id;
811 __le32 nsid;
812 __le32 cdw2[2];
813 __le64 metadata;
814 union nvme_data_ptr dptr;
815 __le32 cdw10;
816 __le32 cdw11;
817 __le32 cdw12;
818 __le32 cdw13;
819 __le32 cdw14;
820 __le32 cdw15;
821 };
822
823 struct nvme_rw_command {
824 __u8 opcode;
825 __u8 flags;
826 __u16 command_id;
827 __le32 nsid;
828 __u64 rsvd2;
829 __le64 metadata;
830 union nvme_data_ptr dptr;
831 __le64 slba;
832 __le16 length;
833 __le16 control;
834 __le32 dsmgmt;
835 __le32 reftag;
836 __le16 apptag;
837 __le16 appmask;
838 };
839
840 enum {
841 NVME_RW_LR = 1 << 15,
842 NVME_RW_FUA = 1 << 14,
843 NVME_RW_APPEND_PIREMAP = 1 << 9,
844 NVME_RW_DSM_FREQ_UNSPEC = 0,
845 NVME_RW_DSM_FREQ_TYPICAL = 1,
846 NVME_RW_DSM_FREQ_RARE = 2,
847 NVME_RW_DSM_FREQ_READS = 3,
848 NVME_RW_DSM_FREQ_WRITES = 4,
849 NVME_RW_DSM_FREQ_RW = 5,
850 NVME_RW_DSM_FREQ_ONCE = 6,
851 NVME_RW_DSM_FREQ_PREFETCH = 7,
852 NVME_RW_DSM_FREQ_TEMP = 8,
853 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
854 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
855 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
856 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
857 NVME_RW_DSM_SEQ_REQ = 1 << 6,
858 NVME_RW_DSM_COMPRESSED = 1 << 7,
859 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
860 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
861 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
862 NVME_RW_PRINFO_PRACT = 1 << 13,
863 NVME_RW_DTYPE_STREAMS = 1 << 4,
864 };
865
866 struct nvme_dsm_cmd {
867 __u8 opcode;
868 __u8 flags;
869 __u16 command_id;
870 __le32 nsid;
871 __u64 rsvd2[2];
872 union nvme_data_ptr dptr;
873 __le32 nr;
874 __le32 attributes;
875 __u32 rsvd12[4];
876 };
877
878 enum {
879 NVME_DSMGMT_IDR = 1 << 0,
880 NVME_DSMGMT_IDW = 1 << 1,
881 NVME_DSMGMT_AD = 1 << 2,
882 };
883
884 #define NVME_DSM_MAX_RANGES 256
885
886 struct nvme_dsm_range {
887 __le32 cattr;
888 __le32 nlb;
889 __le64 slba;
890 };
891
892 struct nvme_write_zeroes_cmd {
893 __u8 opcode;
894 __u8 flags;
895 __u16 command_id;
896 __le32 nsid;
897 __u64 rsvd2;
898 __le64 metadata;
899 union nvme_data_ptr dptr;
900 __le64 slba;
901 __le16 length;
902 __le16 control;
903 __le32 dsmgmt;
904 __le32 reftag;
905 __le16 apptag;
906 __le16 appmask;
907 };
908
909 enum nvme_zone_mgmt_action {
910 NVME_ZONE_CLOSE = 0x1,
911 NVME_ZONE_FINISH = 0x2,
912 NVME_ZONE_OPEN = 0x3,
913 NVME_ZONE_RESET = 0x4,
914 NVME_ZONE_OFFLINE = 0x5,
915 NVME_ZONE_SET_DESC_EXT = 0x10,
916 };
917
918 struct nvme_zone_mgmt_send_cmd {
919 __u8 opcode;
920 __u8 flags;
921 __u16 command_id;
922 __le32 nsid;
923 __le32 cdw2[2];
924 __le64 metadata;
925 union nvme_data_ptr dptr;
926 __le64 slba;
927 __le32 cdw12;
928 __u8 zsa;
929 __u8 select_all;
930 __u8 rsvd13[2];
931 __le32 cdw14[2];
932 };
933
934 struct nvme_zone_mgmt_recv_cmd {
935 __u8 opcode;
936 __u8 flags;
937 __u16 command_id;
938 __le32 nsid;
939 __le64 rsvd2[2];
940 union nvme_data_ptr dptr;
941 __le64 slba;
942 __le32 numd;
943 __u8 zra;
944 __u8 zrasf;
945 __u8 pr;
946 __u8 rsvd13;
947 __le32 cdw14[2];
948 };
949
950 enum {
951 NVME_ZRA_ZONE_REPORT = 0,
952 NVME_ZRASF_ZONE_REPORT_ALL = 0,
953 NVME_ZRASF_ZONE_STATE_EMPTY = 0x01,
954 NVME_ZRASF_ZONE_STATE_IMP_OPEN = 0x02,
955 NVME_ZRASF_ZONE_STATE_EXP_OPEN = 0x03,
956 NVME_ZRASF_ZONE_STATE_CLOSED = 0x04,
957 NVME_ZRASF_ZONE_STATE_READONLY = 0x05,
958 NVME_ZRASF_ZONE_STATE_FULL = 0x06,
959 NVME_ZRASF_ZONE_STATE_OFFLINE = 0x07,
960 NVME_REPORT_ZONE_PARTIAL = 1,
961 };
962
963 /* Features */
964
965 enum {
966 NVME_TEMP_THRESH_MASK = 0xffff,
967 NVME_TEMP_THRESH_SELECT_SHIFT = 16,
968 NVME_TEMP_THRESH_TYPE_UNDER = 0x100000,
969 };
970
971 struct nvme_feat_auto_pst {
972 __le64 entries[32];
973 };
974
975 enum {
976 NVME_HOST_MEM_ENABLE = (1 << 0),
977 NVME_HOST_MEM_RETURN = (1 << 1),
978 };
979
980 struct nvme_feat_host_behavior {
981 __u8 acre;
982 __u8 resv1[511];
983 };
984
985 enum {
986 NVME_ENABLE_ACRE = 1,
987 };
988
989 /* Admin commands */
990
991 enum nvme_admin_opcode {
992 nvme_admin_delete_sq = 0x00,
993 nvme_admin_create_sq = 0x01,
994 nvme_admin_get_log_page = 0x02,
995 nvme_admin_delete_cq = 0x04,
996 nvme_admin_create_cq = 0x05,
997 nvme_admin_identify = 0x06,
998 nvme_admin_abort_cmd = 0x08,
999 nvme_admin_set_features = 0x09,
1000 nvme_admin_get_features = 0x0a,
1001 nvme_admin_async_event = 0x0c,
1002 nvme_admin_ns_mgmt = 0x0d,
1003 nvme_admin_activate_fw = 0x10,
1004 nvme_admin_download_fw = 0x11,
1005 nvme_admin_dev_self_test = 0x14,
1006 nvme_admin_ns_attach = 0x15,
1007 nvme_admin_keep_alive = 0x18,
1008 nvme_admin_directive_send = 0x19,
1009 nvme_admin_directive_recv = 0x1a,
1010 nvme_admin_virtual_mgmt = 0x1c,
1011 nvme_admin_nvme_mi_send = 0x1d,
1012 nvme_admin_nvme_mi_recv = 0x1e,
1013 nvme_admin_dbbuf = 0x7C,
1014 nvme_admin_format_nvm = 0x80,
1015 nvme_admin_security_send = 0x81,
1016 nvme_admin_security_recv = 0x82,
1017 nvme_admin_sanitize_nvm = 0x84,
1018 nvme_admin_get_lba_status = 0x86,
1019 nvme_admin_vendor_start = 0xC0,
1020 };
1021
1022 #define nvme_admin_opcode_name(opcode) { opcode, #opcode }
1023 #define show_admin_opcode_name(val) \
1024 __print_symbolic(val, \
1025 nvme_admin_opcode_name(nvme_admin_delete_sq), \
1026 nvme_admin_opcode_name(nvme_admin_create_sq), \
1027 nvme_admin_opcode_name(nvme_admin_get_log_page), \
1028 nvme_admin_opcode_name(nvme_admin_delete_cq), \
1029 nvme_admin_opcode_name(nvme_admin_create_cq), \
1030 nvme_admin_opcode_name(nvme_admin_identify), \
1031 nvme_admin_opcode_name(nvme_admin_abort_cmd), \
1032 nvme_admin_opcode_name(nvme_admin_set_features), \
1033 nvme_admin_opcode_name(nvme_admin_get_features), \
1034 nvme_admin_opcode_name(nvme_admin_async_event), \
1035 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
1036 nvme_admin_opcode_name(nvme_admin_activate_fw), \
1037 nvme_admin_opcode_name(nvme_admin_download_fw), \
1038 nvme_admin_opcode_name(nvme_admin_ns_attach), \
1039 nvme_admin_opcode_name(nvme_admin_keep_alive), \
1040 nvme_admin_opcode_name(nvme_admin_directive_send), \
1041 nvme_admin_opcode_name(nvme_admin_directive_recv), \
1042 nvme_admin_opcode_name(nvme_admin_dbbuf), \
1043 nvme_admin_opcode_name(nvme_admin_format_nvm), \
1044 nvme_admin_opcode_name(nvme_admin_security_send), \
1045 nvme_admin_opcode_name(nvme_admin_security_recv), \
1046 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
1047 nvme_admin_opcode_name(nvme_admin_get_lba_status))
1048
1049 enum {
1050 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
1051 NVME_CQ_IRQ_ENABLED = (1 << 1),
1052 NVME_SQ_PRIO_URGENT = (0 << 1),
1053 NVME_SQ_PRIO_HIGH = (1 << 1),
1054 NVME_SQ_PRIO_MEDIUM = (2 << 1),
1055 NVME_SQ_PRIO_LOW = (3 << 1),
1056 NVME_FEAT_ARBITRATION = 0x01,
1057 NVME_FEAT_POWER_MGMT = 0x02,
1058 NVME_FEAT_LBA_RANGE = 0x03,
1059 NVME_FEAT_TEMP_THRESH = 0x04,
1060 NVME_FEAT_ERR_RECOVERY = 0x05,
1061 NVME_FEAT_VOLATILE_WC = 0x06,
1062 NVME_FEAT_NUM_QUEUES = 0x07,
1063 NVME_FEAT_IRQ_COALESCE = 0x08,
1064 NVME_FEAT_IRQ_CONFIG = 0x09,
1065 NVME_FEAT_WRITE_ATOMIC = 0x0a,
1066 NVME_FEAT_ASYNC_EVENT = 0x0b,
1067 NVME_FEAT_AUTO_PST = 0x0c,
1068 NVME_FEAT_HOST_MEM_BUF = 0x0d,
1069 NVME_FEAT_TIMESTAMP = 0x0e,
1070 NVME_FEAT_KATO = 0x0f,
1071 NVME_FEAT_HCTM = 0x10,
1072 NVME_FEAT_NOPSC = 0x11,
1073 NVME_FEAT_RRL = 0x12,
1074 NVME_FEAT_PLM_CONFIG = 0x13,
1075 NVME_FEAT_PLM_WINDOW = 0x14,
1076 NVME_FEAT_HOST_BEHAVIOR = 0x16,
1077 NVME_FEAT_SANITIZE = 0x17,
1078 NVME_FEAT_SW_PROGRESS = 0x80,
1079 NVME_FEAT_HOST_ID = 0x81,
1080 NVME_FEAT_RESV_MASK = 0x82,
1081 NVME_FEAT_RESV_PERSIST = 0x83,
1082 NVME_FEAT_WRITE_PROTECT = 0x84,
1083 NVME_FEAT_VENDOR_START = 0xC0,
1084 NVME_FEAT_VENDOR_END = 0xFF,
1085 NVME_LOG_ERROR = 0x01,
1086 NVME_LOG_SMART = 0x02,
1087 NVME_LOG_FW_SLOT = 0x03,
1088 NVME_LOG_CHANGED_NS = 0x04,
1089 NVME_LOG_CMD_EFFECTS = 0x05,
1090 NVME_LOG_DEVICE_SELF_TEST = 0x06,
1091 NVME_LOG_TELEMETRY_HOST = 0x07,
1092 NVME_LOG_TELEMETRY_CTRL = 0x08,
1093 NVME_LOG_ENDURANCE_GROUP = 0x09,
1094 NVME_LOG_ANA = 0x0c,
1095 NVME_LOG_DISC = 0x70,
1096 NVME_LOG_RESERVATION = 0x80,
1097 NVME_FWACT_REPL = (0 << 3),
1098 NVME_FWACT_REPL_ACTV = (1 << 3),
1099 NVME_FWACT_ACTV = (2 << 3),
1100 };
1101
1102 /* NVMe Namespace Write Protect State */
1103 enum {
1104 NVME_NS_NO_WRITE_PROTECT = 0,
1105 NVME_NS_WRITE_PROTECT,
1106 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1107 NVME_NS_WRITE_PROTECT_PERMANENT,
1108 };
1109
1110 #define NVME_MAX_CHANGED_NAMESPACES 1024
1111
1112 struct nvme_identify {
1113 __u8 opcode;
1114 __u8 flags;
1115 __u16 command_id;
1116 __le32 nsid;
1117 __u64 rsvd2[2];
1118 union nvme_data_ptr dptr;
1119 __u8 cns;
1120 __u8 rsvd3;
1121 __le16 ctrlid;
1122 __u8 rsvd11[3];
1123 __u8 csi;
1124 __u32 rsvd12[4];
1125 };
1126
1127 #define NVME_IDENTIFY_DATA_SIZE 4096
1128
1129 struct nvme_features {
1130 __u8 opcode;
1131 __u8 flags;
1132 __u16 command_id;
1133 __le32 nsid;
1134 __u64 rsvd2[2];
1135 union nvme_data_ptr dptr;
1136 __le32 fid;
1137 __le32 dword11;
1138 __le32 dword12;
1139 __le32 dword13;
1140 __le32 dword14;
1141 __le32 dword15;
1142 };
1143
1144 struct nvme_host_mem_buf_desc {
1145 __le64 addr;
1146 __le32 size;
1147 __u32 rsvd;
1148 };
1149
1150 struct nvme_create_cq {
1151 __u8 opcode;
1152 __u8 flags;
1153 __u16 command_id;
1154 __u32 rsvd1[5];
1155 __le64 prp1;
1156 __u64 rsvd8;
1157 __le16 cqid;
1158 __le16 qsize;
1159 __le16 cq_flags;
1160 __le16 irq_vector;
1161 __u32 rsvd12[4];
1162 };
1163
1164 struct nvme_create_sq {
1165 __u8 opcode;
1166 __u8 flags;
1167 __u16 command_id;
1168 __u32 rsvd1[5];
1169 __le64 prp1;
1170 __u64 rsvd8;
1171 __le16 sqid;
1172 __le16 qsize;
1173 __le16 sq_flags;
1174 __le16 cqid;
1175 __u32 rsvd12[4];
1176 };
1177
1178 struct nvme_delete_queue {
1179 __u8 opcode;
1180 __u8 flags;
1181 __u16 command_id;
1182 __u32 rsvd1[9];
1183 __le16 qid;
1184 __u16 rsvd10;
1185 __u32 rsvd11[5];
1186 };
1187
1188 struct nvme_abort_cmd {
1189 __u8 opcode;
1190 __u8 flags;
1191 __u16 command_id;
1192 __u32 rsvd1[9];
1193 __le16 sqid;
1194 __u16 cid;
1195 __u32 rsvd11[5];
1196 };
1197
1198 struct nvme_download_firmware {
1199 __u8 opcode;
1200 __u8 flags;
1201 __u16 command_id;
1202 __u32 rsvd1[5];
1203 union nvme_data_ptr dptr;
1204 __le32 numd;
1205 __le32 offset;
1206 __u32 rsvd12[4];
1207 };
1208
1209 struct nvme_format_cmd {
1210 __u8 opcode;
1211 __u8 flags;
1212 __u16 command_id;
1213 __le32 nsid;
1214 __u64 rsvd2[4];
1215 __le32 cdw10;
1216 __u32 rsvd11[5];
1217 };
1218
1219 struct nvme_get_log_page_command {
1220 __u8 opcode;
1221 __u8 flags;
1222 __u16 command_id;
1223 __le32 nsid;
1224 __u64 rsvd2[2];
1225 union nvme_data_ptr dptr;
1226 __u8 lid;
1227 __u8 lsp; /* upper 4 bits reserved */
1228 __le16 numdl;
1229 __le16 numdu;
1230 __u16 rsvd11;
1231 union {
1232 struct {
1233 __le32 lpol;
1234 __le32 lpou;
1235 };
1236 __le64 lpo;
1237 };
1238 __u8 rsvd14[3];
1239 __u8 csi;
1240 __u32 rsvd15;
1241 };
1242
1243 struct nvme_directive_cmd {
1244 __u8 opcode;
1245 __u8 flags;
1246 __u16 command_id;
1247 __le32 nsid;
1248 __u64 rsvd2[2];
1249 union nvme_data_ptr dptr;
1250 __le32 numd;
1251 __u8 doper;
1252 __u8 dtype;
1253 __le16 dspec;
1254 __u8 endir;
1255 __u8 tdtype;
1256 __u16 rsvd15;
1257
1258 __u32 rsvd16[3];
1259 };
1260
1261 /*
1262 * Fabrics subcommands.
1263 */
1264 enum nvmf_fabrics_opcode {
1265 nvme_fabrics_command = 0x7f,
1266 };
1267
1268 enum nvmf_capsule_command {
1269 nvme_fabrics_type_property_set = 0x00,
1270 nvme_fabrics_type_connect = 0x01,
1271 nvme_fabrics_type_property_get = 0x04,
1272 };
1273
1274 #define nvme_fabrics_type_name(type) { type, #type }
1275 #define show_fabrics_type_name(type) \
1276 __print_symbolic(type, \
1277 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1278 nvme_fabrics_type_name(nvme_fabrics_type_connect), \
1279 nvme_fabrics_type_name(nvme_fabrics_type_property_get))
1280
1281 /*
1282 * If not fabrics command, fctype will be ignored.
1283 */
1284 #define show_opcode_name(qid, opcode, fctype) \
1285 ((opcode) == nvme_fabrics_command ? \
1286 show_fabrics_type_name(fctype) : \
1287 ((qid) ? \
1288 show_nvm_opcode_name(opcode) : \
1289 show_admin_opcode_name(opcode)))
1290
1291 struct nvmf_common_command {
1292 __u8 opcode;
1293 __u8 resv1;
1294 __u16 command_id;
1295 __u8 fctype;
1296 __u8 resv2[35];
1297 __u8 ts[24];
1298 };
1299
1300 /*
1301 * The legal cntlid range a NVMe Target will provide.
1302 * Note that cntlid of value 0 is considered illegal in the fabrics world.
1303 * Devices based on earlier specs did not have the subsystem concept;
1304 * therefore, those devices had their cntlid value set to 0 as a result.
1305 */
1306 #define NVME_CNTLID_MIN 1
1307 #define NVME_CNTLID_MAX 0xffef
1308 #define NVME_CNTLID_DYNAMIC 0xffff
1309
1310 #define MAX_DISC_LOGS 255
1311
1312 /* Discovery log page entry */
1313 struct nvmf_disc_rsp_page_entry {
1314 __u8 trtype;
1315 __u8 adrfam;
1316 __u8 subtype;
1317 __u8 treq;
1318 __le16 portid;
1319 __le16 cntlid;
1320 __le16 asqsz;
1321 __u8 resv8[22];
1322 char trsvcid[NVMF_TRSVCID_SIZE];
1323 __u8 resv64[192];
1324 char subnqn[NVMF_NQN_FIELD_LEN];
1325 char traddr[NVMF_TRADDR_SIZE];
1326 union tsas {
1327 char common[NVMF_TSAS_SIZE];
1328 struct rdma {
1329 __u8 qptype;
1330 __u8 prtype;
1331 __u8 cms;
1332 __u8 resv3[5];
1333 __u16 pkey;
1334 __u8 resv10[246];
1335 } rdma;
1336 } tsas;
1337 };
1338
1339 /* Discovery log page header */
1340 struct nvmf_disc_rsp_page_hdr {
1341 __le64 genctr;
1342 __le64 numrec;
1343 __le16 recfmt;
1344 __u8 resv14[1006];
1345 struct nvmf_disc_rsp_page_entry entries[];
1346 };
1347
1348 enum {
1349 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1350 };
1351
1352 struct nvmf_connect_command {
1353 __u8 opcode;
1354 __u8 resv1;
1355 __u16 command_id;
1356 __u8 fctype;
1357 __u8 resv2[19];
1358 union nvme_data_ptr dptr;
1359 __le16 recfmt;
1360 __le16 qid;
1361 __le16 sqsize;
1362 __u8 cattr;
1363 __u8 resv3;
1364 __le32 kato;
1365 __u8 resv4[12];
1366 };
1367
1368 struct nvmf_connect_data {
1369 uuid_t hostid;
1370 __le16 cntlid;
1371 char resv4[238];
1372 char subsysnqn[NVMF_NQN_FIELD_LEN];
1373 char hostnqn[NVMF_NQN_FIELD_LEN];
1374 char resv5[256];
1375 };
1376
1377 struct nvmf_property_set_command {
1378 __u8 opcode;
1379 __u8 resv1;
1380 __u16 command_id;
1381 __u8 fctype;
1382 __u8 resv2[35];
1383 __u8 attrib;
1384 __u8 resv3[3];
1385 __le32 offset;
1386 __le64 value;
1387 __u8 resv4[8];
1388 };
1389
1390 struct nvmf_property_get_command {
1391 __u8 opcode;
1392 __u8 resv1;
1393 __u16 command_id;
1394 __u8 fctype;
1395 __u8 resv2[35];
1396 __u8 attrib;
1397 __u8 resv3[3];
1398 __le32 offset;
1399 __u8 resv4[16];
1400 };
1401
1402 struct nvme_dbbuf {
1403 __u8 opcode;
1404 __u8 flags;
1405 __u16 command_id;
1406 __u32 rsvd1[5];
1407 __le64 prp1;
1408 __le64 prp2;
1409 __u32 rsvd12[6];
1410 };
1411
1412 struct streams_directive_params {
1413 __le16 msl;
1414 __le16 nssa;
1415 __le16 nsso;
1416 __u8 rsvd[10];
1417 __le32 sws;
1418 __le16 sgs;
1419 __le16 nsa;
1420 __le16 nso;
1421 __u8 rsvd2[6];
1422 };
1423
1424 struct nvme_command {
1425 union {
1426 struct nvme_common_command common;
1427 struct nvme_rw_command rw;
1428 struct nvme_identify identify;
1429 struct nvme_features features;
1430 struct nvme_create_cq create_cq;
1431 struct nvme_create_sq create_sq;
1432 struct nvme_delete_queue delete_queue;
1433 struct nvme_download_firmware dlfw;
1434 struct nvme_format_cmd format;
1435 struct nvme_dsm_cmd dsm;
1436 struct nvme_write_zeroes_cmd write_zeroes;
1437 struct nvme_zone_mgmt_send_cmd zms;
1438 struct nvme_zone_mgmt_recv_cmd zmr;
1439 struct nvme_abort_cmd abort;
1440 struct nvme_get_log_page_command get_log_page;
1441 struct nvmf_common_command fabrics;
1442 struct nvmf_connect_command connect;
1443 struct nvmf_property_set_command prop_set;
1444 struct nvmf_property_get_command prop_get;
1445 struct nvme_dbbuf dbbuf;
1446 struct nvme_directive_cmd directive;
1447 };
1448 };
1449
nvme_is_fabrics(struct nvme_command * cmd)1450 static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1451 {
1452 return cmd->common.opcode == nvme_fabrics_command;
1453 }
1454
1455 struct nvme_error_slot {
1456 __le64 error_count;
1457 __le16 sqid;
1458 __le16 cmdid;
1459 __le16 status_field;
1460 __le16 param_error_location;
1461 __le64 lba;
1462 __le32 nsid;
1463 __u8 vs;
1464 __u8 resv[3];
1465 __le64 cs;
1466 __u8 resv2[24];
1467 };
1468
nvme_is_write(struct nvme_command * cmd)1469 static inline bool nvme_is_write(struct nvme_command *cmd)
1470 {
1471 /*
1472 * What a mess...
1473 *
1474 * Why can't we simply have a Fabrics In and Fabrics out command?
1475 */
1476 if (unlikely(nvme_is_fabrics(cmd)))
1477 return cmd->fabrics.fctype & 1;
1478 return cmd->common.opcode & 1;
1479 }
1480
1481 enum {
1482 /*
1483 * Generic Command Status:
1484 */
1485 NVME_SC_SUCCESS = 0x0,
1486 NVME_SC_INVALID_OPCODE = 0x1,
1487 NVME_SC_INVALID_FIELD = 0x2,
1488 NVME_SC_CMDID_CONFLICT = 0x3,
1489 NVME_SC_DATA_XFER_ERROR = 0x4,
1490 NVME_SC_POWER_LOSS = 0x5,
1491 NVME_SC_INTERNAL = 0x6,
1492 NVME_SC_ABORT_REQ = 0x7,
1493 NVME_SC_ABORT_QUEUE = 0x8,
1494 NVME_SC_FUSED_FAIL = 0x9,
1495 NVME_SC_FUSED_MISSING = 0xa,
1496 NVME_SC_INVALID_NS = 0xb,
1497 NVME_SC_CMD_SEQ_ERROR = 0xc,
1498 NVME_SC_SGL_INVALID_LAST = 0xd,
1499 NVME_SC_SGL_INVALID_COUNT = 0xe,
1500 NVME_SC_SGL_INVALID_DATA = 0xf,
1501 NVME_SC_SGL_INVALID_METADATA = 0x10,
1502 NVME_SC_SGL_INVALID_TYPE = 0x11,
1503 NVME_SC_CMB_INVALID_USE = 0x12,
1504 NVME_SC_PRP_INVALID_OFFSET = 0x13,
1505 NVME_SC_ATOMIC_WU_EXCEEDED = 0x14,
1506 NVME_SC_OP_DENIED = 0x15,
1507 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1508 NVME_SC_RESERVED = 0x17,
1509 NVME_SC_HOST_ID_INCONSIST = 0x18,
1510 NVME_SC_KA_TIMEOUT_EXPIRED = 0x19,
1511 NVME_SC_KA_TIMEOUT_INVALID = 0x1A,
1512 NVME_SC_ABORTED_PREEMPT_ABORT = 0x1B,
1513 NVME_SC_SANITIZE_FAILED = 0x1C,
1514 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
1515 NVME_SC_SGL_INVALID_GRANULARITY = 0x1E,
1516 NVME_SC_CMD_NOT_SUP_CMB_QUEUE = 0x1F,
1517 NVME_SC_NS_WRITE_PROTECTED = 0x20,
1518 NVME_SC_CMD_INTERRUPTED = 0x21,
1519 NVME_SC_TRANSIENT_TR_ERR = 0x22,
1520 NVME_SC_INVALID_IO_CMD_SET = 0x2C,
1521
1522 NVME_SC_LBA_RANGE = 0x80,
1523 NVME_SC_CAP_EXCEEDED = 0x81,
1524 NVME_SC_NS_NOT_READY = 0x82,
1525 NVME_SC_RESERVATION_CONFLICT = 0x83,
1526 NVME_SC_FORMAT_IN_PROGRESS = 0x84,
1527
1528 /*
1529 * Command Specific Status:
1530 */
1531 NVME_SC_CQ_INVALID = 0x100,
1532 NVME_SC_QID_INVALID = 0x101,
1533 NVME_SC_QUEUE_SIZE = 0x102,
1534 NVME_SC_ABORT_LIMIT = 0x103,
1535 NVME_SC_ABORT_MISSING = 0x104,
1536 NVME_SC_ASYNC_LIMIT = 0x105,
1537 NVME_SC_FIRMWARE_SLOT = 0x106,
1538 NVME_SC_FIRMWARE_IMAGE = 0x107,
1539 NVME_SC_INVALID_VECTOR = 0x108,
1540 NVME_SC_INVALID_LOG_PAGE = 0x109,
1541 NVME_SC_INVALID_FORMAT = 0x10a,
1542 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
1543 NVME_SC_INVALID_QUEUE = 0x10c,
1544 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1545 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1546 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
1547 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1548 NVME_SC_FW_NEEDS_RESET = 0x111,
1549 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1550 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
1551 NVME_SC_OVERLAPPING_RANGE = 0x114,
1552 NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
1553 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1554 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1555 NVME_SC_NS_IS_PRIVATE = 0x119,
1556 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1557 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1558 NVME_SC_CTRL_LIST_INVALID = 0x11c,
1559 NVME_SC_SELT_TEST_IN_PROGRESS = 0x11d,
1560 NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
1561 NVME_SC_CTRL_ID_INVALID = 0x11f,
1562 NVME_SC_SEC_CTRL_STATE_INVALID = 0x120,
1563 NVME_SC_CTRL_RES_NUM_INVALID = 0x121,
1564 NVME_SC_RES_ID_INVALID = 0x122,
1565 NVME_SC_PMR_SAN_PROHIBITED = 0x123,
1566 NVME_SC_ANA_GROUP_ID_INVALID = 0x124,
1567 NVME_SC_ANA_ATTACH_FAILED = 0x125,
1568
1569 /*
1570 * I/O Command Set Specific - NVM commands:
1571 */
1572 NVME_SC_BAD_ATTRIBUTES = 0x180,
1573 NVME_SC_INVALID_PI = 0x181,
1574 NVME_SC_READ_ONLY = 0x182,
1575 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
1576
1577 /*
1578 * I/O Command Set Specific - Fabrics commands:
1579 */
1580 NVME_SC_CONNECT_FORMAT = 0x180,
1581 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1582 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1583 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1584 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1585
1586 NVME_SC_DISCOVERY_RESTART = 0x190,
1587 NVME_SC_AUTH_REQUIRED = 0x191,
1588
1589 /*
1590 * I/O Command Set Specific - Zoned commands:
1591 */
1592 NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8,
1593 NVME_SC_ZONE_FULL = 0x1b9,
1594 NVME_SC_ZONE_READ_ONLY = 0x1ba,
1595 NVME_SC_ZONE_OFFLINE = 0x1bb,
1596 NVME_SC_ZONE_INVALID_WRITE = 0x1bc,
1597 NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd,
1598 NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be,
1599 NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
1600
1601 /*
1602 * Media and Data Integrity Errors:
1603 */
1604 NVME_SC_WRITE_FAULT = 0x280,
1605 NVME_SC_READ_ERROR = 0x281,
1606 NVME_SC_GUARD_CHECK = 0x282,
1607 NVME_SC_APPTAG_CHECK = 0x283,
1608 NVME_SC_REFTAG_CHECK = 0x284,
1609 NVME_SC_COMPARE_FAILED = 0x285,
1610 NVME_SC_ACCESS_DENIED = 0x286,
1611 NVME_SC_UNWRITTEN_BLOCK = 0x287,
1612
1613 /*
1614 * Path-related Errors:
1615 */
1616 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
1617 NVME_SC_ANA_INACCESSIBLE = 0x302,
1618 NVME_SC_ANA_TRANSITION = 0x303,
1619 NVME_SC_HOST_PATH_ERROR = 0x370,
1620 NVME_SC_HOST_ABORTED_CMD = 0x371,
1621
1622 NVME_SC_CRD = 0x1800,
1623 NVME_SC_DNR = 0x4000,
1624 };
1625
1626 struct nvme_completion {
1627 /*
1628 * Used by Admin and Fabrics commands to return data:
1629 */
1630 union nvme_result {
1631 __le16 u16;
1632 __le32 u32;
1633 __le64 u64;
1634 } result;
1635 __le16 sq_head; /* how much of this queue may be reclaimed */
1636 __le16 sq_id; /* submission queue that generated this entry */
1637 __u16 command_id; /* of the command which completed */
1638 __le16 status; /* did the command fail, and if so, why? */
1639 };
1640
1641 #define NVME_VS(major, minor, tertiary) \
1642 (((major) << 16) | ((minor) << 8) | (tertiary))
1643
1644 #define NVME_MAJOR(ver) ((ver) >> 16)
1645 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1646 #define NVME_TERTIARY(ver) ((ver) & 0xff)
1647
1648 #endif /* _LINUX_NVME_H */
1649