| /sound/soc/mediatek/mt8183/ |
| D | mt8183-afe-clk.c | 97 afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk), in mt8183_init_clock()
99 if (!afe_priv->clk) in mt8183_init_clock()
103 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]); in mt8183_init_clock()
104 if (IS_ERR(afe_priv->clk[i])) { in mt8183_init_clock()
107 PTR_ERR(afe_priv->clk[i])); in mt8183_init_clock()
108 return PTR_ERR(afe_priv->clk[i]); in mt8183_init_clock()
120 ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]); in mt8183_afe_enable_clock()
127 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]); in mt8183_afe_enable_clock()
134 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO], in mt8183_afe_enable_clock()
135 afe_priv->clk[CLK_CLK26M]); in mt8183_afe_enable_clock()
[all …]
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| /sound/soc/mediatek/mt8195/ |
| D | mt8195-afe-clk.c | 104 return clk_get_rate(afe_priv->clk[clk_id]); in mt8195_afe_get_mclk_source_rate()
120 afe_priv->clk = in mt8195_afe_init_clock()
121 devm_kcalloc(afe->dev, MT8195_CLK_NUM, sizeof(*afe_priv->clk), in mt8195_afe_init_clock()
123 if (!afe_priv->clk) in mt8195_afe_init_clock()
127 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]); in mt8195_afe_init_clock()
128 if (IS_ERR(afe_priv->clk[i])) { in mt8195_afe_init_clock()
131 PTR_ERR(afe_priv->clk[i])); in mt8195_afe_init_clock()
132 return PTR_ERR(afe_priv->clk[i]); in mt8195_afe_init_clock()
139 int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk) in mt8195_afe_enable_clk() argument
143 if (clk) { in mt8195_afe_enable_clk()
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| D | mt8195-afe-clk.h | 93 int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk);
94 void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);
95 int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk);
96 void mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk);
97 int mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk);
98 void mt8195_afe_disable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk);
99 int mt8195_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
101 int mt8195_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
102 struct clk *parent);
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| D | mt8195-audsys-clk.c | 155 struct clk *clk; in mt8195_audsys_clk_unregister() local
167 clk = cl->clk; in mt8195_audsys_clk_unregister()
168 clk_unregister_gate(clk); in mt8195_audsys_clk_unregister()
177 struct clk *clk; in mt8195_audsys_clk_register() local
191 clk = clk_register_gate(afe->dev, gate->name, gate->parent_name, in mt8195_audsys_clk_register()
195 if (IS_ERR(clk)) { in mt8195_audsys_clk_register()
197 gate->name, PTR_ERR(clk)); in mt8195_audsys_clk_register()
206 cl->clk = clk; in mt8195_audsys_clk_register()
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| /sound/soc/qcom/qdsp6/ |
| D | q6afe-clocks.c | 52 struct q6afe_clk *clk = to_q6afe_clk(hw); in clk_q6afe_prepare() local
54 return q6afe_set_lpass_clock(clk->dev, clk->afe_clk_id, clk->attributes, in clk_q6afe_prepare()
55 Q6AFE_LPASS_CLK_ROOT_DEFAULT, clk->rate); in clk_q6afe_prepare()
60 struct q6afe_clk *clk = to_q6afe_clk(hw); in clk_q6afe_unprepare() local
62 q6afe_set_lpass_clock(clk->dev, clk->afe_clk_id, clk->attributes, in clk_q6afe_unprepare()
69 struct q6afe_clk *clk = to_q6afe_clk(hw); in clk_q6afe_set_rate() local
71 clk->rate = rate; in clk_q6afe_set_rate()
79 struct q6afe_clk *clk = to_q6afe_clk(hw); in clk_q6afe_recalc_rate() local
81 return clk->rate; in clk_q6afe_recalc_rate()
100 struct q6afe_clk *clk = to_q6afe_clk(hw); in clk_vote_q6afe_block() local
[all …]
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| /sound/soc/mediatek/mt6797/ |
| D | mt6797-afe-clk.c | 39 afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk), in mt6797_init_clock()
41 if (!afe_priv->clk) in mt6797_init_clock()
45 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]); in mt6797_init_clock()
46 if (IS_ERR(afe_priv->clk[i])) { in mt6797_init_clock()
49 PTR_ERR(afe_priv->clk[i])); in mt6797_init_clock()
50 return PTR_ERR(afe_priv->clk[i]); in mt6797_init_clock()
62 ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUD]); in mt6797_afe_enable_clock()
69 ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUD_26M]); in mt6797_afe_enable_clock()
76 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD]); in mt6797_afe_enable_clock()
83 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD], in mt6797_afe_enable_clock()
[all …]
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| /sound/soc/mediatek/mt8192/ |
| D | mt8192-afe-clk.c | 69 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS], in mt8192_set_audio_int_bus_parent()
70 afe_priv->clk[clk_id]); in mt8192_set_audio_int_bus_parent()
86 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]); in apll1_mux_setting()
92 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
93 afe_priv->clk[CLK_TOP_APLL1_CK]); in apll1_mux_setting()
102 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]); in apll1_mux_setting()
108 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
109 afe_priv->clk[CLK_TOP_APLL1_D4]); in apll1_mux_setting()
117 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
118 afe_priv->clk[CLK_CLK26M]); in apll1_mux_setting()
[all …]
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| /sound/soc/sh/rcar/ |
| D | adg.c | 29 struct clk *clk[CLKMAX]; member
30 struct clk *clkout[CLKOUTMAX];
31 struct clk *null_clk;
50 ((pos) = adg->clk[i]); \
367 struct clk *clk; in rsnd_adg_clk_control() local
370 for_each_rsnd_clk(clk, adg, i) { in rsnd_adg_clk_control()
372 clk_prepare_enable(clk); in rsnd_adg_clk_control()
379 adg->clk_rate[i] = clk_get_rate(clk); in rsnd_adg_clk_control()
381 clk_disable_unprepare(clk); in rsnd_adg_clk_control()
386 static struct clk *rsnd_adg_create_null_clk(struct rsnd_priv *priv, in rsnd_adg_create_null_clk()
[all …]
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| /sound/soc/rockchip/ |
| D | rockchip_pdm.c | 31 struct clk *clk; member
32 struct clk *hclk;
41 unsigned int clk; member
79 unsigned int i, count, clk, div, rate; in get_pdm_clk() local
81 clk = 0; in get_pdm_clk()
83 return clk; in get_pdm_clk()
92 rate = clk_round_rate(pdm->clk, clkref[i].clk); in get_pdm_clk()
93 if (rate != clkref[i].clk) in get_pdm_clk()
95 clk = clkref[i].clk; in get_pdm_clk()
96 *clk_src = clkref[i].clk; in get_pdm_clk()
[all …]
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| /sound/soc/mxs/ |
| D | mxs-saif.c | 116 ret = clk_prepare_enable(master_saif->clk); in mxs_saif_set_clk()
128 ret = clk_set_rate(master_saif->clk, 512 * rate); in mxs_saif_set_clk()
135 ret = clk_set_rate(master_saif->clk, 384 * rate); in mxs_saif_set_clk()
139 clk_disable_unprepare(master_saif->clk); in mxs_saif_set_clk()
143 ret = clk_set_rate(master_saif->clk, 512 * rate); in mxs_saif_set_clk()
147 clk_disable_unprepare(master_saif->clk); in mxs_saif_set_clk()
219 clk_disable_unprepare(saif->clk); in mxs_saif_put_mclk()
274 ret = clk_prepare_enable(saif->clk); in mxs_saif_get_mclk()
395 ret = clk_prepare(saif->clk); in mxs_saif_startup()
407 clk_unprepare(saif->clk); in mxs_saif_shutdown()
[all …]
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| /sound/soc/mediatek/mt2701/ |
| D | mt2701-afe-common.h | 77 struct clk *hop_ck[MTK_STREAM_NUM];
78 struct clk *sel_ck;
79 struct clk *div_ck;
80 struct clk *mclk_ck;
81 struct clk *asrco_ck;
91 struct clk *base_ck[MT2701_BASE_CLK_NUM];
92 struct clk *mrgif_ck;
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| /sound/soc/fsl/ |
| D | fsl_audmix.c | 47 u8 clk; member
53 { .tdms = 0, .clk = 0, .msg = "" },
55 { .tdms = 1, .clk = 1, .msg = "DIS->TDM1: TDM1 not started!\n" },
57 { .tdms = 2, .clk = 2, .msg = "DIS->TDM2: TDM2 not started!\n" },
59 { .tdms = 3, .clk = 0, .msg = "DIS->MIX: Please start both TDMs!\n" }
61 { .tdms = 1, .clk = 0, .msg = "TDM1->DIS: TDM1 not started!\n" },
63 { .tdms = 0, .clk = 0, .msg = "" },
65 { .tdms = 3, .clk = 2, .msg = "TDM1->TDM2: Please start both TDMs!\n" },
67 { .tdms = 3, .clk = 0, .msg = "TDM1->MIX: Please start both TDMs!\n" }
69 { .tdms = 2, .clk = 0, .msg = "TDM2->DIS: TDM2 not started!\n" },
[all …]
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| D | fsl_rpmsg.h | 24 struct clk *ipg;
25 struct clk *mclk;
26 struct clk *dma;
27 struct clk *pll8k;
28 struct clk *pll11k;
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| /sound/soc/samsung/ |
| D | s3c-i2s-v2.h | 53 struct clk *iis_pclk;
54 struct clk *iis_cclk;
68 extern struct clk *s3c_i2sv2_get_clock(struct snd_soc_dai *cpu_dai);
77 unsigned int rate, struct clk *clk);
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| D | s3c24xx_uda134x.c | 21 struct clk *xtal;
22 struct clk *pclk;
124 unsigned int clk = 0; in s3c24xx_uda134x_hw_params() local
157 clk = (fs_mode == S3C2410_IISMOD_384FS ? 384 : 256) * rate; in s3c24xx_uda134x_hw_params()
162 div, clk, err); in s3c24xx_uda134x_hw_params()
170 ret = snd_soc_dai_set_sysclk(cpu_dai, clk_source , clk, in s3c24xx_uda134x_hw_params()
190 ret = snd_soc_dai_set_sysclk(codec_dai, 0, clk, in s3c24xx_uda134x_hw_params()
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| /sound/soc/adi/ |
| D | axi-spdif.c | 39 struct clk *clk; member
40 struct clk *clk_ref;
201 spdif->clk = devm_clk_get(&pdev->dev, "axi"); in axi_spdif_probe()
202 if (IS_ERR(spdif->clk)) in axi_spdif_probe()
203 return PTR_ERR(spdif->clk); in axi_spdif_probe()
209 ret = clk_prepare_enable(spdif->clk); in axi_spdif_probe()
237 clk_disable_unprepare(spdif->clk); in axi_spdif_probe()
245 clk_disable_unprepare(spdif->clk); in axi_spdif_dev_remove()
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| D | axi-i2s.c | 42 struct clk *clk; member
43 struct clk *clk_ref;
210 i2s->clk = devm_clk_get(&pdev->dev, "axi"); in axi_i2s_probe()
211 if (IS_ERR(i2s->clk)) in axi_i2s_probe()
212 return PTR_ERR(i2s->clk); in axi_i2s_probe()
218 ret = clk_prepare_enable(i2s->clk); in axi_i2s_probe()
272 clk_disable_unprepare(i2s->clk); in axi_i2s_probe()
280 clk_disable_unprepare(i2s->clk); in axi_i2s_dev_remove()
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| /sound/soc/spear/ |
| D | spdif_out.c | 35 struct clk *clk; member
69 ret = clk_enable(host->clk); in spdif_out_startup()
87 clk_disable(host->clk); in spdif_out_shutdown()
96 clk_set_rate(host->clk, core_freq); in spdif_out_clock()
97 divider = DIV_ROUND_CLOSEST(clk_get_rate(host->clk), (rate * 128)); in spdif_out_clock()
294 host->clk = devm_clk_get(&pdev->dev, NULL); in spdif_out_probe()
295 if (IS_ERR(host->clk)) in spdif_out_probe()
296 return PTR_ERR(host->clk); in spdif_out_probe()
323 clk_disable(host->clk); in spdif_out_suspend()
334 clk_enable(host->clk); in spdif_out_resume()
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| D | spdif_in.c | 35 struct clk *clk; member
124 clk_enable(host->clk); in spdif_in_trigger()
144 clk_disable(host->clk); in spdif_in_trigger()
228 host->clk = devm_clk_get(&pdev->dev, NULL); in spdif_in_probe()
229 if (IS_ERR(host->clk)) in spdif_in_probe()
230 return PTR_ERR(host->clk); in spdif_in_probe()
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| /sound/soc/pxa/ |
| D | imote2.c | 17 unsigned int clk = 0; in imote2_asoc_hw_params() local
25 clk = 12288000; in imote2_asoc_hw_params()
30 clk = 11289600; in imote2_asoc_hw_params()
34 ret = snd_soc_dai_set_sysclk(codec_dai, 0, clk, in imote2_asoc_hw_params()
40 ret = snd_soc_dai_set_sysclk(cpu_dai, PXA2XX_I2S_SYSCLK, clk, in imote2_asoc_hw_params()
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| D | mmp-sspa.c | 36 struct clk *clk; member
37 struct clk *audio_clk;
38 struct clk *sysclk;
89 clk_prepare_enable(sspa->clk); in mmp_sspa_startup()
99 clk_disable_unprepare(sspa->clk); in mmp_sspa_shutdown()
151 ret = clk_set_rate(sspa->clk, freq_out); in mmp_sspa_set_dai_pll()
265 clk_set_rate(sspa->clk, params_rate(params) * in mmp_sspa_hw_params()
484 sspa->clk = devm_clk_get(&pdev->dev, "bitclk"); in asoc_mmp_sspa_probe()
485 if (IS_ERR(sspa->clk)) in asoc_mmp_sspa_probe()
486 return PTR_ERR(sspa->clk); in asoc_mmp_sspa_probe()
[all …]
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| /sound/soc/tegra/ |
| D | tegra_asoc_machine.h | 6 struct clk;
31 struct clk *clk_pll_a_out0;
32 struct clk *clk_pll_a;
33 struct clk *clk_cdev1;
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| /sound/soc/codecs/ |
| D | uda1380.c | 535 u16 clk = uda1380_read_reg_cache(component, UDA1380_CLK); in uda1380_pcm_hw_params() local
538 if (clk & R00_DAC_CLK) { in uda1380_pcm_hw_params()
541 clk &= ~0x3; /* clear SEL_LOOP_DIV */ in uda1380_pcm_hw_params()
544 clk |= 0x0; in uda1380_pcm_hw_params()
547 clk |= 0x1; in uda1380_pcm_hw_params()
550 clk |= 0x2; in uda1380_pcm_hw_params()
553 clk |= 0x3; in uda1380_pcm_hw_params()
560 clk |= R00_EN_DAC | R00_EN_INT; in uda1380_pcm_hw_params()
562 clk |= R00_EN_ADC | R00_EN_DEC; in uda1380_pcm_hw_params()
564 uda1380_write(component, UDA1380_CLK, clk); in uda1380_pcm_hw_params()
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| /sound/ac97/ |
| D | bus.c | 398 clk_disable(codec->clk); in ac97_pm_runtime_suspend()
400 clk_disable_unprepare(codec->clk); in ac97_pm_runtime_suspend()
413 ret = clk_enable(codec->clk); in ac97_pm_runtime_resume()
415 ret = clk_prepare_enable(codec->clk); in ac97_pm_runtime_resume()
441 adev->clk = clk_get(&adev->dev, "ac97_clk"); in ac97_get_enable_clk()
442 if (IS_ERR(adev->clk)) in ac97_get_enable_clk()
443 return PTR_ERR(adev->clk); in ac97_get_enable_clk()
445 ret = clk_prepare_enable(adev->clk); in ac97_get_enable_clk()
447 clk_put(adev->clk); in ac97_get_enable_clk()
454 clk_disable_unprepare(adev->clk); in ac97_put_disable_clk()
[all …]
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| /sound/soc/hisilicon/ |
| D | hi6210-i2s.c | 37 struct clk *clk[8]; member
104 ret = clk_prepare_enable(i2s->clk[n]); in hi6210_i2s_startup()
109 ret = clk_set_rate(i2s->clk[CLK_I2S_BASE], 49152000); in hi6210_i2s_startup()
168 clk_disable_unprepare(i2s->clk[n]); in hi6210_i2s_startup()
179 clk_disable_unprepare(i2s->clk[n]); in hi6210_i2s_shutdown()
573 i2s->clk[CLK_DACODEC] = devm_clk_get(dev, "dacodec"); in hi6210_i2s_probe()
574 if (IS_ERR(i2s->clk[CLK_DACODEC])) in hi6210_i2s_probe()
575 return PTR_ERR(i2s->clk[CLK_DACODEC]); in hi6210_i2s_probe()
578 i2s->clk[CLK_I2S_BASE] = devm_clk_get(dev, "i2s-base"); in hi6210_i2s_probe()
579 if (IS_ERR(i2s->clk[CLK_I2S_BASE])) in hi6210_i2s_probe()
[all …]
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