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/tools/power/cpupower/bench/
Dbenchmark.c80 unsigned int _round, cycle; in start_benchmark() local
125 for (cycle = 0; cycle < config->cycles; cycle++) { in start_benchmark()
151 for (cycle = 0; cycle < config->cycles; cycle++) { in start_benchmark()
/tools/testing/ktest/examples/include/
Ddefaults.conf71 POWER_CYCLE = ${SCRIPTS_DIR}/${BOX}-cycle
/tools/testing/ktest/examples/
Dcrosstests.conf216 POWER_CYCLE = cycle
/tools/memory-model/Documentation/
Dglossary.txt72 extended to additional CPUs, and the result is called a "cycle".
73 In a cycle, each CPU's ordering interacts with that of the next:
82 to complete the cycle. Because of the smp_mb() calls between
Dexplanation.txt264 The counterpart to ordering is a cycle. Ordering rules out cycles:
268 involved just such an impossible cycle:
278 if those accesses would form a cycle, then the memory model predicts
1290 would generate a cycle in the hb relation: The fence would create a ppo
1421 cycle in pb, which is not possible since an instruction cannot execute
1618 Guarantee by requiring that the rb relation does not contain a cycle.
1665 a forbidden cycle. Thus the "rcu" axiom rules out this violation of
1703 forbidden cycle, violating the "rcu" axiom. Hence the outcome is not
1741 L2 ->rcu-link U0. However this cycle is not forbidden, because the
2410 various relation must not contain a cycle) doesn't apply to plain
/tools/perf/Documentation/
Dperf-dlfilter.txt91 __u64 insn_cnt; /* For instructions-per-cycle (IPC) */
92 __u64 cyc_cnt; /* For instructions-per-cycle (IPC) */
Dperf-stat.txt92 28,982 instructions # 0.34 insn per cycle
341 for metrics like instructions per cycle can be lower - as both metrics
508 313,163,853,778 instructions:u # 1.36 insn per cycle
Dsecurity.txt202 175,746,713 instructions # 0.67 insn per cycle
Dperf-intel-pt.txt147 There are two ways that instructions-per-cycle (IPC) can be calculated depending
151 calculated using the cycle count from CYC packets, otherwise MTC packets are
155 Because Intel PT does not update the cycle count on every branch or instruction,
162 instruction. If the cycle count is associated with an asynchronous branch
165 that instruction has retired when the cycle count is updated.
Dperf-script-python.txt654 insn_cnt - instruction count for determining instructions-per-cycle (IPC)
655 cyc_cnt - cycle count for determining IPC
Dperf-script.txt220 The ipc (instructions per cycle) field is synthesized and may have a value when
/tools/memory-model/litmus-tests/
DREADME163 scheme covers litmus tests having a single cycle that passes through
247 within the cycle through a given litmus test can be provided by the herd7
/tools/arch/x86/kcpuid/
Dcpuid.csv131 6, 0, EAX, 5, ecmd, Clock modulation duty cycle extension supported
221 0xA, 0, EBX, 0, pmu_no_core_cycle_evt, Core cycle event not available
/tools/bpf/bpftool/Documentation/
Dbpftool-prog.rst344 42518139 instructions # 1.06 insns per cycle (83.39%)