| /arch/arm/mach-omap2/ |
| D | omap_hwmod_2xxx_ipblock_data.c | 167 .class = &l3_hwmod_class,
174 .class = &l4_hwmod_class,
181 .class = &l4_hwmod_class,
188 .class = &mpu_hwmod_class,
195 .class = &iva_hwmod_class,
209 .class = &omap2xxx_timer_hwmod_class,
224 .class = &omap2xxx_timer_hwmod_class,
239 .class = &omap2xxx_timer_hwmod_class,
254 .class = &omap2xxx_timer_hwmod_class,
269 .class = &omap2xxx_timer_hwmod_class,
[all …]
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| D | omap_hwmod_81xx_data.c | 114 .class = &l3_hwmod_class,
121 .class = &l3_hwmod_class,
128 .class = &l3_hwmod_class,
139 .class = &l4_hwmod_class,
151 .class = &l4_hwmod_class,
173 .class = &mpu_hwmod_class,
200 .class = &mpu_hwmod_class,
241 .class = &ti81xx_rtc_hwmod_class,
288 .class = &uart_class,
309 .class = &uart_class,
[all …]
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| D | omap_hwmod_3xxx_data.c | 51 .class = &l3_hwmod_class,
58 .class = &l4_hwmod_class,
65 .class = &l4_hwmod_class,
72 .class = &l4_hwmod_class,
79 .class = &l4_hwmod_class,
87 .class = &mpu_hwmod_class,
100 .class = &iva_hwmod_class,
126 .class = &omap3xxx_debugss_hwmod_class,
161 .class = &omap3xxx_timer_hwmod_class,
176 .class = &omap3xxx_timer_hwmod_class,
[all …]
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| D | omap_hwmod.c | 272 if (!oh->class->sysc) { in _update_sysc_cache()
279 oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs); in _update_sysc_cache()
281 if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE)) in _update_sysc_cache()
297 if (!oh->class->sysc) { in _write_sysconfig()
313 if (oh->class->unlock) in _write_sysconfig()
314 oh->class->unlock(oh); in _write_sysconfig()
316 omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); in _write_sysconfig()
318 if (oh->class->lock) in _write_sysconfig()
319 oh->class->lock(oh); in _write_sysconfig()
338 if (!oh->class->sysc || in _set_master_standbymode()
[all …]
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| D | omap_hwmod_2430_data.c | 47 .class = &iva_hwmod_class,
90 .class = &i2c_class,
105 .class = &i2c_class,
120 .class = &omap2xxx_gpio_hwmod_class,
126 .class = &omap2xxx_mailbox_hwmod_class,
148 .class = &omap2xxx_mcspi_class,
180 .class = &usbotg_class,
215 .class = &omap2430_mcbsp_hwmod_class,
231 .class = &omap2430_mcbsp_hwmod_class,
247 .class = &omap2430_mcbsp_hwmod_class,
[all …]
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| D | omap_hwmod_2420_data.c | 52 .class = &iva1_hwmod_class,
71 .class = &dsp_hwmod_class,
104 .class = &i2c_class,
124 .class = &i2c_class,
131 .class = &omap2xxx_mailbox_hwmod_class,
159 .class = &omap2420_mcbsp_hwmod_class,
175 .class = &omap2420_mcbsp_hwmod_class,
205 .class = &omap2420_msdi_hwmod_class,
228 .class = &omap2_hdq1w_class,
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| D | wd_timer.c | 84 oh->class->sysc->syss_offs) in omap2_wd_timer_reset()
88 if (oh->class->sysc->srst_udelay) in omap2_wd_timer_reset()
89 udelay(oh->class->sysc->srst_udelay); in omap2_wd_timer_reset()
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| D | soc.h | 76 #define IS_OMAP_CLASS(class, id) \ argument
77 static inline int is_omap ##class (void) \
84 #define IS_AM_CLASS(class, id) \ argument
85 static inline int is_am ##class (void) \
92 #define IS_TI_CLASS(class, id) \ argument
93 static inline int is_ti ##class (void) \
100 #define IS_DRA_CLASS(class, id) \ argument
101 static inline int is_dra ##class (void) \
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| D | hdq1w.c | 52 oh->class->sysc->syss_offs) in omap_hdq1w_reset()
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| /arch/powerpc/include/asm/ |
| D | spu_priv1.h | 20 void (*int_mask_and) (struct spu *spu, int class, u64 mask);
21 void (*int_mask_or) (struct spu *spu, int class, u64 mask);
22 void (*int_mask_set) (struct spu *spu, int class, u64 mask);
23 u64 (*int_mask_get) (struct spu *spu, int class);
24 void (*int_stat_clear) (struct spu *spu, int class, u64 stat);
25 u64 (*int_stat_get) (struct spu *spu, int class);
45 spu_int_mask_and (struct spu *spu, int class, u64 mask) in spu_int_mask_and() argument
47 spu_priv1_ops->int_mask_and(spu, class, mask); in spu_int_mask_and()
51 spu_int_mask_or (struct spu *spu, int class, u64 mask) in spu_int_mask_or() argument
53 spu_priv1_ops->int_mask_or(spu, class, mask); in spu_int_mask_or()
[all …]
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| /arch/powerpc/platforms/cell/ |
| D | spu_priv1_mmio.c | 27 static void int_mask_and(struct spu *spu, int class, u64 mask) in int_mask_and() argument
31 old_mask = in_be64(&spu->priv1->int_mask_RW[class]); in int_mask_and()
32 out_be64(&spu->priv1->int_mask_RW[class], old_mask & mask); in int_mask_and()
35 static void int_mask_or(struct spu *spu, int class, u64 mask) in int_mask_or() argument
39 old_mask = in_be64(&spu->priv1->int_mask_RW[class]); in int_mask_or()
40 out_be64(&spu->priv1->int_mask_RW[class], old_mask | mask); in int_mask_or()
43 static void int_mask_set(struct spu *spu, int class, u64 mask) in int_mask_set() argument
45 out_be64(&spu->priv1->int_mask_RW[class], mask); in int_mask_set()
48 static u64 int_mask_get(struct spu *spu, int class) in int_mask_get() argument
50 return in_be64(&spu->priv1->int_mask_RW[class]); in int_mask_get()
[all …]
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| D | interrupt.c | 53 unsigned char class = bits.class & 3; in iic_pending_to_hwnum() local
59 return (node << IIC_IRQ_NODE_SHIFT) | (class << 4) | unit; in iic_pending_to_hwnum()
232 unsigned int node, ext, unit, class; in iic_host_xlate() local
246 class = (intspec[0] >> 8) & 0xff; in iic_host_xlate()
255 if (unit == IIC_UNIT_IIC && class == 1) in iic_host_xlate()
259 (class << IIC_IRQ_CLASS_SHIFT) | unit; in iic_host_xlate()
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| /arch/powerpc/perf/ |
| D | mpc7450-pmu.c | 153 int pmc, class; in mpc7450_get_constraint() local
157 class = mpc7450_classify_event(event); in mpc7450_get_constraint()
158 if (class < 0) in mpc7450_get_constraint()
160 if (class == 4) { in mpc7450_get_constraint()
165 mask = classbits[class][0]; in mpc7450_get_constraint()
166 value = classbits[class][1]; in mpc7450_get_constraint()
266 int i, j, class, tuse; in mpc7450_compute_mmcr() local
278 class = mpc7450_classify_event(event[i]); in mpc7450_compute_mmcr()
279 if (class < 0) in mpc7450_compute_mmcr()
281 j = n_classevent[class]++; in mpc7450_compute_mmcr()
[all …]
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| /arch/alpha/kernel/ |
| D | err_common.c | 96 if (header->class != EL_CLASS__HEADER) { in el_process_header_subpacket()
99 header->class, header->type); in el_process_header_subpacket()
134 header->class, header->type); in el_process_header_subpacket()
142 header->class, header->type); in el_process_header_subpacket()
162 for (; h && h->class != header->class; h = h->next); in el_process_subpacket_reg()
199 switch(header->class) { in el_process_subpacket()
211 header->class, header->type); in el_process_subpacket()
226 if (a->class == header->class && in el_annotate_subpacket()
252 for (err = 0; header && (header->class != EL_CLASS__TERMINATION); err++) in cdl_process_console_data_log()
287 if ((a->class == new->class && a->type == new->type) || in cdl_register_subpacket_annotation()
[all …]
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| D | err_ev7.c | 33 if (el_ptr->class != EL_CLASS__HEADER || in ev7_collect_logout_frame_subpackets()
46 if (el_ptr->class != EL_CLASS__PAL || in ev7_collect_logout_frame_subpackets()
65 if (subpacket->class != EL_CLASS__PAL) { in ev7_collect_logout_frame_subpackets()
68 err_print_prefix, subpacket->class, i); in ev7_collect_logout_frame_subpackets()
239 if (header->class != EL_CLASS__PAL) { in ev7_process_pal_subpacket()
242 header->class, header->type); in ev7_process_pal_subpacket()
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| D | pci.c | 66 dev->class = PCI_CLASS_BRIDGE_ISA << 8; in quirk_isa_bridge()
77 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE) { in quirk_cypress()
95 if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA) { in quirk_cypress()
111 unsigned int class = dev->class >> 8; in pcibios_fixup_final() local
113 if (class == PCI_CLASS_BRIDGE_ISA || class == PCI_CLASS_BRIDGE_EISA) { in pcibios_fixup_final()
259 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { in pcibios_fixup_bus()
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| D | err_impl.h | 19 u16 class; member
29 u16 class; member
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| /arch/powerpc/platforms/ps3/ |
| D | spu.c | 462 static void int_mask_and(struct spu *spu, int class, u64 mask) in int_mask_and() argument
467 old_mask = spu_int_mask_get(spu, class); in int_mask_and()
468 spu_int_mask_set(spu, class, old_mask & mask); in int_mask_and()
471 static void int_mask_or(struct spu *spu, int class, u64 mask) in int_mask_or() argument
475 old_mask = spu_int_mask_get(spu, class); in int_mask_or()
476 spu_int_mask_set(spu, class, old_mask | mask); in int_mask_or()
479 static void int_mask_set(struct spu *spu, int class, u64 mask) in int_mask_set() argument
481 spu_pdata(spu)->cache.masks[class] = mask; in int_mask_set()
482 lv1_set_spe_interrupt_mask(spu_pdata(spu)->spe_id, class, in int_mask_set()
483 spu_pdata(spu)->cache.masks[class]); in int_mask_set()
[all …]
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| /arch/mips/include/asm/ |
| D | mips_mt.h | 28 struct class;
29 extern struct class *mt_class;
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| /arch/x86/ia32/ |
| D | Makefile | 10 audit-class-$(CONFIG_AUDIT) := audit.o
11 obj-$(CONFIG_IA32_EMULATION) += $(audit-class-y)
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| /arch/powerpc/platforms/book3s/ |
| D | vas-api.c | 46 struct class *class; member
441 coproc_device.class = class_create(mod, name); in vas_register_coproc_api()
442 if (IS_ERR(coproc_device.class)) { in vas_register_coproc_api()
443 rc = PTR_ERR(coproc_device.class); in vas_register_coproc_api()
447 coproc_device.class->devnode = coproc_devnode; in vas_register_coproc_api()
461 coproc_device.device = device_create(coproc_device.class, NULL, in vas_register_coproc_api()
477 class_destroy(coproc_device.class); in vas_register_coproc_api()
489 device_destroy(coproc_device.class, devno); in vas_unregister_coproc_api()
491 class_destroy(coproc_device.class); in vas_unregister_coproc_api()
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| /arch/mips/pci/ |
| D | fixup-cobalt.c | 42 (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) { in qube_raq_galileo_early_fixup()
44 dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff); in qube_raq_galileo_early_fixup()
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| /arch/parisc/math-emu/ |
| D | fpudispatch.c | 184 u_int class, subop; in fpudispatch() local
194 class = get_class(ir); in fpudispatch()
195 if (class == 1) { in fpudispatch()
204 if (FPUDEBUG) printk("class %d subop %d\n", class, subop); in fpudispatch()
209 return(decode_0c(ir,class,subop,fpregs)); in fpudispatch()
211 return(decode_0e(ir,class,subop,fpregs)); in fpudispatch()
239 u_int class, subop, major; in emfpudispatch() local
248 class = get_class(ir); in emfpudispatch()
249 if (class == 1) { in emfpudispatch()
259 return(decode_0c(ir,class,subop,fpregs)); in emfpudispatch()
[all …]
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| /arch/arm/mach-omap1/include/mach/ |
| D | soc.h | 86 #define IS_OMAP_CLASS(class, id) \ argument
87 static inline int is_omap ##class (void) \
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| /arch/arm/kernel/ |
| D | bios32.c | 148 dev->class &= 0xff; in pci_fixup_dec21285()
149 dev->class |= PCI_CLASS_BRIDGE_HOST << 8; in pci_fixup_dec21285()
167 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) in pci_fixup_ide_bases()
207 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) { in pci_fixup_cy82c693()
210 if (dev->class & 0x80) { /* primary */ in pci_fixup_cy82c693()
299 switch (dev->class >> 8) { in pcibios_fixup_bus()
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