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Searched refs:set_rate (Results 1 – 8 of 8) sorted by relevance

/arch/arm/mach-omap1/
Dclock_data.c113 .set_rate = &omap1_set_sossi_rate,
123 .set_rate = omap1_clk_set_rate_ckctl_arm,
137 .set_rate = omap1_clk_set_rate_ckctl_arm,
217 .set_rate = omap1_clk_set_rate_ckctl_arm,
227 .set_rate = omap1_clk_set_rate_ckctl_arm,
239 .set_rate = &omap1_clk_set_rate_dsp_domain,
269 .set_rate = omap1_clk_set_rate_ckctl_arm,
390 .set_rate = omap1_clk_set_rate_ckctl_arm,
404 .set_rate = omap1_clk_set_rate_ckctl_arm,
424 .set_rate = &omap1_set_uart_rate,
[all …]
Dclock.h148 int (*set_rate)(struct clk *, unsigned long); member
Dclock.c570 if (clk->set_rate) in omap1_clk_set_rate()
571 ret = clk->set_rate(clk, rate); in omap1_clk_set_rate()
/arch/arm/mach-ep93xx/
Dclock.c36 int (*set_rate)(struct clk *clk, unsigned long rate); member
96 .set_rate = set_keytchclk_rate,
103 .set_rate = set_keytchclk_rate,
118 .set_rate = set_div_rate,
125 .set_rate = set_div_rate,
133 .set_rate = set_i2s_sclk_rate,
141 .set_rate = set_i2s_lrclk_rate,
476 if (clk->set_rate) in clk_set_rate()
477 return clk->set_rate(clk, rate); in clk_set_rate()
/arch/sh/kernel/cpu/sh4/
Dclock-sh4-202.c81 if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0) in shoc_clk_init()
133 .set_rate = shoc_clk_set_rate,
/arch/arm/mach-omap2/
Dclkt2xxx_virt_prcm_set.c215 .set_rate = &omap2_select_table_rate,
/arch/mips/alchemy/common/
Dclock.c236 .set_rate = alchemy_clk_aux_setr,
589 .set_rate = alchemy_clk_fgv1_setr,
730 .set_rate = alchemy_clk_fgv2_setr,
938 .set_rate = alchemy_clk_csrc_setr,
/arch/arm/mach-vexpress/
Dspc.c527 .set_rate = spc_set_rate,