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Searched refs:CDCE706_PLL_FREQ_MIN (Results 1 – 1 of 1) sorted by relevance

/drivers/clk/
Dclk-cdce706.c46 #define CDCE706_PLL_FREQ_MIN 80000000 macro
313 for (div = CDCE706_PLL_FREQ_MIN / rate; best_diff && in cdce706_divider_round_rate()
320 if (rate * div < CDCE706_PLL_FREQ_MIN) in cdce706_divider_round_rate()