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Searched refs:DPCS_BASE__INST1_SEG5 (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/include/
Ddimgrey_cavefish_ip_offset.h424 #define DPCS_BASE__INST1_SEG5 0 macro
Dbeige_goby_ip_offset.h502 #define DPCS_BASE__INST1_SEG5 0 macro
Dyellow_carp_offset.h447 #define DPCS_BASE__INST1_SEG5 0 macro
Dvangogh_ip_offset.h520 #define DPCS_BASE__INST1_SEG5 0 macro