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Searched refs:MASTER_COMM_CNTL_REG (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dce/
Ddce_dmcu.c144 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_dmcu_set_psr_enable()
157 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dce_dmcu_set_psr_enable()
238 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_dmcu_setup_psr()
280 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dce_dmcu_setup_psr()
315 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); in dce_psr_wait_loop()
326 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dce_psr_wait_loop()
369 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); in dcn10_dmcu_enable_fractional_pwm()
379 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dcn10_dmcu_enable_fractional_pwm()
382 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); in dcn10_dmcu_enable_fractional_pwm()
419 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); in dcn10_dmcu_init()
[all …]
Ddce_abm.c66 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_abm_set_pipe()
78 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dce_abm_set_pipe()
80 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_abm_set_pipe()
106 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, in dmcu_set_backlight_level()
121 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dmcu_set_backlight_level()
134 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, in dmcu_set_backlight_level()
206 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_abm_set_level()
215 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dce_abm_set_level()
Ddce_dmcu.h42 SR(MASTER_COMM_CNTL_REG), \
64 SR(MASTER_COMM_CNTL_REG), \
81 SR(MASTER_COMM_CNTL_REG), \
118 DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
146 DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh)
164 DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
219 uint32_t MASTER_COMM_CNTL_REG; member
Ddce_abm.h33 SR(MASTER_COMM_CNTL_REG), \
119 ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
231 uint32_t MASTER_COMM_CNTL_REG; member
Ddce_link_encoder.h152 uint32_t MASTER_COMM_CNTL_REG; member