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Searched refs:OWNER (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/nouveau/dispnv50/
Dbase907c.c170 NVDEF(NV907C, SET_CSC_RED2RED, OWNER, CORE)); in base907c_csc_clr()
184 NVDEF(NV907C, SET_CSC_RED2RED, OWNER, BASE) | in base907c_csc_set()
Dcorec37d.c45 NVDEF(NVC37D, WINDOW_SET_CONTROL, OWNER, HEAD(i >> 1))); in corec37d_wndw_owner()
Ddisp.c523 const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE); in nv50_dac_atomic_disable()
541 case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break; in nv50_dac_atomic_enable()
542 case 1: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break; in nv50_dac_atomic_enable()
1674 if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE)) in nv50_sor_update()
1975 const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE); in nv50_pior_atomic_disable()
1993 case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break; in nv50_pior_atomic_enable()
1994 case 1: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break; in nv50_pior_atomic_enable()
/drivers/gpu/drm/tegra/
Ddc.h739 #define OWNER(x) (((x) & 0xf) << 0) macro
Dhub.c286 value |= OWNER(new->pipe); in tegra_shared_plane_set_owner()