| /drivers/gpu/drm/amd/amdgpu/ |
| D | yellow_carp_reg_init.c | 48 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); in yellow_carp_reg_base_init()
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| D | vangogh_reg_init.c | 48 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); in vangogh_reg_base_init()
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| D | navi12_reg_init.c | 48 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); in navi12_reg_base_init()
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| D | navi10_reg_init.c | 48 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); in navi10_reg_base_init()
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| D | navi14_reg_init.c | 48 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); in navi14_reg_base_init()
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| D | beige_goby_reg_init.c | 51 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); in beige_goby_reg_base_init()
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| D | sienna_cichlid_reg_init.c | 51 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); in sienna_cichlid_reg_base_init()
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| D | dimgrey_cavefish_reg_init.c | 51 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
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| D | aldebaran_reg_init.c | 49 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); in aldebaran_reg_base_init()
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| D | arct_reg_init.c | 53 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); in arct_reg_base_init()
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| D | vega10_reg_init.c | 52 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); in vega10_reg_base_init()
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| D | vega20_reg_init.c | 50 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); in vega20_reg_base_init()
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| /drivers/gpu/drm/amd/include/ |
| D | cyan_skillfish_ip_offset.h | 117 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0 } }, variable
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| D | navi10_ip_offset.h | 121 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0, 0 } }, variable
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| D | vega20_ip_offset.h | 129 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0, 0 } }, variable
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| D | navi12_ip_offset.h | 165 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } }, variable
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| D | dimgrey_cavefish_ip_offset.h | 144 static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } }, variable
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| D | navi14_ip_offset.h | 165 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } }, variable
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| D | sienna_cichlid_ip_offset.h | 172 static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0 } }, variable
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| D | beige_goby_ip_offset.h | 173 static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } }, variable
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| D | renoir_ip_offset.h | 205 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } }, variable
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| D | vega10_ip_offset.h | 188 static const struct IP_BASE __maybe_unused THM_BASE = { { { { 0x00016600, 0, 0, 0, 0 } }, variable
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| D | yellow_carp_offset.h | 167 static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } }, variable
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| D | vangogh_ip_offset.h | 194 static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } }, variable
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| D | arct_ip_offset.h | 205 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0, 0 } }, variable
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