| /drivers/clk/ti/ |
| D | clk-7xx.c | 22 static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
27 static const struct omap_clkctrl_reg_data dra7_dsp1_clkctrl_regs[] __initconst = {
32 static const char * const dra7_ipu1_gfclk_mux_parents[] __initconst = {
38 static const struct omap_clkctrl_bit_data dra7_mmu_ipu1_bit_data[] __initconst = {
43 static const struct omap_clkctrl_reg_data dra7_ipu1_clkctrl_regs[] __initconst = {
48 static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = {
56 static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = {
74 static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = {
81 static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = {
97 static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = {
[all …]
|
| D | clk-44xx.c | 34 static const struct omap_clkctrl_reg_data omap4_mpuss_clkctrl_regs[] __initconst = {
39 static const struct omap_clkctrl_reg_data omap4_tesla_clkctrl_regs[] __initconst = {
44 static const char * const omap4_aess_fclk_parents[] __initconst = {
49 static const struct omap_clkctrl_div_data omap4_aess_fclk_data __initconst = { variable
53 static const struct omap_clkctrl_bit_data omap4_aess_bit_data[] __initconst = {
58 static const char * const omap4_func_dmic_abe_gfclk_parents[] __initconst = {
65 static const char * const omap4_dmic_sync_mux_ck_parents[] __initconst = {
72 static const struct omap_clkctrl_bit_data omap4_dmic_bit_data[] __initconst = {
78 static const char * const omap4_func_mcasp_abe_gfclk_parents[] __initconst = {
85 static const struct omap_clkctrl_bit_data omap4_mcasp_bit_data[] __initconst = {
[all …]
|
| D | clk-7xx-compat.c | 22 static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
27 static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = {
35 static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = {
53 static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = {
60 static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = {
76 static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = {
81 static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = {
86 static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = {
91 static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = {
96 static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = {
[all …]
|
| D | clk-54xx.c | 28 static const struct omap_clkctrl_reg_data omap5_mpu_clkctrl_regs[] __initconst = {
33 static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst = {
38 static const char * const omap5_aess_fclk_parents[] __initconst = {
43 static const struct omap_clkctrl_div_data omap5_aess_fclk_data __initconst = { variable
47 static const struct omap_clkctrl_bit_data omap5_aess_bit_data[] __initconst = {
52 static const char * const omap5_dmic_gfclk_parents[] __initconst = {
59 static const char * const omap5_dmic_sync_mux_ck_parents[] __initconst = {
66 static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = {
72 static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = {
79 static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst = {
[all …]
|
| D | clk-33xx.c | 26 static const char * const am3_gpio1_dbclk_parents[] __initconst = {
31 static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {
36 static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {
41 static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
46 static const struct omap_clkctrl_reg_data am3_l4ls_clkctrl_regs[] __initconst = {
81 static const struct omap_clkctrl_reg_data am3_l3s_clkctrl_regs[] __initconst = {
90 static const struct omap_clkctrl_reg_data am3_l3_clkctrl_regs[] __initconst = {
104 static const struct omap_clkctrl_reg_data am3_l4hs_clkctrl_regs[] __initconst = {
109 static const struct omap_clkctrl_reg_data am3_pruss_ocp_clkctrl_regs[] __initconst = {
114 static const struct omap_clkctrl_reg_data am3_cpsw_125mhz_clkctrl_regs[] __initconst = {
[all …]
|
| D | clk-43xx.c | 26 static const struct omap_clkctrl_reg_data am4_l3s_tsc_clkctrl_regs[] __initconst = {
31 static const char * const am4_synctimer_32kclk_parents[] __initconst = {
36 static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst = {
41 static const struct omap_clkctrl_reg_data am4_l4_wkup_aon_clkctrl_regs[] __initconst = {
47 static const char * const am4_gpio0_dbclk_parents[] __initconst = {
52 static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = {
57 static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = {
70 static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = {
75 static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {
80 static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = {
[all …]
|
| D | clk-33xx-compat.c | 26 static const char * const am3_gpio1_dbclk_parents[] __initconst = {
31 static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {
36 static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {
41 static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
46 static const struct omap_clkctrl_reg_data am3_l4_per_clkctrl_regs[] __initconst = {
101 static const char * const am3_gpio0_dbclk_parents[] __initconst = {
106 static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
111 static const char * const am3_dbg_sysclk_ck_parents[] __initconst = {
116 static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = {
122 static const char * const am3_trace_clk_div_ck_parents[] __initconst = {
[all …]
|
| D | clk-43xx-compat.c | 26 static const char * const am4_synctimer_32kclk_parents[] __initconst = {
31 static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst = {
36 static const char * const am4_gpio0_dbclk_parents[] __initconst = {
41 static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = {
46 static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = {
62 static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = {
67 static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {
72 static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = {
77 static const char * const am4_usb_otg_ss0_refclk960m_parents[] __initconst = {
82 static const struct omap_clkctrl_bit_data am4_usb_otg_ss0_bit_data[] __initconst = {
[all …]
|
| /drivers/soc/renesas/ |
| D | renesas-soc.c | 21 static const struct renesas_family fam_rcar_gen1 __initconst __maybe_unused = {
26 static const struct renesas_family fam_rcar_gen2 __initconst __maybe_unused = {
31 static const struct renesas_family fam_rcar_gen3 __initconst __maybe_unused = {
36 static const struct renesas_family fam_rmobile __initconst __maybe_unused = {
41 static const struct renesas_family fam_rza1 __initconst __maybe_unused = {
45 static const struct renesas_family fam_rza2 __initconst __maybe_unused = {
49 static const struct renesas_family fam_rzg1 __initconst __maybe_unused = {
54 static const struct renesas_family fam_rzg2 __initconst __maybe_unused = {
59 static const struct renesas_family fam_rzg2l __initconst __maybe_unused = {
63 static const struct renesas_family fam_shmobile __initconst __maybe_unused = {
[all …]
|
| /drivers/clk/mediatek/ |
| D | clk-mt8173.c | 26 static const struct mtk_fixed_clk fixed_clks[] __initconst = {
35 static const struct mtk_fixed_factor top_divs[] __initconst = {
131 static const char * const axi_parents[] __initconst = {
142 static const char * const mem_parents[] __initconst = {
147 static const char * const ddrphycfg_parents[] __initconst = {
152 static const char * const mm_parents[] __initconst = {
164 static const char * const pwm_parents[] __initconst = {
171 static const char * const vdec_parents[] __initconst = {
184 static const char * const venc_parents[] __initconst = {
197 static const char * const mfg_parents[] __initconst = {
[all …]
|
| D | clk-mt8167.c | 22 static const struct mtk_fixed_clk fixed_clks[] __initconst = {
31 static const struct mtk_fixed_factor top_divs[] __initconst = {
87 static const char * const uart0_parents[] __initconst = {
92 static const char * const gfmux_emi1x_parents[] __initconst = {
97 static const char * const emi_ddrphy_parents[] __initconst = {
102 static const char * const ahb_infra_parents[] __initconst = {
118 static const char * const csw_mux_mfg_parents[] __initconst = {
129 static const char * const msdc0_parents[] __initconst = {
140 static const char * const camtg_mm_parents[] __initconst = {
148 static const char * const pwm_mm_parents[] __initconst = {
[all …]
|
| D | clk-mt8135.c | 19 static const struct mtk_fixed_factor root_clk_alias[] __initconst = {
26 static const struct mtk_fixed_factor top_divs[] __initconst = {
102 static const char * const axi_parents[] __initconst = {
112 static const char * const smi_parents[] __initconst = {
130 static const char * const mfg_parents[] __initconst = {
146 static const char * const irda_parents[] __initconst = {
152 static const char * const cam_parents[] __initconst = {
163 static const char * const aud_intbus_parents[] __initconst = {
169 static const char * const jpg_parents[] __initconst = {
179 static const char * const disp_parents[] __initconst = {
[all …]
|
| D | clk-mt8516.c | 21 static const struct mtk_fixed_clk fixed_clks[] __initconst = {
27 static const struct mtk_fixed_factor top_divs[] __initconst = {
73 static const char * const uart0_parents[] __initconst = {
78 static const char * const ahb_infra_parents[] __initconst = {
94 static const char * const msdc0_parents[] __initconst = {
105 static const char * const uart1_parents[] __initconst = {
110 static const char * const msdc1_parents[] __initconst = {
121 static const char * const pmicspi_parents[] __initconst = {
128 static const char * const qaxi_aud26m_parents[] __initconst = {
133 static const char * const aud_intbus_parents[] __initconst = {
[all …]
|
| /drivers/pinctrl/samsung/ |
| D | pinctrl-exynos-arm64.c | 65 static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst = {
79 static const struct samsung_pin_bank_data exynos5433_pin_banks1[] __initconst = {
86 static const struct samsung_pin_bank_data exynos5433_pin_banks2[] __initconst = {
92 static const struct samsung_pin_bank_data exynos5433_pin_banks3[] __initconst = {
98 static const struct samsung_pin_bank_data exynos5433_pin_banks4[] __initconst = {
104 static const struct samsung_pin_bank_data exynos5433_pin_banks5[] __initconst = {
115 static const struct samsung_pin_bank_data exynos5433_pin_banks6[] __initconst = {
121 static const struct samsung_pin_bank_data exynos5433_pin_banks7[] __initconst = {
127 static const struct samsung_pin_bank_data exynos5433_pin_banks8[] __initconst = {
149 static const struct samsung_pin_bank_data exynos5433_pin_banks9[] __initconst = {
[all …]
|
| D | pinctrl-exynos-arm.c | 86 static const struct samsung_retention_data s5pv210_retention_data __initconst = { variable
91 static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = {
129 static const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = {
142 const struct samsung_pinctrl_of_match_data s5pv210_of_data __initconst = { variable
151 static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = {
163 static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = {
199 static const struct samsung_retention_data exynos3250_retention_data __initconst = { variable
211 static const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = {
232 const struct samsung_pinctrl_of_match_data exynos3250_of_data __initconst = { variable
238 static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = {
[all …]
|
| /drivers/clk/samsung/ |
| D | clk-s5pv210.c | 129 static const char *const fin_pll_p[] __initconst = {
134 static const char *const mout_apll_p[] __initconst = {
139 static const char *const mout_mpll_p[] __initconst = {
144 static const char *const mout_epll_p[] __initconst = {
149 static const char *const mout_vpllsrc_p[] __initconst = {
154 static const char *const mout_vpll_p[] __initconst = {
159 static const char *const mout_group1_p[] __initconst = {
166 static const char *const mout_group2_p[] __initconst = {
178 static const char *const mout_audio0_p[] __initconst = {
190 static const char *const mout_audio1_p[] __initconst = {
[all …]
|
| D | clk-exynos7.c | 35 static const struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initconst = {
68 static const unsigned long topc_clk_regs[] __initconst = {
88 static const struct samsung_mux_clock topc_mux_clks[] __initconst = {
117 static const struct samsung_div_clock topc_div_clks[] __initconst = {
138 static const struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initconst = {
143 static const struct samsung_gate_clock topc_gate_clks[] __initconst = {
173 static const struct samsung_pll_clock topc_pll_clks[] __initconst = {
186 static const struct samsung_cmu_info topc_cmu_info __initconst = { variable
255 static const unsigned long top0_clk_regs[] __initconst = {
274 static const struct samsung_mux_clock top0_mux_clks[] __initconst = {
[all …]
|
| D | clk-exynos5260.c | 22 static const struct samsung_pll_rate_table pll2550_24mhz_tbl[] __initconst = {
55 static const struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initconst = {
78 static const unsigned long aud_clk_regs[] __initconst = {
92 static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
101 static const struct samsung_div_clock aud_div_clks[] __initconst = {
113 static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
131 static const struct samsung_cmu_info aud_cmu __initconst = { variable
154 static const unsigned long disp_clk_regs[] __initconst = {
201 static const struct samsung_mux_clock disp_mux_clks[] __initconst = {
270 static const struct samsung_div_clock disp_div_clks[] __initconst = {
[all …]
|
| D | clk-exynos5433.c | 115 static const unsigned long top_clk_regs[] __initconst = {
236 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
240 static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = {
256 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
392 static const struct samsung_div_clock top_div_clks[] __initconst = {
556 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
714 static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = {
767 static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = {
781 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
788 static const struct samsung_cmu_info top_cmu_info __initconst = { variable
[all …]
|
| /drivers/soc/rockchip/ |
| D | grf.c | 30 static const struct rockchip_grf_value rk3036_defaults[] __initconst = {
38 static const struct rockchip_grf_info rk3036_grf __initconst = { variable
45 static const struct rockchip_grf_value rk3128_defaults[] __initconst = {
49 static const struct rockchip_grf_info rk3128_grf __initconst = { variable
56 static const struct rockchip_grf_value rk3228_defaults[] __initconst = {
60 static const struct rockchip_grf_info rk3228_grf __initconst = { variable
68 static const struct rockchip_grf_value rk3288_defaults[] __initconst = {
73 static const struct rockchip_grf_info rk3288_grf __initconst = { variable
80 static const struct rockchip_grf_value rk3328_defaults[] __initconst = {
84 static const struct rockchip_grf_info rk3328_grf __initconst = { variable
[all …]
|
| /drivers/clk/hisilicon/ |
| D | clk-hi3620.c | 25 static const char *const timer0_mux_p[] __initconst = { "osc32k", "timerclk01", };
26 static const char *const timer1_mux_p[] __initconst = { "osc32k", "timerclk01", };
27 static const char *const timer2_mux_p[] __initconst = { "osc32k", "timerclk23", };
28 static const char *const timer3_mux_p[] __initconst = { "osc32k", "timerclk23", };
29 static const char *const timer4_mux_p[] __initconst = { "osc32k", "timerclk45", };
30 static const char *const timer5_mux_p[] __initconst = { "osc32k", "timerclk45", };
31 static const char *const timer6_mux_p[] __initconst = { "osc32k", "timerclk67", };
32 static const char *const timer7_mux_p[] __initconst = { "osc32k", "timerclk67", };
33 static const char *const timer8_mux_p[] __initconst = { "osc32k", "timerclk89", };
34 static const char *const timer9_mux_p[] __initconst = { "osc32k", "timerclk89", };
[all …]
|
| /drivers/clk/mvebu/ |
| D | mv98dx3236.c | 50 static const u32 mv98dx3236_cpu_frequencies[] __initconst = {
60 static const u32 mv98dx4251_cpu_frequencies[] __initconst = {
92 static const struct coreclk_ratio mv98dx3236_core_ratios[] __initconst = {
97 static const int __initconst mv98dx3236_cpu_mpll_ratios[8][2] = {
102 static const int __initconst mv98dx3236_cpu_ddr_ratios[8][2] = {
107 static const int __initconst mv98dx4251_cpu_mpll_ratios[8][2] = {
112 static const int __initconst mv98dx4251_cpu_ddr_ratios[8][2] = {
158 static const struct clk_gating_soc_desc mv98dx3236_gating_desc[] __initconst = {
|
| D | armada-370.c | 34 static const struct coreclk_ratio a370_coreclk_ratios[] __initconst = {
40 static const u32 a370_tclk_freqs[] __initconst = {
54 static const u32 a370_cpu_freqs[] __initconst = {
80 static const int a370_nbclk_ratios[32][2] __initconst = {
91 static const int a370_hclk_ratios[32][2] __initconst = {
102 static const int a370_dramclk_ratios[32][2] __initconst = {
154 static const struct clk_gating_soc_desc a370_gating_desc[] __initconst = {
|
| D | armada-375.c | 45 static const u32 armada_375_tclk_frequencies[] __initconst = {
60 static const u32 armada_375_cpu_frequencies[] __initconst = {
87 static const struct coreclk_ratio armada_375_coreclk_ratios[] __initconst = {
92 static const int armada_375_cpu_l2_ratios[32][2] __initconst = {
103 static const int armada_375_cpu_ddr_ratios[32][2] __initconst = {
150 static const struct clk_gating_soc_desc armada_375_gating_desc[] __initconst = {
|
| /drivers/clk/sunxi/ |
| D | clk-sunxi.c | 490 static const struct factors_data sun4i_pll1_data __initconst = { variable
496 static const struct factors_data sun6i_a31_pll1_data __initconst = { variable
502 static const struct factors_data sun8i_a23_pll1_data __initconst = { variable
508 static const struct factors_data sun7i_a20_pll4_data __initconst = { variable
514 static const struct factors_data sun4i_pll5_data __initconst = { variable
520 static const struct factors_data sun6i_a31_pll6_data __initconst = { variable
526 static const struct factors_data sun5i_a13_ahb_data __initconst = { variable
533 static const struct factors_data sun6i_ahb1_data __initconst = { variable
541 static const struct factors_data sun4i_apb1_data __initconst = { variable
548 static const struct factors_data sun7i_a20_out_data __initconst = { variable
[all …]
|