Searched refs:max_tile_pipes (Results 1 – 18 of 18) sorted by relevance
378 *value = rdev->config.cik.max_tile_pipes; in radeon_info_ioctl()380 *value = rdev->config.si.max_tile_pipes; in radeon_info_ioctl()382 *value = rdev->config.cayman.max_tile_pipes; in radeon_info_ioctl()384 *value = rdev->config.evergreen.max_tile_pipes; in radeon_info_ioctl()386 *value = rdev->config.rv770.max_tile_pipes; in radeon_info_ioctl()388 *value = rdev->config.r600.max_tile_pipes; in radeon_info_ioctl()
1205 rdev->config.rv770.max_tile_pipes = 8; in rv770_gpu_init()1225 rdev->config.rv770.max_tile_pipes = 4; in rv770_gpu_init()1249 rdev->config.rv770.max_tile_pipes = 2; in rv770_gpu_init()1269 rdev->config.rv770.max_tile_pipes = 4; in rv770_gpu_init()1331 switch (rdev->config.rv770.max_tile_pipes) { in rv770_gpu_init()1346 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; in rv770_gpu_init()
3160 rdev->config.evergreen.max_tile_pipes = 8; in evergreen_gpu_init()3182 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3204 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3227 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()3249 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()3271 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3299 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3321 rdev->config.evergreen.max_tile_pipes = 8; in evergreen_gpu_init()3343 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3365 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()[all …]
2047 unsigned max_tile_pipes; member2069 unsigned max_tile_pipes; member2096 unsigned max_tile_pipes; member2123 unsigned max_tile_pipes; member2161 unsigned max_tile_pipes; member2192 unsigned max_tile_pipes; member
2008 rdev->config.r600.max_tile_pipes = 8; in r600_gpu_init()2024 rdev->config.r600.max_tile_pipes = 2; in r600_gpu_init()2042 rdev->config.r600.max_tile_pipes = 1; in r600_gpu_init()2057 rdev->config.r600.max_tile_pipes = 4; in r600_gpu_init()2088 switch (rdev->config.r600.max_tile_pipes) { in r600_gpu_init()2104 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; in r600_gpu_init()
3100 rdev->config.si.max_tile_pipes = 12; in si_gpu_init()3117 rdev->config.si.max_tile_pipes = 8; in si_gpu_init()3135 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()3152 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()3169 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()3206 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes; in si_gpu_init()
895 rdev->config.cayman.max_tile_pipes = 8; in cayman_gpu_init()919 rdev->config.cayman.max_tile_pipes = 2; in cayman_gpu_init()
2346 num_pipe_configs = rdev->config.cik.max_tile_pipes; in cik_tiling_mode_table_init()3179 rdev->config.cik.max_tile_pipes = 4; in cik_gpu_init()3196 rdev->config.cik.max_tile_pipes = 16; in cik_gpu_init()3213 rdev->config.cik.max_tile_pipes = 4; in cik_gpu_init()3232 rdev->config.cik.max_tile_pipes = 2; in cik_gpu_init()3267 rdev->config.cik.num_tile_pipes = rdev->config.cik.max_tile_pipes; in cik_gpu_init()
149 unsigned max_tile_pipes; member
1587 adev->gfx.config.max_tile_pipes = 12; in gfx_v6_0_constants_init()1604 adev->gfx.config.max_tile_pipes = 8; in gfx_v6_0_constants_init()1621 adev->gfx.config.max_tile_pipes = 4; in gfx_v6_0_constants_init()1638 adev->gfx.config.max_tile_pipes = 4; in gfx_v6_0_constants_init()1655 adev->gfx.config.max_tile_pipes = 4; in gfx_v6_0_constants_init()1684 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v6_0_constants_init()
4284 adev->gfx.config.max_tile_pipes = 4; in gfx_v7_0_gpu_early_init()4301 adev->gfx.config.max_tile_pipes = 16; in gfx_v7_0_gpu_early_init()4318 adev->gfx.config.max_tile_pipes = 4; in gfx_v7_0_gpu_early_init()4337 adev->gfx.config.max_tile_pipes = 2; in gfx_v7_0_gpu_early_init()4362 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v7_0_gpu_early_init()
1704 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()1721 adev->gfx.config.max_tile_pipes = 16; in gfx_v8_0_gpu_early_init()1768 adev->gfx.config.max_tile_pipes = 8; in gfx_v8_0_gpu_early_init()1785 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()1802 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()1819 adev->gfx.config.max_tile_pipes = 4; in gfx_v8_0_gpu_early_init()1844 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v8_0_gpu_early_init()
726 adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes; in amdgpu_atombios_get_gfx_info()
605 config[no_regs++] = adev->gfx.config.max_tile_pipes; in amdgpu_debugfs_gca_config_read()
2245 adev->gfx.config.max_tile_pipes = in gfx_v9_0_gpu_early_init()
4732 adev->gfx.config.max_tile_pipes = in gfx_v10_0_gpu_early_init()
1556 uint8_t max_tile_pipes; member1576 uint8_t max_tile_pipes; member
5653 UCHAR max_tile_pipes; member5666 UCHAR max_tile_pipes; member