| /drivers/thermal/qcom/ |
| D | tsens-v0_1.c | 229 u32 p1[5], p2[5]; in calibrate_8916() local
259 p1[0] = (qfprom_cdata[0] & MSM8916_S0_P1_MASK) >> MSM8916_S0_P1_SHIFT; in calibrate_8916()
260 p1[1] = (qfprom_cdata[0] & MSM8916_S1_P1_MASK) >> MSM8916_S1_P1_SHIFT; in calibrate_8916()
261 p1[2] = (qfprom_cdata[0] & MSM8916_S2_P1_MASK) >> MSM8916_S2_P1_SHIFT; in calibrate_8916()
262 p1[3] = (qfprom_cdata[1] & MSM8916_S3_P1_MASK) >> MSM8916_S3_P1_SHIFT; in calibrate_8916()
263 p1[4] = (qfprom_cdata[1] & MSM8916_S4_P1_MASK) >> MSM8916_S4_P1_SHIFT; in calibrate_8916()
265 p1[i] = (((base0) + p1[i]) << 3); in calibrate_8916()
269 p1[i] = 500; in calibrate_8916()
275 compute_intercept_slope(priv, p1, p2, mode); in calibrate_8916()
285 u32 p1[10], p2[10]; in calibrate_8939() local
[all …]
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| D | tsens-v1.c | 143 u32 p1[10], p2[10]; in calibrate_v1() local
179 p1[0] = (qfprom_cdata[0] & S0_P1_MASK) >> S0_P1_SHIFT; in calibrate_v1()
180 p1[1] = (qfprom_cdata[0] & S1_P1_MASK) >> S1_P1_SHIFT; in calibrate_v1()
181 p1[2] = (qfprom_cdata[0] & S2_P1_MASK) >> S2_P1_SHIFT; in calibrate_v1()
182 p1[3] = (qfprom_cdata[1] & S3_P1_MASK) >> S3_P1_SHIFT; in calibrate_v1()
183 p1[4] = (qfprom_cdata[1] & S4_P1_MASK) >> S4_P1_SHIFT; in calibrate_v1()
184 p1[5] = (qfprom_cdata[2] & S5_P1_MASK) >> S5_P1_SHIFT; in calibrate_v1()
185 p1[6] = (qfprom_cdata[2] & S6_P1_MASK) >> S6_P1_SHIFT; in calibrate_v1()
186 p1[7] = (qfprom_cdata[2] & S7_P1_MASK) >> S7_P1_SHIFT; in calibrate_v1()
187 p1[8] = (qfprom_cdata[3] & S8_P1_MASK) >> S8_P1_SHIFT; in calibrate_v1()
[all …]
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| /drivers/gpu/drm/omapdrm/ |
| D | tcm.h | 53 struct tcm_pt p1; member
228 slice->p0.y != slice->p1.y && in tcm_slice()
229 (slice->p0.x || (slice->p1.x != slice->tcm->width - 1))) { in tcm_slice()
231 slice->p1.x = slice->tcm->width - 1; in tcm_slice()
232 slice->p1.y = (slice->p0.x) ? slice->p0.y : slice->p1.y - 1; in tcm_slice()
235 parent->p0.y = slice->p1.y + 1; in tcm_slice()
247 area->p1.x < area->tcm->width && in tcm_area_is_valid()
248 area->p1.y < area->tcm->height && in tcm_area_is_valid()
249 area->p0.y <= area->p1.y && in tcm_area_is_valid()
254 area->p1.x + area->p1.y * area->tcm->width) || in tcm_area_is_valid()
[all …]
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| D | tcm-sita.c | 173 area->p1.x = (pos + num_slots - 1) % tcm->width; in sita_reserve_1d()
174 area->p1.y = (pos + num_slots - 1) / tcm->width; in sita_reserve_1d()
195 area->p1.x = area->p0.x + w - 1; in sita_reserve_2d()
196 area->p1.y = area->p0.y + h - 1; in sita_reserve_2d()
215 w = area->p1.x - area->p0.x + 1; in sita_free()
216 h = area->p1.y - area->p0.y + 1; in sita_free()
218 w = area->p1.x + area->p1.y * tcm->width - pos + 1; in sita_free()
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| D | omap_dmm_tiler.c | 495 .x1 = slice.p1.x, .y1 = slice.p1.y, in fill()
960 .p1.x = omap_dmm->container_width - 1, in omap_dmm_probe()
961 .p1.y = omap_dmm->container_height - 1, in omap_dmm_probe()
1013 for (y = a->p0.y / ydiv; y <= a->p1.y / ydiv; y++) in fill_map()
1014 for (x = a->p0.x / xdiv; x <= a->p1.x / xdiv; x++) in fill_map()
1050 if (a->p0.y + 1 < a->p1.y) { in map_1d_info()
1051 text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv, 0, in map_1d_info()
1053 } else if (a->p0.y < a->p1.y) { in map_1d_info()
1057 else if (strlen(nice) < map_width(xdiv, 0, a->p1.x)) in map_1d_info()
1058 text_map(map, xdiv, nice, a->p1.y / ydiv, in map_1d_info()
[all …]
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| /drivers/tty/vt/ |
| D | consolemap.c | 227 u16 **p1, *p2; in set_inverse_trans_unicode() local
241 p1 = p->uni_pgdir[i]; in set_inverse_trans_unicode()
242 if (!p1) in set_inverse_trans_unicode()
245 p2 = p1[j]; in set_inverse_trans_unicode()
398 u16 **p1; in con_release_unimap() local
403 p1 = p->uni_pgdir[i]; in con_release_unimap()
404 if (p1 != NULL) { in con_release_unimap()
406 kfree(p1[j]); in con_release_unimap()
407 kfree(p1); in con_release_unimap()
446 u16 **p1, **q1; in con_unify_unimap() local
[all …]
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| D | conmakehash.c | 84 char *p, *p1; in main() local
139 fp0 = strtol(p, &p1, 0); in main()
140 if (p1 == p) in main()
145 p = p1; in main()
152 fp1 = strtol(p, &p1, 0); in main()
153 if (p1 == p) in main()
158 p = p1; in main()
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| /drivers/media/i2c/ |
| D | aptina-pll.c | 24 unsigned int p1; in aptina_pll_calculate() local
133 for (p1 = p1_max & ~1; p1 >= p1_min; p1 -= 2) { in aptina_pll_calculate()
134 unsigned int mf_inc = p1 / gcd(div, p1); in aptina_pll_calculate()
138 mf_low = roundup(max(mf_min, DIV_ROUND_UP(pll->ext_clock * p1, in aptina_pll_calculate()
140 mf_high = min(mf_max, pll->ext_clock * p1 / in aptina_pll_calculate()
146 pll->n = div * mf_low / p1; in aptina_pll_calculate()
148 pll->p1 = p1; in aptina_pll_calculate()
149 dev_dbg(dev, "PLL: N %u M %u P1 %u\n", pll->n, pll->m, pll->p1); in aptina_pll_calculate()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/ |
| D | i2c_.fuc | 102 bclr $flags $p1
106 bset $flags $p1
111 bclr $flags $p1
115 bset $flags $p1
166 bra $p1 #i2c_raise_scl_done
175 bra not $p1 #i2c_start_rep
177 bra not $p1 #i2c_start_rep
183 bra not $p1 #i2c_start_out
210 bra not $p1 #i2c_bitw_out
225 bra not $p1 #i2c_bitr_done
[all …]
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| /drivers/gpu/drm/i915/display/ |
| D | intel_dpll.c | 19 } dot, vco, n, m, m1, m2, p, p1; member
34 .p1 = { .min = 2, .max = 33 },
47 .p1 = { .min = 2, .max = 33 },
60 .p1 = { .min = 1, .max = 6 },
73 .p1 = { .min = 1, .max = 8 },
86 .p1 = { .min = 1, .max = 8 },
100 .p1 = { .min = 1, .max = 3},
115 .p1 = { .min = 1, .max = 8},
128 .p1 = { .min = 2, .max = 8 },
142 .p1 = { .min = 2, .max = 6 },
[all …]
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| /drivers/gpu/drm/gma500/ |
| D | oaktrail_crtc.c | 48 .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1},
54 .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_0},
60 .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1},
67 .p1 = {.min = 1, .max = 2},
113 clock->dot = (refclk * clock->m) / (14 * clock->p1); in mrst_lvds_clock()
120 clock->p1, clock->p2); in mrst_print_pll()
137 for (clock.p1 = limit->p1.min; in mrst_sdvo_find_best_pll()
138 clock.p1 <= limit->p1.max; clock.p1++) { in mrst_sdvo_find_best_pll()
140 clock.p = clock.p1 * limit->p2.p2_slow; in mrst_sdvo_find_best_pll()
192 for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max; in mrst_lvds_find_best_pll()
[all …]
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| D | cdv_intel_display.c | 43 .p1 = {.min = 2, .max = 10},
55 .p1 = {.min = 2, .max = 10},
70 .p1 = {.min = 1, .max = 9},
82 .p1 = {.min = 1, .max = 10},
94 .p1 = {.min = 1, .max = 9},
106 .p1 = {.min = 1, .max = 10},
311 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER); in cdv_dpll_set_clock_cdv()
395 clock->p = clock->p1 * clock->p2; in cdv_intel_clock()
413 clock.p1 = 2; in cdv_intel_find_dp_pll()
419 clock.p1 = 1; in cdv_intel_find_dp_pll()
[all …]
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| D | psb_intel_display.c | 33 .p1 = {.min = 1, .max = 8},
45 .p1 = {.min = 1, .max = 8},
69 clock->p = clock->p1 * clock->p2; in psb_intel_clock()
167 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
335 clock.p1 = in psb_intel_crtc_clock_get()
349 clock.p1 = 2; in psb_intel_crtc_clock_get()
351 clock.p1 = in psb_intel_crtc_clock_get()
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| D | gma_display.c | 723 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) in gma_pll_is_valid()
789 for (clock.p1 = limit->p1.min; in gma_find_best_pll()
790 clock.p1 <= limit->p1.max; in gma_find_best_pll()
791 clock.p1++) { in gma_find_best_pll()
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| /drivers/video/fbdev/intelfb/ |
| D | intelfbhw.c | 666 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, in calc_vclock() argument
677 p = ((p1 + 2) * (1 << (p2 + 1))); in calc_vclock()
679 p = ((p1) * (p2 ? 5 : 10)); in calc_vclock()
687 int p1, p2; in intelfbhw_get_p1p2() local
691 p1 = 1; in intelfbhw_get_p1p2()
693 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff; in intelfbhw_get_p1p2()
695 p1 = ffs(p1); in intelfbhw_get_p1p2()
700 p1 = 0; in intelfbhw_get_p1p2()
702 p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK; in intelfbhw_get_p1p2()
706 *o_p1 = p1; in intelfbhw_get_p1p2()
[all …]
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| /drivers/clk/ |
| D | clk-si5351.c | 36 unsigned long p1; member
138 params->p1 = buf[0]; in si5351_read_parameters()
144 params->p1 = ((buf[2] & 0x03) << 16) | (buf[3] << 8) | buf[4]; in si5351_read_parameters()
159 buf[0] = params->p1 & 0xff; in si5351_write_parameters()
167 buf[2] |= ((params->p1 & 0x30000) >> 16) & 0x03; in si5351_write_parameters()
168 buf[3] = ((params->p1 & 0x0ff00) >> 8) & 0xff; in si5351_write_parameters()
169 buf[4] = params->p1 & 0xff; in si5351_write_parameters()
430 rate = hwdata->params.p1 * hwdata->params.p3; in si5351_pll_recalc_rate()
439 hwdata->params.p1, hwdata->params.p2, hwdata->params.p3, in si5351_pll_recalc_rate()
482 hwdata->params.p1 = 128 * a; in si5351_pll_round_rate()
[all …]
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| /drivers/misc/cxl/ |
| D | hcalls.c | 206 u64 p1, u64 p2, u64 p3, u64 p4, u64 *out) in cxl_h_control_function() argument
211 CXL_H9_WAIT_UNTIL_DONE(rc, retbuf, H_CONTROL_CA_FUNCTION, unit_address, op, p1, p2, p3, p4); in cxl_h_control_function()
213 unit_address, OP_STR_AFU(op), p1, p2, p3, p4, retbuf[0], rc); in cxl_h_control_function()
214 trace_cxl_hcall_control_function(unit_address, OP_STR_AFU(op), p1, p2, p3, p4, retbuf[0], rc); in cxl_h_control_function()
479 u64 p1, u64 p2, u64 p3, u64 p4, u64 *out) in cxl_h_control_facility() argument
484 CXL_H9_WAIT_UNTIL_DONE(rc, retbuf, H_CONTROL_CA_FACILITY, unit_address, op, p1, p2, p3, p4); in cxl_h_control_facility()
486 unit_address, OP_STR_CONTROL_ADAPTER(op), p1, p2, p3, p4, retbuf[0], rc); in cxl_h_control_facility()
487 …trace_cxl_hcall_control_facility(unit_address, OP_STR_CONTROL_ADAPTER(op), p1, p2, p3, p4, retbuf[… in cxl_h_control_facility()
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| D | trace.h | 517 TP_PROTO(u64 unit_address, char *fct, u64 p1, u64 p2, u64 p3,
520 TP_ARGS(unit_address, fct, p1, p2, p3, p4, r4, rc),
525 __field(u64, p1)
536 __entry->p1 = p1;
547 __entry->p1,
598 TP_PROTO(u64 unit_address, char *fct, u64 p1, u64 p2, u64 p3,
600 TP_ARGS(unit_address, fct, p1, p2, p3, p4, r4, rc)
646 TP_PROTO(u64 unit_address, char *fct, u64 p1, u64 p2, u64 p3,
648 TP_ARGS(unit_address, fct, p1, p2, p3, p4, r4, rc)
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| /drivers/scsi/ |
| D | dpt_i2o.c | 785 struct adpt_i2o_post_wait_data *p1, *old; in adpt_i2o_sys_shutdown() local
803 for(p1 = adpt_post_wait_queue; p1;) { in adpt_i2o_sys_shutdown()
804 old = p1; in adpt_i2o_sys_shutdown()
805 p1 = p1->next; in adpt_i2o_sys_shutdown()
987 adpt_hba* p1; in adpt_i2o_delete_hba() local
1002 for( p1 = hba_chain; p1; p2 = p1,p1=p1->next){ in adpt_i2o_delete_hba()
1003 if(p1 == pHba) { in adpt_i2o_delete_hba()
1005 p2->next = p1->next; in adpt_i2o_delete_hba()
1007 hba_chain = p1->next; in adpt_i2o_delete_hba()
1106 struct adpt_i2o_post_wait_data *p1, *p2; in adpt_i2o_post_wait() local
[all …]
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| /drivers/gpu/drm/nouveau/dispnv04/ |
| D | arb.c | 58 int found, mclk_extra, mclk_loop, cbs, m1, p1; in nv04_calc_arb() local
93 p1 = m1 * pclk_freq / mclk_freq; in nv04_calc_arb()
94 p1 = p1 * bpp / 8; in nv04_calc_arb()
95 if ((p1 < m1 && m1 > 0) || clwm > 519) { in nv04_calc_arb()
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| /drivers/cpufreq/ |
| D | brcmstb-avs-cpufreq.c | 170 unsigned int p1; member
341 static void brcm_avs_parse_p1(u32 p1, unsigned int *mdiv_p0, unsigned int *pdiv, in brcm_avs_parse_p1() argument
344 *mdiv_p0 = (p1 >> MDIV_P0_SHIFT) & MDIV_P0_MASK; in brcm_avs_parse_p1()
345 *pdiv = (p1 >> PDIV_SHIFT) & PDIV_MASK; in brcm_avs_parse_p1()
346 *ndiv = (p1 >> NDIV_INT_SHIFT) & NDIV_INT_MASK; in brcm_avs_parse_p1()
369 pmap->p1 = args[1]; in brcm_avs_get_pmap()
381 args[1] = pmap->p1; in brcm_avs_set_pmap()
689 brcm_avs_parse_p1(pmap.p1, &mdiv_p0, &pdiv, &ndiv); in show_brcm_avs_pmap()
693 pmap.p1, pmap.p2, ndiv, pdiv, mdiv_p0, mdiv_p1, mdiv_p2, in show_brcm_avs_pmap()
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| /drivers/auxdisplay/ |
| D | ht16k33.c | 133 uint8_t *p1, *p2; in ht16k33_fb_update() local
136 p1 = fbdev->cache; in ht16k33_fb_update()
141 if (*(p1++) - *(p2++)) in ht16k33_fb_update()
151 p1 = fbdev->cache + HT16K33_FB_SIZE - 1; in ht16k33_fb_update()
156 if (*(p1--) - *(p2--)) in ht16k33_fb_update()
161 p1 = fbdev->cache + first; in ht16k33_fb_update()
164 memcpy(p1, p2, len); in ht16k33_fb_update()
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| /drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/ |
| D | gpc.fuc | 300 bra $p1 #wait
305 // fetch $flags and mask off $p1/$p2
310 // set $p1/$p2 according to transfer type
398 // $p1 clear on save, set on load
409 bra not $p1 #ctx_xfer_not_load
417 xbit $r2 $flags $p1 // SAVE/LOAD
424 xbit $r15 $flags $p1 // SAVE/LOAD
430 xbit $r10 $flags $p1 // direction
442 xbit $r10 $flags $p1 // direction
458 xbit $r10 $flags $p1 // direction
[all …]
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| D | hub.fuc | 228 bra $p1 #wait
244 bclr $flags $p1
250 bset $flags $p1
257 bclr $flags $p1
266 bset $flags $p1
290 bclr $flags $p1
597 // $p1 clear on save, set on load
611 bra not $p1 #ctx_xfer_pre
619 bra not $p1 #ctx_xfer_exec
638 xbit $r15 $flags $p1
[all …]
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| /drivers/gpu/drm/radeon/ |
| D | radeon_legacy_tv.c | 431 u16 p1, p2, h_inc; in radeon_legacy_tv_init_restarts() local
457 p1 = hor_timing_NTSC[H_TABLE_POS1]; in radeon_legacy_tv_init_restarts()
460 p1 = hor_timing_PAL[H_TABLE_POS1]; in radeon_legacy_tv_init_restarts()
464 p1 = (u16)((int)p1 + h_offset); in radeon_legacy_tv_init_restarts()
467 h_changed = (p1 != tv_dac->tv.h_code_timing[H_TABLE_POS1] || in radeon_legacy_tv_init_restarts()
470 tv_dac->tv.h_code_timing[H_TABLE_POS1] = p1; in radeon_legacy_tv_init_restarts()
493 const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart); in radeon_legacy_tv_init_restarts()
|