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Searched refs:tcon (Results 1 – 22 of 22) sorted by relevance

/drivers/gpu/drm/sun4i/
Dsun4i_tcon.c83 static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel, in sun4i_tcon_channel_set_status() argument
90 WARN_ON(!tcon->quirks->has_channel_0); in sun4i_tcon_channel_set_status()
91 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon_channel_set_status()
94 clk = tcon->dclk; in sun4i_tcon_channel_set_status()
97 WARN_ON(!tcon->quirks->has_channel_1); in sun4i_tcon_channel_set_status()
98 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon_channel_set_status()
101 clk = tcon->sclk1; in sun4i_tcon_channel_set_status()
117 static void sun4i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon, in sun4i_tcon_setup_lvds_phy() argument
120 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun4i_tcon_setup_lvds_phy()
129 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG, in sun4i_tcon_setup_lvds_phy()
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Dsun4i_dotclock.c18 struct sun4i_tcon *tcon; member
74 struct sun4i_tcon *tcon = dclk->tcon; in sun4i_dclk_round_rate() local
79 for (i = tcon->dclk_min_div; i <= tcon->dclk_max_div; i++) { in sun4i_dclk_round_rate()
165 int sun4i_dclk_create(struct device *dev, struct sun4i_tcon *tcon) in sun4i_dclk_create() argument
172 parent_name = __clk_get_name(tcon->sclk0); in sun4i_dclk_create()
182 dclk->tcon = tcon; in sun4i_dclk_create()
190 dclk->regmap = tcon->regs; in sun4i_dclk_create()
193 tcon->dclk = clk_register(dev, &dclk->hw); in sun4i_dclk_create()
194 if (IS_ERR(tcon->dclk)) in sun4i_dclk_create()
195 return PTR_ERR(tcon->dclk); in sun4i_dclk_create()
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Dsun4i_rgb.c27 struct sun4i_tcon *tcon; member
66 struct sun4i_tcon *tcon = rgb->tcon; in sun4i_rgb_mode_valid() local
121 tcon->dclk_min_div = 6; in sun4i_rgb_mode_valid()
122 tcon->dclk_max_div = 127; in sun4i_rgb_mode_valid()
123 rounded_rate = clk_round_rate(tcon->dclk, rate); in sun4i_rgb_mode_valid()
189 int sun4i_rgb_init(struct drm_device *drm, struct sun4i_tcon *tcon) in sun4i_rgb_init() argument
198 rgb->tcon = tcon; in sun4i_rgb_init()
201 ret = drm_of_find_panel_or_bridge(tcon->dev->of_node, 1, 0, in sun4i_rgb_init()
218 rgb->encoder.possible_crtcs = drm_crtc_mask(&tcon->crtc->crtc); in sun4i_rgb_init()
DMakefile21 sun4i-tcon-y += sun4i_crtc.o
22 sun4i-tcon-y += sun4i_dotclock.o
23 sun4i-tcon-y += sun4i_lvds.o
24 sun4i-tcon-y += sun4i_tcon.o
25 sun4i-tcon-y += sun4i_rgb.o
28 obj-$(CONFIG_DRM_SUN4I) += sun4i-tcon.o
Dsun4i_crtc.c118 sun4i_tcon_set_status(scrtc->tcon, encoder, false); in sun4i_crtc_atomic_disable()
137 sun4i_tcon_set_status(scrtc->tcon, encoder, true); in sun4i_crtc_atomic_enable()
148 sun4i_tcon_mode_set(scrtc->tcon, encoder, mode); in sun4i_crtc_mode_set_nofb()
166 sun4i_tcon_enable_vblank(scrtc->tcon, true); in sun4i_crtc_enable_vblank()
177 sun4i_tcon_enable_vblank(scrtc->tcon, false); in sun4i_crtc_disable_vblank()
193 struct sun4i_tcon *tcon) in sun4i_crtc_init() argument
204 scrtc->tcon = tcon; in sun4i_crtc_init()
242 scrtc->crtc.port = of_graph_get_port_by_id(scrtc->tcon->dev->of_node, in sun4i_crtc_init()
Dsun8i_tcon_top.c28 int sun8i_tcon_top_set_hdmi_src(struct device *dev, int tcon) in sun8i_tcon_top_set_hdmi_src() argument
39 if (tcon < 2 || tcon > 3) { in sun8i_tcon_top_set_hdmi_src()
48 val |= FIELD_PREP(TCON_TOP_HDMI_SRC_MSK, tcon - 1); in sun8i_tcon_top_set_hdmi_src()
57 int sun8i_tcon_top_de_config(struct device *dev, int mixer, int tcon) in sun8i_tcon_top_de_config() argument
73 if (tcon > 3) { in sun8i_tcon_top_de_config()
83 reg |= FIELD_PREP(TCON_TOP_PORT_DE0_MSK, tcon); in sun8i_tcon_top_de_config()
86 reg |= FIELD_PREP(TCON_TOP_PORT_DE1_MSK, tcon); in sun8i_tcon_top_de_config()
Dsun4i_dotclock.h14 int sun4i_dclk_create(struct device *dev, struct sun4i_tcon *tcon);
15 int sun4i_dclk_free(struct sun4i_tcon *tcon);
Dsun4i_lvds.c97 int sun4i_lvds_init(struct drm_device *drm, struct sun4i_tcon *tcon) in sun4i_lvds_init() argument
109 ret = drm_of_find_panel_or_bridge(tcon->dev->of_node, 1, 0, in sun4i_lvds_init()
126 lvds->encoder.possible_crtcs = drm_crtc_mask(&tcon->crtc->crtc); in sun4i_lvds_init()
Dsun4i_crtc.h17 struct sun4i_tcon *tcon; member
27 struct sun4i_tcon *tcon);
Dsun8i_tcon_top.h41 int sun8i_tcon_top_set_hdmi_src(struct device *dev, int tcon);
42 int sun8i_tcon_top_de_config(struct device *dev, int mixer, int tcon);
Dsun4i_tcon.h250 void (*setup_lvds_phy)(struct sun4i_tcon *tcon,
293 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable);
294 void sun4i_tcon_mode_set(struct sun4i_tcon *tcon,
Dsun4i_lvds.h10 int sun4i_lvds_init(struct drm_device *drm, struct sun4i_tcon *tcon);
Dsun4i_rgb.h12 int sun4i_rgb_init(struct drm_device *drm, struct sun4i_tcon *tcon);
/drivers/gpu/drm/fsl-dcu/
Dfsl_tcon.c19 void fsl_tcon_bypass_disable(struct fsl_tcon *tcon) in fsl_tcon_bypass_disable() argument
21 regmap_update_bits(tcon->regs, FSL_TCON_CTRL1, in fsl_tcon_bypass_disable()
25 void fsl_tcon_bypass_enable(struct fsl_tcon *tcon) in fsl_tcon_bypass_enable() argument
27 regmap_update_bits(tcon->regs, FSL_TCON_CTRL1, in fsl_tcon_bypass_enable()
41 struct fsl_tcon *tcon, in fsl_tcon_init_regmap() argument
54 tcon->regs = devm_regmap_init_mmio(dev, regs, in fsl_tcon_init_regmap()
56 return PTR_ERR_OR_ZERO(tcon->regs); in fsl_tcon_init_regmap()
61 struct fsl_tcon *tcon; in fsl_tcon_init() local
70 tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL); in fsl_tcon_init()
71 if (!tcon) in fsl_tcon_init()
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Dfsl_tcon.h24 void fsl_tcon_free(struct fsl_tcon *tcon);
26 void fsl_tcon_bypass_disable(struct fsl_tcon *tcon);
27 void fsl_tcon_bypass_enable(struct fsl_tcon *tcon);
Dfsl_dcu_drm_rgb.c30 if (fsl_dev->tcon) in fsl_dcu_drm_encoder_create()
31 fsl_tcon_bypass_enable(fsl_dev->tcon); in fsl_dcu_drm_encoder_create()
Dfsl_dcu_drm_drv.c203 if (fsl_dev->tcon) in fsl_dcu_drm_pm_resume()
204 fsl_tcon_bypass_enable(fsl_dev->tcon); in fsl_dcu_drm_pm_resume()
318 fsl_dev->tcon = fsl_tcon_init(dev); in fsl_dcu_drm_probe()
Dfsl_dcu_drm_drv.h186 struct fsl_tcon *tcon; member
/drivers/pwm/
Dpwm-samsung.c245 u32 tcon; in pwm_samsung_enable() local
249 tcon = readl(our_chip->base + REG_TCON); in pwm_samsung_enable()
251 tcon &= ~TCON_START(tcon_chan); in pwm_samsung_enable()
252 tcon |= TCON_MANUALUPDATE(tcon_chan); in pwm_samsung_enable()
253 writel(tcon, our_chip->base + REG_TCON); in pwm_samsung_enable()
255 tcon &= ~TCON_MANUALUPDATE(tcon_chan); in pwm_samsung_enable()
256 tcon |= TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan); in pwm_samsung_enable()
257 writel(tcon, our_chip->base + REG_TCON); in pwm_samsung_enable()
271 u32 tcon; in pwm_samsung_disable() local
275 tcon = readl(our_chip->base + REG_TCON); in pwm_samsung_disable()
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/drivers/clocksource/
Dsamsung_pwm_timer.c121 unsigned long tcon; in samsung_time_stop() local
129 tcon = readl_relaxed(pwm.base + REG_TCON); in samsung_time_stop()
130 tcon &= ~TCON_START(channel); in samsung_time_stop()
131 writel_relaxed(tcon, pwm.base + REG_TCON); in samsung_time_stop()
138 unsigned long tcon; in samsung_time_setup() local
147 tcon = readl_relaxed(pwm.base + REG_TCON); in samsung_time_setup()
149 tcon &= ~(TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan)); in samsung_time_setup()
150 tcon |= TCON_MANUALUPDATE(tcon_chan); in samsung_time_setup()
154 writel_relaxed(tcon, pwm.base + REG_TCON); in samsung_time_setup()
161 unsigned long tcon; in samsung_time_start() local
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Dexynos_mct.c261 unsigned int tcon; in exynos4_mct_comp0_stop() local
263 tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); in exynos4_mct_comp0_stop()
264 tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC); in exynos4_mct_comp0_stop()
266 exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON); in exynos4_mct_comp0_stop()
272 unsigned int tcon; in exynos4_mct_comp0_start() local
275 tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); in exynos4_mct_comp0_start()
278 tcon |= MCT_G_TCON_COMP0_AUTO_INC; in exynos4_mct_comp0_start()
288 tcon |= MCT_G_TCON_COMP0_ENABLE; in exynos4_mct_comp0_start()
289 exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON); in exynos4_mct_comp0_start()
/drivers/clk/sunxi/
DMakefile19 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sun4i-tcon-ch1.o