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Searched refs:v7 (Results 1 – 13 of 13) sorted by relevance

/drivers/input/rmi4/
Drmi_f34v7.c28 f34->fn->fd.data_base_addr + f34->v7.off.flash_status, in rmi_f34v7_read_flash_status()
37 f34->v7.in_bl_mode = status >> 7; in rmi_f34v7_read_flash_status()
38 f34->v7.flash_status = status & 0x1f; in rmi_f34v7_read_flash_status()
40 if (f34->v7.flash_status != 0x00) { in rmi_f34v7_read_flash_status()
42 __func__, f34->v7.flash_status, f34->v7.command); in rmi_f34v7_read_flash_status()
46 f34->fn->fd.data_base_addr + f34->v7.off.flash_cmd, in rmi_f34v7_read_flash_status()
55 f34->v7.command = command; in rmi_f34v7_read_flash_status()
66 if (!wait_for_completion_timeout(&f34->v7.cmd_done, timeout)) { in rmi_f34v7_wait_for_idle()
125 base + f34->v7.off.partition_id, in rmi_f34v7_write_command_single_transaction()
174 f34->v7.command = command; in rmi_f34v7_write_command()
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Drmi_f34.c118 f34->v7.off.flash_status, in rmi_f34_attention()
124 complete(&f34->v7.cmd_done); in rmi_f34_attention()
Drmi_f34.h304 struct f34v7_data v7; member
/drivers/gpu/drm/amd/display/dc/inc/
Dreg_helper.h105 f5, v5, f6, v6, f7, v7) \ argument
113 FN(reg, f7), v7)
116 f5, v5, f6, v6, f7, v7, f8, v8) \ argument
124 FN(reg, f7), v7,\
128 v5, f6, v6, f7, v7, f8, v8, f9, v9) \ argument
136 FN(reg, f7), v7, \
141 v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \ argument
149 FN(reg, f7), v7, \
195 #define REG_GET_7(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ argument
203 FN(reg_name, f7), v7)
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/drivers/char/mwave/
Dmwavedd.h109 #define PRINTK_8(f,s,v1,v2,v3,v4,v5,v6,v7) \ argument
111 printk(s,v1,v2,v3,v4,v5,v6,v7); \
122 #define PRINTK_8(f,s,v1,v2,v3,v4,v5,v6,v7) argument
/drivers/gpu/drm/amd/amdgpu/
Datombios_crtc.c465 PIXEL_CLOCK_PARAMETERS_V7 v7; member
707 args.v7.ulPixelClock = cpu_to_le32(clock * 10); /* 100 hz units */ in amdgpu_atombios_crtc_program_pll()
708 args.v7.ucMiscInfo = 0; in amdgpu_atombios_crtc_program_pll()
711 args.v7.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN; in amdgpu_atombios_crtc_program_pll()
712 args.v7.ucCRTC = crtc_id; in amdgpu_atombios_crtc_program_pll()
717 args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS; in amdgpu_atombios_crtc_program_pll()
720 args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4; in amdgpu_atombios_crtc_program_pll()
723 args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2; in amdgpu_atombios_crtc_program_pll()
726 args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1; in amdgpu_atombios_crtc_program_pll()
730 args.v7.ucTransmitterID = encoder_id; in amdgpu_atombios_crtc_program_pll()
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/drivers/net/wireless/intel/iwlwifi/mvm/
Dscan.c111 return (void *)&cmd->v7.data; in iwl_mvm_get_scan_req_umac_data()
128 return &cmd->v7.channel; in iwl_mvm_get_scan_req_umac_channel()
1302 cmd->v7.adwell_default_n_aps_social = in iwl_mvm_scan_umac_dwell()
1304 cmd->v7.adwell_default_n_aps = in iwl_mvm_scan_umac_dwell()
1313 cmd->v7.adwell_max_budget = in iwl_mvm_scan_umac_dwell()
1316 cmd->v7.adwell_max_budget = in iwl_mvm_scan_umac_dwell()
1319 cmd->v7.adwell_max_budget = in iwl_mvm_scan_umac_dwell()
1322 cmd->v7.scan_priority = cpu_to_le32(IWL_SCAN_PRIORITY_EXT_6); in iwl_mvm_scan_umac_dwell()
1323 cmd->v7.max_out_time[SCAN_LB_LMAC_IDX] = in iwl_mvm_scan_umac_dwell()
1325 cmd->v7.suspend_time[SCAN_LB_LMAC_IDX] = in iwl_mvm_scan_umac_dwell()
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Dd3.c1853 iwl_mvm_parse_wowlan_status_common(v7) in iwl_mvm_parse_wowlan_status_common() argument
1928 struct iwl_wowlan_status_v7 *v7 = (void *)cmd.resp_pkt->data; in iwl_mvm_parse_wowlan_status_common() local
1936 status->gtk[0] = v7->gtk[0]; in iwl_mvm_parse_wowlan_status_common()
1937 status->igtk[0] = v7->igtk[0]; in iwl_mvm_parse_wowlan_status_common()
/drivers/cpuidle/
DMakefile14 obj-$(CONFIG_ARM_MVEBU_V7_CPUIDLE) += cpuidle-mvebu-v7.o
DKconfig.arm95 bool "CPU Idle Driver for mvebu v7 family processors"
/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
Dfwil_types.h642 } v7; member
/drivers/net/wireless/intel/iwlwifi/fw/api/
Dscan.h819 } v7; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_7 */ member
/drivers/video/fbdev/sis/
Dsis_main.c4351 u8 reg, v1, v2, v3, v4, v5, v6, v7, v8; in sisfb_post_sis300() local
4403 v5 = 0x06; v6 = 0x00; v7 = 0x00; v8 = 0x00; in sisfb_post_sis300()
4412 v7 = bios[memtype + 48]; in sisfb_post_sis300()
4423 SiS_SetReg(SISSR, 0x1b, v7); in sisfb_post_sis300()