1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ahci.c - AHCI SATA support
4 *
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
13 *
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/dmi.h>
28 #include <linux/gfp.h>
29 #include <linux/msi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_cmnd.h>
32 #include <linux/libata.h>
33 #include <linux/ahci-remap.h>
34 #include <linux/io-64-nonatomic-lo-hi.h>
35 #include "ahci.h"
36
37 #define DRV_NAME "ahci"
38 #define DRV_VERSION "3.0"
39
40 enum {
41 AHCI_PCI_BAR_STA2X11 = 0,
42 AHCI_PCI_BAR_CAVIUM = 0,
43 AHCI_PCI_BAR_LOONGSON = 0,
44 AHCI_PCI_BAR_ENMOTUS = 2,
45 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
46 AHCI_PCI_BAR_STANDARD = 5,
47 };
48
49 enum board_ids {
50 /* board IDs by feature in alphabetical order */
51 board_ahci,
52 board_ahci_ign_iferr,
53 board_ahci_low_power,
54 board_ahci_no_debounce_delay,
55 board_ahci_nomsi,
56 board_ahci_noncq,
57 board_ahci_nosntf,
58 board_ahci_yes_fbs,
59
60 /* board IDs for specific chipsets in alphabetical order */
61 board_ahci_al,
62 board_ahci_avn,
63 board_ahci_mcp65,
64 board_ahci_mcp77,
65 board_ahci_mcp89,
66 board_ahci_mv,
67 board_ahci_sb600,
68 board_ahci_sb700, /* for SB700 and SB800 */
69 board_ahci_vt8251,
70
71 /*
72 * board IDs for Intel chipsets that support more than 6 ports
73 * *and* end up needing the PCS quirk.
74 */
75 board_ahci_pcs7,
76
77 /* aliases */
78 board_ahci_mcp_linux = board_ahci_mcp65,
79 board_ahci_mcp67 = board_ahci_mcp65,
80 board_ahci_mcp73 = board_ahci_mcp65,
81 board_ahci_mcp79 = board_ahci_mcp77,
82 };
83
84 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
85 static void ahci_remove_one(struct pci_dev *dev);
86 static void ahci_shutdown_one(struct pci_dev *dev);
87 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv);
88 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
91 unsigned long deadline);
92 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
93 static bool is_mcp89_apple(struct pci_dev *pdev);
94 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
95 unsigned long deadline);
96 #ifdef CONFIG_PM
97 static int ahci_pci_device_runtime_suspend(struct device *dev);
98 static int ahci_pci_device_runtime_resume(struct device *dev);
99 #ifdef CONFIG_PM_SLEEP
100 static int ahci_pci_device_suspend(struct device *dev);
101 static int ahci_pci_device_resume(struct device *dev);
102 #endif
103 #endif /* CONFIG_PM */
104
105 static struct scsi_host_template ahci_sht = {
106 AHCI_SHT("ahci"),
107 };
108
109 static struct ata_port_operations ahci_vt8251_ops = {
110 .inherits = &ahci_ops,
111 .hardreset = ahci_vt8251_hardreset,
112 };
113
114 static struct ata_port_operations ahci_p5wdh_ops = {
115 .inherits = &ahci_ops,
116 .hardreset = ahci_p5wdh_hardreset,
117 };
118
119 static struct ata_port_operations ahci_avn_ops = {
120 .inherits = &ahci_ops,
121 .hardreset = ahci_avn_hardreset,
122 };
123
124 static const struct ata_port_info ahci_port_info[] = {
125 /* by features */
126 [board_ahci] = {
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
131 },
132 [board_ahci_ign_iferr] = {
133 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
134 .flags = AHCI_FLAG_COMMON,
135 .pio_mask = ATA_PIO4,
136 .udma_mask = ATA_UDMA6,
137 .port_ops = &ahci_ops,
138 },
139 [board_ahci_low_power] = {
140 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
141 .flags = AHCI_FLAG_COMMON,
142 .pio_mask = ATA_PIO4,
143 .udma_mask = ATA_UDMA6,
144 .port_ops = &ahci_ops,
145 },
146 [board_ahci_no_debounce_delay] = {
147 .flags = AHCI_FLAG_COMMON,
148 .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY,
149 .pio_mask = ATA_PIO4,
150 .udma_mask = ATA_UDMA6,
151 .port_ops = &ahci_ops,
152 },
153 [board_ahci_nomsi] = {
154 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
155 .flags = AHCI_FLAG_COMMON,
156 .pio_mask = ATA_PIO4,
157 .udma_mask = ATA_UDMA6,
158 .port_ops = &ahci_ops,
159 },
160 [board_ahci_noncq] = {
161 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
162 .flags = AHCI_FLAG_COMMON,
163 .pio_mask = ATA_PIO4,
164 .udma_mask = ATA_UDMA6,
165 .port_ops = &ahci_ops,
166 },
167 [board_ahci_nosntf] = {
168 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
169 .flags = AHCI_FLAG_COMMON,
170 .pio_mask = ATA_PIO4,
171 .udma_mask = ATA_UDMA6,
172 .port_ops = &ahci_ops,
173 },
174 [board_ahci_yes_fbs] = {
175 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
176 .flags = AHCI_FLAG_COMMON,
177 .pio_mask = ATA_PIO4,
178 .udma_mask = ATA_UDMA6,
179 .port_ops = &ahci_ops,
180 },
181 /* by chipsets */
182 [board_ahci_al] = {
183 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
184 .flags = AHCI_FLAG_COMMON,
185 .pio_mask = ATA_PIO4,
186 .udma_mask = ATA_UDMA6,
187 .port_ops = &ahci_ops,
188 },
189 [board_ahci_avn] = {
190 .flags = AHCI_FLAG_COMMON,
191 .pio_mask = ATA_PIO4,
192 .udma_mask = ATA_UDMA6,
193 .port_ops = &ahci_avn_ops,
194 },
195 [board_ahci_mcp65] = {
196 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
197 AHCI_HFLAG_YES_NCQ),
198 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
199 .pio_mask = ATA_PIO4,
200 .udma_mask = ATA_UDMA6,
201 .port_ops = &ahci_ops,
202 },
203 [board_ahci_mcp77] = {
204 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
205 .flags = AHCI_FLAG_COMMON,
206 .pio_mask = ATA_PIO4,
207 .udma_mask = ATA_UDMA6,
208 .port_ops = &ahci_ops,
209 },
210 [board_ahci_mcp89] = {
211 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
212 .flags = AHCI_FLAG_COMMON,
213 .pio_mask = ATA_PIO4,
214 .udma_mask = ATA_UDMA6,
215 .port_ops = &ahci_ops,
216 },
217 [board_ahci_mv] = {
218 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
219 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
220 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
221 .pio_mask = ATA_PIO4,
222 .udma_mask = ATA_UDMA6,
223 .port_ops = &ahci_ops,
224 },
225 [board_ahci_sb600] = {
226 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
227 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
228 AHCI_HFLAG_32BIT_ONLY),
229 .flags = AHCI_FLAG_COMMON,
230 .pio_mask = ATA_PIO4,
231 .udma_mask = ATA_UDMA6,
232 .port_ops = &ahci_pmp_retry_srst_ops,
233 },
234 [board_ahci_sb700] = { /* for SB700 and SB800 */
235 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
236 .flags = AHCI_FLAG_COMMON,
237 .pio_mask = ATA_PIO4,
238 .udma_mask = ATA_UDMA6,
239 .port_ops = &ahci_pmp_retry_srst_ops,
240 },
241 [board_ahci_vt8251] = {
242 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
243 .flags = AHCI_FLAG_COMMON,
244 .pio_mask = ATA_PIO4,
245 .udma_mask = ATA_UDMA6,
246 .port_ops = &ahci_vt8251_ops,
247 },
248 [board_ahci_pcs7] = {
249 .flags = AHCI_FLAG_COMMON,
250 .pio_mask = ATA_PIO4,
251 .udma_mask = ATA_UDMA6,
252 .port_ops = &ahci_ops,
253 },
254 };
255
256 static const struct pci_device_id ahci_pci_tbl[] = {
257 /* Intel */
258 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
259 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
260 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
261 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
262 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
263 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
264 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
265 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
266 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
267 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
268 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
269 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
270 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
271 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
272 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
273 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
274 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
275 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
276 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
277 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
278 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
279 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_low_power }, /* ICH9M */
280 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_low_power }, /* ICH9M */
281 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_low_power }, /* ICH9M */
282 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_low_power }, /* ICH9M */
283 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_low_power }, /* ICH9M */
284 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
285 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_low_power }, /* ICH9M */
286 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
287 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
288 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
289 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
290 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
291 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
292 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
293 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
294 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
295 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_low_power }, /* PCH M AHCI */
296 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
297 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_low_power }, /* PCH M RAID */
298 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
299 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
300 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
301 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
302 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
303 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
304 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
305 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
306 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
307 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
309 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
310 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
311 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
312 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
313 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
314 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
315 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
316 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
317 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
318 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
319 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
320 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_low_power }, /* CPT M AHCI */
321 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
322 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_low_power }, /* CPT M RAID */
323 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
324 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
325 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
326 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
327 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
328 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
329 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
330 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
331 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_low_power }, /* Panther M AHCI */
332 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
333 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
334 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
335 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_low_power }, /* Panther M RAID */
336 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
337 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
338 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_low_power }, /* Lynx M AHCI */
339 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
340 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_low_power }, /* Lynx M RAID */
341 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
342 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_low_power }, /* Lynx M RAID */
343 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
344 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_low_power }, /* Lynx M RAID */
345 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_low_power }, /* Lynx LP AHCI */
346 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_low_power }, /* Lynx LP AHCI */
347 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_low_power }, /* Lynx LP RAID */
348 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_low_power }, /* Lynx LP RAID */
349 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_low_power }, /* Lynx LP RAID */
350 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_low_power }, /* Lynx LP RAID */
351 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_low_power }, /* Lynx LP RAID */
352 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_low_power }, /* Lynx LP RAID */
353 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_low_power }, /* Cannon Lake PCH-LP AHCI */
354 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
355 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
356 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
357 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
358 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
359 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
360 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
361 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
362 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
363 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
364 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
365 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
366 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
367 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
368 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
369 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
370 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
371 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
372 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */
373 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */
374 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */
375 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */
376 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
377 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
378 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
379 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
380 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
381 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
382 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
383 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
384 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
385 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_low_power }, /* Wildcat LP AHCI */
386 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_low_power }, /* Wildcat LP RAID */
387 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_low_power }, /* Wildcat LP RAID */
388 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_low_power }, /* Wildcat LP RAID */
389 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
390 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_low_power }, /* 9 Series M AHCI */
391 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
392 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_low_power }, /* 9 Series M RAID */
393 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
394 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_low_power }, /* 9 Series M RAID */
395 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
396 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_low_power }, /* 9 Series M RAID */
397 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_low_power }, /* Sunrise LP AHCI */
398 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_low_power }, /* Sunrise LP RAID */
399 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_low_power }, /* Sunrise LP RAID */
400 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
401 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_low_power }, /* Sunrise M AHCI */
402 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
403 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
404 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_low_power }, /* Sunrise M RAID */
405 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
406 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
407 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
408 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
409 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
410 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
411 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
412 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
413 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
414 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
415 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
416 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
417 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
418 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
419 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
420 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
421 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_low_power }, /* Bay Trail AHCI */
422 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_low_power }, /* Bay Trail AHCI */
423 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_low_power }, /* Cherry Tr. AHCI */
424 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_low_power }, /* ApolloLake AHCI */
425 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power }, /* Ice Lake LP AHCI */
426 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power }, /* Comet Lake PCH-U AHCI */
427 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */
428 /* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */
429 { PCI_VDEVICE(INTEL, 0x4b63), board_ahci_low_power }, /* Elkhart Lake AHCI */
430
431 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
432 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
433 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
434 /* JMicron 362B and 362C have an AHCI function with IDE class code */
435 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
436 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
437 /* May need to update quirk_jmicron_async_suspend() for additions */
438
439 /* ATI */
440 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
441 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
442 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
443 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
444 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
445 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
446 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
447
448 /* Amazon's Annapurna Labs support */
449 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
450 .class = PCI_CLASS_STORAGE_SATA_AHCI,
451 .class_mask = 0xffffff,
452 board_ahci_al },
453 /* AMD */
454 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
455 { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
456 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
457 { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sardine */
458 /* AMD is using RAID class only for ahci controllers */
459 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
460 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
461
462 /* Dell S140/S150 */
463 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID,
464 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
465
466 /* VIA */
467 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
468 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
469
470 /* NVIDIA */
471 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
472 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
473 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
474 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
475 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
476 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
477 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
478 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
479 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
480 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
481 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
482 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
483 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
484 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
485 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
486 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
487 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
488 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
489 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
490 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
491 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
492 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
493 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
494 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
495 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
496 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
497 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
498 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
499 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
500 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
501 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
502 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
503 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
504 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
505 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
506 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
507 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
508 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
509 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
510 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
511 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
512 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
513 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
514 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
515 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
516 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
517 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
518 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
519 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
520 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
521 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
522 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
523 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
524 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
525 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
526 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
527 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
528 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
529 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
530 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
531 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
532 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
533 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
534 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
535 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
536 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
537 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
538 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
539 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
540 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
541 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
542 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
543 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
544 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
545 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
546 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
547 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
548 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
549 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
550 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
551 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
552 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
553 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
554 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
555
556 /* SiS */
557 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
558 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
559 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
560
561 /* ST Microelectronics */
562 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
563
564 /* Marvell */
565 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
566 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
567 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
568 .class = PCI_CLASS_STORAGE_SATA_AHCI,
569 .class_mask = 0xffffff,
570 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
571 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
572 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
573 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
574 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
575 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
576 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
577 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
578 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
579 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
580 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
581 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
582 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
583 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
584 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
585 .driver_data = board_ahci_yes_fbs },
586 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
587 .driver_data = board_ahci_yes_fbs },
588 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
589 .driver_data = board_ahci_yes_fbs },
590 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
591 .driver_data = board_ahci_yes_fbs },
592 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
593 .driver_data = board_ahci_yes_fbs },
594 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
595 .driver_data = board_ahci_yes_fbs },
596
597 /* Promise */
598 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
599 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
600
601 /* Asmedia */
602 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
603 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
604 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
605 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
606 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
607 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
608
609 /*
610 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
611 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
612 */
613 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
614 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
615
616 /* Enmotus */
617 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
618
619 /* Loongson */
620 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
621
622 /* Generic, PCI class code for AHCI */
623 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
624 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
625
626 { } /* terminate list */
627 };
628
629 static const struct dev_pm_ops ahci_pci_pm_ops = {
630 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
631 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
632 ahci_pci_device_runtime_resume, NULL)
633 };
634
635 static struct pci_driver ahci_pci_driver = {
636 .name = DRV_NAME,
637 .id_table = ahci_pci_tbl,
638 .probe = ahci_init_one,
639 .remove = ahci_remove_one,
640 .shutdown = ahci_shutdown_one,
641 .driver = {
642 .pm = &ahci_pci_pm_ops,
643 },
644 };
645
646 #if IS_ENABLED(CONFIG_PATA_MARVELL)
647 static int marvell_enable;
648 #else
649 static int marvell_enable = 1;
650 #endif
651 module_param(marvell_enable, int, 0644);
652 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
653
654 static int mobile_lpm_policy = -1;
655 module_param(mobile_lpm_policy, int, 0644);
656 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
657
ahci_pci_save_initial_config(struct pci_dev * pdev,struct ahci_host_priv * hpriv)658 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
659 struct ahci_host_priv *hpriv)
660 {
661 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
662 dev_info(&pdev->dev, "JMB361 has only one port\n");
663 hpriv->force_port_map = 1;
664 }
665
666 /*
667 * Temporary Marvell 6145 hack: PATA port presence
668 * is asserted through the standard AHCI port
669 * presence register, as bit 4 (counting from 0)
670 */
671 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
672 if (pdev->device == 0x6121)
673 hpriv->mask_port_map = 0x3;
674 else
675 hpriv->mask_port_map = 0xf;
676 dev_info(&pdev->dev,
677 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
678 }
679
680 ahci_save_initial_config(&pdev->dev, hpriv);
681 }
682
ahci_pci_reset_controller(struct ata_host * host)683 static int ahci_pci_reset_controller(struct ata_host *host)
684 {
685 struct pci_dev *pdev = to_pci_dev(host->dev);
686 struct ahci_host_priv *hpriv = host->private_data;
687 int rc;
688
689 rc = ahci_reset_controller(host);
690 if (rc)
691 return rc;
692
693 /*
694 * If platform firmware failed to enable ports, try to enable
695 * them here.
696 */
697 ahci_intel_pcs_quirk(pdev, hpriv);
698
699 return 0;
700 }
701
ahci_pci_init_controller(struct ata_host * host)702 static void ahci_pci_init_controller(struct ata_host *host)
703 {
704 struct ahci_host_priv *hpriv = host->private_data;
705 struct pci_dev *pdev = to_pci_dev(host->dev);
706 void __iomem *port_mmio;
707 u32 tmp;
708 int mv;
709
710 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
711 if (pdev->device == 0x6121)
712 mv = 2;
713 else
714 mv = 4;
715 port_mmio = __ahci_port_base(host, mv);
716
717 writel(0, port_mmio + PORT_IRQ_MASK);
718
719 /* clear port IRQ */
720 tmp = readl(port_mmio + PORT_IRQ_STAT);
721 dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
722 if (tmp)
723 writel(tmp, port_mmio + PORT_IRQ_STAT);
724 }
725
726 ahci_init_controller(host);
727 }
728
ahci_vt8251_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)729 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
730 unsigned long deadline)
731 {
732 struct ata_port *ap = link->ap;
733 struct ahci_host_priv *hpriv = ap->host->private_data;
734 bool online;
735 int rc;
736
737 DPRINTK("ENTER\n");
738
739 hpriv->stop_engine(ap);
740
741 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
742 deadline, &online, NULL);
743
744 hpriv->start_engine(ap);
745
746 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
747
748 /* vt8251 doesn't clear BSY on signature FIS reception,
749 * request follow-up softreset.
750 */
751 return online ? -EAGAIN : rc;
752 }
753
ahci_p5wdh_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)754 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
755 unsigned long deadline)
756 {
757 struct ata_port *ap = link->ap;
758 struct ahci_port_priv *pp = ap->private_data;
759 struct ahci_host_priv *hpriv = ap->host->private_data;
760 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
761 struct ata_taskfile tf;
762 bool online;
763 int rc;
764
765 hpriv->stop_engine(ap);
766
767 /* clear D2H reception area to properly wait for D2H FIS */
768 ata_tf_init(link->device, &tf);
769 tf.status = ATA_BUSY;
770 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
771
772 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
773 deadline, &online, NULL);
774
775 hpriv->start_engine(ap);
776
777 /* The pseudo configuration device on SIMG4726 attached to
778 * ASUS P5W-DH Deluxe doesn't send signature FIS after
779 * hardreset if no device is attached to the first downstream
780 * port && the pseudo device locks up on SRST w/ PMP==0. To
781 * work around this, wait for !BSY only briefly. If BSY isn't
782 * cleared, perform CLO and proceed to IDENTIFY (achieved by
783 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
784 *
785 * Wait for two seconds. Devices attached to downstream port
786 * which can't process the following IDENTIFY after this will
787 * have to be reset again. For most cases, this should
788 * suffice while making probing snappish enough.
789 */
790 if (online) {
791 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
792 ahci_check_ready);
793 if (rc)
794 ahci_kick_engine(ap);
795 }
796 return rc;
797 }
798
799 /*
800 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
801 *
802 * It has been observed with some SSDs that the timing of events in the
803 * link synchronization phase can leave the port in a state that can not
804 * be recovered by a SATA-hard-reset alone. The failing signature is
805 * SStatus.DET stuck at 1 ("Device presence detected but Phy
806 * communication not established"). It was found that unloading and
807 * reloading the driver when this problem occurs allows the drive
808 * connection to be recovered (DET advanced to 0x3). The critical
809 * component of reloading the driver is that the port state machines are
810 * reset by bouncing "port enable" in the AHCI PCS configuration
811 * register. So, reproduce that effect by bouncing a port whenever we
812 * see DET==1 after a reset.
813 */
ahci_avn_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)814 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
815 unsigned long deadline)
816 {
817 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
818 struct ata_port *ap = link->ap;
819 struct ahci_port_priv *pp = ap->private_data;
820 struct ahci_host_priv *hpriv = ap->host->private_data;
821 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
822 unsigned long tmo = deadline - jiffies;
823 struct ata_taskfile tf;
824 bool online;
825 int rc, i;
826
827 DPRINTK("ENTER\n");
828
829 hpriv->stop_engine(ap);
830
831 for (i = 0; i < 2; i++) {
832 u16 val;
833 u32 sstatus;
834 int port = ap->port_no;
835 struct ata_host *host = ap->host;
836 struct pci_dev *pdev = to_pci_dev(host->dev);
837
838 /* clear D2H reception area to properly wait for D2H FIS */
839 ata_tf_init(link->device, &tf);
840 tf.status = ATA_BUSY;
841 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
842
843 rc = sata_link_hardreset(link, timing, deadline, &online,
844 ahci_check_ready);
845
846 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
847 (sstatus & 0xf) != 1)
848 break;
849
850 ata_link_info(link, "avn bounce port%d\n", port);
851
852 pci_read_config_word(pdev, 0x92, &val);
853 val &= ~(1 << port);
854 pci_write_config_word(pdev, 0x92, val);
855 ata_msleep(ap, 1000);
856 val |= 1 << port;
857 pci_write_config_word(pdev, 0x92, val);
858 deadline += tmo;
859 }
860
861 hpriv->start_engine(ap);
862
863 if (online)
864 *class = ahci_dev_classify(ap);
865
866 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
867 return rc;
868 }
869
870
871 #ifdef CONFIG_PM
ahci_pci_disable_interrupts(struct ata_host * host)872 static void ahci_pci_disable_interrupts(struct ata_host *host)
873 {
874 struct ahci_host_priv *hpriv = host->private_data;
875 void __iomem *mmio = hpriv->mmio;
876 u32 ctl;
877
878 /* AHCI spec rev1.1 section 8.3.3:
879 * Software must disable interrupts prior to requesting a
880 * transition of the HBA to D3 state.
881 */
882 ctl = readl(mmio + HOST_CTL);
883 ctl &= ~HOST_IRQ_EN;
884 writel(ctl, mmio + HOST_CTL);
885 readl(mmio + HOST_CTL); /* flush */
886 }
887
ahci_pci_device_runtime_suspend(struct device * dev)888 static int ahci_pci_device_runtime_suspend(struct device *dev)
889 {
890 struct pci_dev *pdev = to_pci_dev(dev);
891 struct ata_host *host = pci_get_drvdata(pdev);
892
893 ahci_pci_disable_interrupts(host);
894 return 0;
895 }
896
ahci_pci_device_runtime_resume(struct device * dev)897 static int ahci_pci_device_runtime_resume(struct device *dev)
898 {
899 struct pci_dev *pdev = to_pci_dev(dev);
900 struct ata_host *host = pci_get_drvdata(pdev);
901 int rc;
902
903 rc = ahci_pci_reset_controller(host);
904 if (rc)
905 return rc;
906 ahci_pci_init_controller(host);
907 return 0;
908 }
909
910 #ifdef CONFIG_PM_SLEEP
ahci_pci_device_suspend(struct device * dev)911 static int ahci_pci_device_suspend(struct device *dev)
912 {
913 struct pci_dev *pdev = to_pci_dev(dev);
914 struct ata_host *host = pci_get_drvdata(pdev);
915 struct ahci_host_priv *hpriv = host->private_data;
916
917 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
918 dev_err(&pdev->dev,
919 "BIOS update required for suspend/resume\n");
920 return -EIO;
921 }
922
923 ahci_pci_disable_interrupts(host);
924 return ata_host_suspend(host, PMSG_SUSPEND);
925 }
926
ahci_pci_device_resume(struct device * dev)927 static int ahci_pci_device_resume(struct device *dev)
928 {
929 struct pci_dev *pdev = to_pci_dev(dev);
930 struct ata_host *host = pci_get_drvdata(pdev);
931 int rc;
932
933 /* Apple BIOS helpfully mangles the registers on resume */
934 if (is_mcp89_apple(pdev))
935 ahci_mcp89_apple_enable(pdev);
936
937 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
938 rc = ahci_pci_reset_controller(host);
939 if (rc)
940 return rc;
941
942 ahci_pci_init_controller(host);
943 }
944
945 ata_host_resume(host);
946
947 return 0;
948 }
949 #endif
950
951 #endif /* CONFIG_PM */
952
ahci_configure_dma_masks(struct pci_dev * pdev,int using_dac)953 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
954 {
955 const int dma_bits = using_dac ? 64 : 32;
956 int rc;
957
958 /*
959 * If the device fixup already set the dma_mask to some non-standard
960 * value, don't extend it here. This happens on STA2X11, for example.
961 *
962 * XXX: manipulating the DMA mask from platform code is completely
963 * bogus, platform code should use dev->bus_dma_limit instead..
964 */
965 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
966 return 0;
967
968 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
969 if (rc)
970 dev_err(&pdev->dev, "DMA enable failed\n");
971 return rc;
972 }
973
ahci_pci_print_info(struct ata_host * host)974 static void ahci_pci_print_info(struct ata_host *host)
975 {
976 struct pci_dev *pdev = to_pci_dev(host->dev);
977 u16 cc;
978 const char *scc_s;
979
980 pci_read_config_word(pdev, 0x0a, &cc);
981 if (cc == PCI_CLASS_STORAGE_IDE)
982 scc_s = "IDE";
983 else if (cc == PCI_CLASS_STORAGE_SATA)
984 scc_s = "SATA";
985 else if (cc == PCI_CLASS_STORAGE_RAID)
986 scc_s = "RAID";
987 else
988 scc_s = "unknown";
989
990 ahci_print_info(host, scc_s);
991 }
992
993 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
994 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
995 * support PMP and the 4726 either directly exports the device
996 * attached to the first downstream port or acts as a hardware storage
997 * controller and emulate a single ATA device (can be RAID 0/1 or some
998 * other configuration).
999 *
1000 * When there's no device attached to the first downstream port of the
1001 * 4726, "Config Disk" appears, which is a pseudo ATA device to
1002 * configure the 4726. However, ATA emulation of the device is very
1003 * lame. It doesn't send signature D2H Reg FIS after the initial
1004 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
1005 *
1006 * The following function works around the problem by always using
1007 * hardreset on the port and not depending on receiving signature FIS
1008 * afterward. If signature FIS isn't received soon, ATA class is
1009 * assumed without follow-up softreset.
1010 */
ahci_p5wdh_workaround(struct ata_host * host)1011 static void ahci_p5wdh_workaround(struct ata_host *host)
1012 {
1013 static const struct dmi_system_id sysids[] = {
1014 {
1015 .ident = "P5W DH Deluxe",
1016 .matches = {
1017 DMI_MATCH(DMI_SYS_VENDOR,
1018 "ASUSTEK COMPUTER INC"),
1019 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
1020 },
1021 },
1022 { }
1023 };
1024 struct pci_dev *pdev = to_pci_dev(host->dev);
1025
1026 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
1027 dmi_check_system(sysids)) {
1028 struct ata_port *ap = host->ports[1];
1029
1030 dev_info(&pdev->dev,
1031 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1032
1033 ap->ops = &ahci_p5wdh_ops;
1034 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1035 }
1036 }
1037
1038 /*
1039 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1040 * booting in BIOS compatibility mode. We restore the registers but not ID.
1041 */
ahci_mcp89_apple_enable(struct pci_dev * pdev)1042 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1043 {
1044 u32 val;
1045
1046 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1047
1048 pci_read_config_dword(pdev, 0xf8, &val);
1049 val |= 1 << 0x1b;
1050 /* the following changes the device ID, but appears not to affect function */
1051 /* val = (val & ~0xf0000000) | 0x80000000; */
1052 pci_write_config_dword(pdev, 0xf8, val);
1053
1054 pci_read_config_dword(pdev, 0x54c, &val);
1055 val |= 1 << 0xc;
1056 pci_write_config_dword(pdev, 0x54c, val);
1057
1058 pci_read_config_dword(pdev, 0x4a4, &val);
1059 val &= 0xff;
1060 val |= 0x01060100;
1061 pci_write_config_dword(pdev, 0x4a4, val);
1062
1063 pci_read_config_dword(pdev, 0x54c, &val);
1064 val &= ~(1 << 0xc);
1065 pci_write_config_dword(pdev, 0x54c, val);
1066
1067 pci_read_config_dword(pdev, 0xf8, &val);
1068 val &= ~(1 << 0x1b);
1069 pci_write_config_dword(pdev, 0xf8, val);
1070 }
1071
is_mcp89_apple(struct pci_dev * pdev)1072 static bool is_mcp89_apple(struct pci_dev *pdev)
1073 {
1074 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1075 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1076 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1077 pdev->subsystem_device == 0xcb89;
1078 }
1079
1080 /* only some SB600 ahci controllers can do 64bit DMA */
ahci_sb600_enable_64bit(struct pci_dev * pdev)1081 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1082 {
1083 static const struct dmi_system_id sysids[] = {
1084 /*
1085 * The oldest version known to be broken is 0901 and
1086 * working is 1501 which was released on 2007-10-26.
1087 * Enable 64bit DMA on 1501 and anything newer.
1088 *
1089 * Please read bko#9412 for more info.
1090 */
1091 {
1092 .ident = "ASUS M2A-VM",
1093 .matches = {
1094 DMI_MATCH(DMI_BOARD_VENDOR,
1095 "ASUSTeK Computer INC."),
1096 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1097 },
1098 .driver_data = "20071026", /* yyyymmdd */
1099 },
1100 /*
1101 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1102 * support 64bit DMA.
1103 *
1104 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1105 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1106 * This spelling mistake was fixed in BIOS version 1.5, so
1107 * 1.5 and later have the Manufacturer as
1108 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1109 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1110 *
1111 * BIOS versions earlier than 1.9 had a Board Product Name
1112 * DMI field of "MS-7376". This was changed to be
1113 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1114 * match on DMI_BOARD_NAME of "MS-7376".
1115 */
1116 {
1117 .ident = "MSI K9A2 Platinum",
1118 .matches = {
1119 DMI_MATCH(DMI_BOARD_VENDOR,
1120 "MICRO-STAR INTER"),
1121 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1122 },
1123 },
1124 /*
1125 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1126 * 64bit DMA.
1127 *
1128 * This board also had the typo mentioned above in the
1129 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1130 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1131 */
1132 {
1133 .ident = "MSI K9AGM2",
1134 .matches = {
1135 DMI_MATCH(DMI_BOARD_VENDOR,
1136 "MICRO-STAR INTER"),
1137 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1138 },
1139 },
1140 /*
1141 * All BIOS versions for the Asus M3A support 64bit DMA.
1142 * (all release versions from 0301 to 1206 were tested)
1143 */
1144 {
1145 .ident = "ASUS M3A",
1146 .matches = {
1147 DMI_MATCH(DMI_BOARD_VENDOR,
1148 "ASUSTeK Computer INC."),
1149 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1150 },
1151 },
1152 { }
1153 };
1154 const struct dmi_system_id *match;
1155 int year, month, date;
1156 char buf[9];
1157
1158 match = dmi_first_match(sysids);
1159 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1160 !match)
1161 return false;
1162
1163 if (!match->driver_data)
1164 goto enable_64bit;
1165
1166 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1167 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1168
1169 if (strcmp(buf, match->driver_data) >= 0)
1170 goto enable_64bit;
1171 else {
1172 dev_warn(&pdev->dev,
1173 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1174 match->ident);
1175 return false;
1176 }
1177
1178 enable_64bit:
1179 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1180 return true;
1181 }
1182
ahci_broken_system_poweroff(struct pci_dev * pdev)1183 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1184 {
1185 static const struct dmi_system_id broken_systems[] = {
1186 {
1187 .ident = "HP Compaq nx6310",
1188 .matches = {
1189 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1190 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1191 },
1192 /* PCI slot number of the controller */
1193 .driver_data = (void *)0x1FUL,
1194 },
1195 {
1196 .ident = "HP Compaq 6720s",
1197 .matches = {
1198 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1199 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1200 },
1201 /* PCI slot number of the controller */
1202 .driver_data = (void *)0x1FUL,
1203 },
1204
1205 { } /* terminate list */
1206 };
1207 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1208
1209 if (dmi) {
1210 unsigned long slot = (unsigned long)dmi->driver_data;
1211 /* apply the quirk only to on-board controllers */
1212 return slot == PCI_SLOT(pdev->devfn);
1213 }
1214
1215 return false;
1216 }
1217
ahci_broken_suspend(struct pci_dev * pdev)1218 static bool ahci_broken_suspend(struct pci_dev *pdev)
1219 {
1220 static const struct dmi_system_id sysids[] = {
1221 /*
1222 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1223 * to the harddisk doesn't become online after
1224 * resuming from STR. Warn and fail suspend.
1225 *
1226 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1227 *
1228 * Use dates instead of versions to match as HP is
1229 * apparently recycling both product and version
1230 * strings.
1231 *
1232 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1233 */
1234 {
1235 .ident = "dv4",
1236 .matches = {
1237 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1238 DMI_MATCH(DMI_PRODUCT_NAME,
1239 "HP Pavilion dv4 Notebook PC"),
1240 },
1241 .driver_data = "20090105", /* F.30 */
1242 },
1243 {
1244 .ident = "dv5",
1245 .matches = {
1246 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1247 DMI_MATCH(DMI_PRODUCT_NAME,
1248 "HP Pavilion dv5 Notebook PC"),
1249 },
1250 .driver_data = "20090506", /* F.16 */
1251 },
1252 {
1253 .ident = "dv6",
1254 .matches = {
1255 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1256 DMI_MATCH(DMI_PRODUCT_NAME,
1257 "HP Pavilion dv6 Notebook PC"),
1258 },
1259 .driver_data = "20090423", /* F.21 */
1260 },
1261 {
1262 .ident = "HDX18",
1263 .matches = {
1264 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1265 DMI_MATCH(DMI_PRODUCT_NAME,
1266 "HP HDX18 Notebook PC"),
1267 },
1268 .driver_data = "20090430", /* F.23 */
1269 },
1270 /*
1271 * Acer eMachines G725 has the same problem. BIOS
1272 * V1.03 is known to be broken. V3.04 is known to
1273 * work. Between, there are V1.06, V2.06 and V3.03
1274 * that we don't have much idea about. For now,
1275 * blacklist anything older than V3.04.
1276 *
1277 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1278 */
1279 {
1280 .ident = "G725",
1281 .matches = {
1282 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1283 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1284 },
1285 .driver_data = "20091216", /* V3.04 */
1286 },
1287 { } /* terminate list */
1288 };
1289 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1290 int year, month, date;
1291 char buf[9];
1292
1293 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1294 return false;
1295
1296 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1297 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1298
1299 return strcmp(buf, dmi->driver_data) < 0;
1300 }
1301
ahci_broken_lpm(struct pci_dev * pdev)1302 static bool ahci_broken_lpm(struct pci_dev *pdev)
1303 {
1304 static const struct dmi_system_id sysids[] = {
1305 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1306 {
1307 .matches = {
1308 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1309 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1310 },
1311 .driver_data = "20180406", /* 1.31 */
1312 },
1313 {
1314 .matches = {
1315 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1316 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1317 },
1318 .driver_data = "20180420", /* 1.28 */
1319 },
1320 {
1321 .matches = {
1322 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1323 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1324 },
1325 .driver_data = "20180315", /* 1.33 */
1326 },
1327 {
1328 .matches = {
1329 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1330 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1331 },
1332 /*
1333 * Note date based on release notes, 2.35 has been
1334 * reported to be good, but I've been unable to get
1335 * a hold of the reporter to get the DMI BIOS date.
1336 * TODO: fix this.
1337 */
1338 .driver_data = "20180310", /* 2.35 */
1339 },
1340 { } /* terminate list */
1341 };
1342 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1343 int year, month, date;
1344 char buf[9];
1345
1346 if (!dmi)
1347 return false;
1348
1349 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1350 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1351
1352 return strcmp(buf, dmi->driver_data) < 0;
1353 }
1354
ahci_broken_online(struct pci_dev * pdev)1355 static bool ahci_broken_online(struct pci_dev *pdev)
1356 {
1357 #define ENCODE_BUSDEVFN(bus, slot, func) \
1358 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1359 static const struct dmi_system_id sysids[] = {
1360 /*
1361 * There are several gigabyte boards which use
1362 * SIMG5723s configured as hardware RAID. Certain
1363 * 5723 firmware revisions shipped there keep the link
1364 * online but fail to answer properly to SRST or
1365 * IDENTIFY when no device is attached downstream
1366 * causing libata to retry quite a few times leading
1367 * to excessive detection delay.
1368 *
1369 * As these firmwares respond to the second reset try
1370 * with invalid device signature, considering unknown
1371 * sig as offline works around the problem acceptably.
1372 */
1373 {
1374 .ident = "EP45-DQ6",
1375 .matches = {
1376 DMI_MATCH(DMI_BOARD_VENDOR,
1377 "Gigabyte Technology Co., Ltd."),
1378 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1379 },
1380 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1381 },
1382 {
1383 .ident = "EP45-DS5",
1384 .matches = {
1385 DMI_MATCH(DMI_BOARD_VENDOR,
1386 "Gigabyte Technology Co., Ltd."),
1387 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1388 },
1389 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1390 },
1391 { } /* terminate list */
1392 };
1393 #undef ENCODE_BUSDEVFN
1394 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1395 unsigned int val;
1396
1397 if (!dmi)
1398 return false;
1399
1400 val = (unsigned long)dmi->driver_data;
1401
1402 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1403 }
1404
ahci_broken_devslp(struct pci_dev * pdev)1405 static bool ahci_broken_devslp(struct pci_dev *pdev)
1406 {
1407 /* device with broken DEVSLP but still showing SDS capability */
1408 static const struct pci_device_id ids[] = {
1409 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1410 {}
1411 };
1412
1413 return pci_match_id(ids, pdev);
1414 }
1415
1416 #ifdef CONFIG_ATA_ACPI
ahci_gtf_filter_workaround(struct ata_host * host)1417 static void ahci_gtf_filter_workaround(struct ata_host *host)
1418 {
1419 static const struct dmi_system_id sysids[] = {
1420 /*
1421 * Aspire 3810T issues a bunch of SATA enable commands
1422 * via _GTF including an invalid one and one which is
1423 * rejected by the device. Among the successful ones
1424 * is FPDMA non-zero offset enable which when enabled
1425 * only on the drive side leads to NCQ command
1426 * failures. Filter it out.
1427 */
1428 {
1429 .ident = "Aspire 3810T",
1430 .matches = {
1431 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1432 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1433 },
1434 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1435 },
1436 { }
1437 };
1438 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1439 unsigned int filter;
1440 int i;
1441
1442 if (!dmi)
1443 return;
1444
1445 filter = (unsigned long)dmi->driver_data;
1446 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1447 filter, dmi->ident);
1448
1449 for (i = 0; i < host->n_ports; i++) {
1450 struct ata_port *ap = host->ports[i];
1451 struct ata_link *link;
1452 struct ata_device *dev;
1453
1454 ata_for_each_link(link, ap, EDGE)
1455 ata_for_each_dev(dev, link, ALL)
1456 dev->gtf_filter |= filter;
1457 }
1458 }
1459 #else
ahci_gtf_filter_workaround(struct ata_host * host)1460 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1461 {}
1462 #endif
1463
1464 /*
1465 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1466 * as DUMMY, or detected but eventually get a "link down" and never get up
1467 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1468 * port_map may hold a value of 0x00.
1469 *
1470 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1471 * and can significantly reduce the occurrence of the problem.
1472 *
1473 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1474 */
acer_sa5_271_workaround(struct ahci_host_priv * hpriv,struct pci_dev * pdev)1475 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1476 struct pci_dev *pdev)
1477 {
1478 static const struct dmi_system_id sysids[] = {
1479 {
1480 .ident = "Acer Switch Alpha 12",
1481 .matches = {
1482 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1483 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1484 },
1485 },
1486 { }
1487 };
1488
1489 if (dmi_check_system(sysids)) {
1490 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1491 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1492 hpriv->port_map = 0x7;
1493 hpriv->cap = 0xC734FF02;
1494 }
1495 }
1496 }
1497
1498 #ifdef CONFIG_ARM64
1499 /*
1500 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1501 * Workaround is to make sure all pending IRQs are served before leaving
1502 * handler.
1503 */
ahci_thunderx_irq_handler(int irq,void * dev_instance)1504 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1505 {
1506 struct ata_host *host = dev_instance;
1507 struct ahci_host_priv *hpriv;
1508 unsigned int rc = 0;
1509 void __iomem *mmio;
1510 u32 irq_stat, irq_masked;
1511 unsigned int handled = 1;
1512
1513 hpriv = host->private_data;
1514 mmio = hpriv->mmio;
1515 irq_stat = readl(mmio + HOST_IRQ_STAT);
1516 if (!irq_stat)
1517 return IRQ_NONE;
1518
1519 do {
1520 irq_masked = irq_stat & hpriv->port_map;
1521 spin_lock(&host->lock);
1522 rc = ahci_handle_port_intr(host, irq_masked);
1523 if (!rc)
1524 handled = 0;
1525 writel(irq_stat, mmio + HOST_IRQ_STAT);
1526 irq_stat = readl(mmio + HOST_IRQ_STAT);
1527 spin_unlock(&host->lock);
1528 } while (irq_stat);
1529
1530 return IRQ_RETVAL(handled);
1531 }
1532 #endif
1533
ahci_remap_check(struct pci_dev * pdev,int bar,struct ahci_host_priv * hpriv)1534 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1535 struct ahci_host_priv *hpriv)
1536 {
1537 int i;
1538 u32 cap;
1539
1540 /*
1541 * Check if this device might have remapped nvme devices.
1542 */
1543 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1544 pci_resource_len(pdev, bar) < SZ_512K ||
1545 bar != AHCI_PCI_BAR_STANDARD ||
1546 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1547 return;
1548
1549 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1550 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1551 if ((cap & (1 << i)) == 0)
1552 continue;
1553 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1554 != PCI_CLASS_STORAGE_EXPRESS)
1555 continue;
1556
1557 /* We've found a remapped device */
1558 hpriv->remapped_nvme++;
1559 }
1560
1561 if (!hpriv->remapped_nvme)
1562 return;
1563
1564 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1565 hpriv->remapped_nvme);
1566 dev_warn(&pdev->dev,
1567 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1568
1569 /*
1570 * Don't rely on the msi-x capability in the remap case,
1571 * share the legacy interrupt across ahci and remapped devices.
1572 */
1573 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1574 }
1575
ahci_get_irq_vector(struct ata_host * host,int port)1576 static int ahci_get_irq_vector(struct ata_host *host, int port)
1577 {
1578 return pci_irq_vector(to_pci_dev(host->dev), port);
1579 }
1580
ahci_init_msi(struct pci_dev * pdev,unsigned int n_ports,struct ahci_host_priv * hpriv)1581 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1582 struct ahci_host_priv *hpriv)
1583 {
1584 int nvec;
1585
1586 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1587 return -ENODEV;
1588
1589 /*
1590 * If number of MSIs is less than number of ports then Sharing Last
1591 * Message mode could be enforced. In this case assume that advantage
1592 * of multipe MSIs is negated and use single MSI mode instead.
1593 */
1594 if (n_ports > 1) {
1595 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1596 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1597 if (nvec > 0) {
1598 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1599 hpriv->get_irq_vector = ahci_get_irq_vector;
1600 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1601 return nvec;
1602 }
1603
1604 /*
1605 * Fallback to single MSI mode if the controller
1606 * enforced MRSM mode.
1607 */
1608 printk(KERN_INFO
1609 "ahci: MRSM is on, fallback to single MSI\n");
1610 pci_free_irq_vectors(pdev);
1611 }
1612 }
1613
1614 /*
1615 * If the host is not capable of supporting per-port vectors, fall
1616 * back to single MSI before finally attempting single MSI-X.
1617 */
1618 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1619 if (nvec == 1)
1620 return nvec;
1621 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1622 }
1623
ahci_update_initial_lpm_policy(struct ata_port * ap,struct ahci_host_priv * hpriv)1624 static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1625 struct ahci_host_priv *hpriv)
1626 {
1627 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1628
1629
1630 /* Ignore processing for non mobile platforms */
1631 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
1632 return;
1633
1634 /* user modified policy via module param */
1635 if (mobile_lpm_policy != -1) {
1636 policy = mobile_lpm_policy;
1637 goto update_policy;
1638 }
1639
1640 #ifdef CONFIG_ACPI
1641 if (policy > ATA_LPM_MED_POWER &&
1642 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1643 if (hpriv->cap & HOST_CAP_PART)
1644 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1645 else if (hpriv->cap & HOST_CAP_SSC)
1646 policy = ATA_LPM_MIN_POWER;
1647 }
1648 #endif
1649
1650 update_policy:
1651 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1652 ap->target_lpm_policy = policy;
1653 }
1654
ahci_intel_pcs_quirk(struct pci_dev * pdev,struct ahci_host_priv * hpriv)1655 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1656 {
1657 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1658 u16 tmp16;
1659
1660 /*
1661 * Only apply the 6-port PCS quirk for known legacy platforms.
1662 */
1663 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1664 return;
1665
1666 /* Skip applying the quirk on Denverton and beyond */
1667 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1668 return;
1669
1670 /*
1671 * port_map is determined from PORTS_IMPL PCI register which is
1672 * implemented as write or write-once register. If the register
1673 * isn't programmed, ahci automatically generates it from number
1674 * of ports, which is good enough for PCS programming. It is
1675 * otherwise expected that platform firmware enables the ports
1676 * before the OS boots.
1677 */
1678 pci_read_config_word(pdev, PCS_6, &tmp16);
1679 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1680 tmp16 |= hpriv->port_map;
1681 pci_write_config_word(pdev, PCS_6, tmp16);
1682 }
1683 }
1684
remapped_nvme_show(struct device * dev,struct device_attribute * attr,char * buf)1685 static ssize_t remapped_nvme_show(struct device *dev,
1686 struct device_attribute *attr,
1687 char *buf)
1688 {
1689 struct ata_host *host = dev_get_drvdata(dev);
1690 struct ahci_host_priv *hpriv = host->private_data;
1691
1692 return sprintf(buf, "%u\n", hpriv->remapped_nvme);
1693 }
1694
1695 static DEVICE_ATTR_RO(remapped_nvme);
1696
ahci_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)1697 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1698 {
1699 unsigned int board_id = ent->driver_data;
1700 struct ata_port_info pi = ahci_port_info[board_id];
1701 const struct ata_port_info *ppi[] = { &pi, NULL };
1702 struct device *dev = &pdev->dev;
1703 struct ahci_host_priv *hpriv;
1704 struct ata_host *host;
1705 int n_ports, i, rc;
1706 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1707
1708 VPRINTK("ENTER\n");
1709
1710 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1711
1712 ata_print_version_once(&pdev->dev, DRV_VERSION);
1713
1714 /* The AHCI driver can only drive the SATA ports, the PATA driver
1715 can drive them all so if both drivers are selected make sure
1716 AHCI stays out of the way */
1717 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1718 return -ENODEV;
1719
1720 /* Apple BIOS on MCP89 prevents us using AHCI */
1721 if (is_mcp89_apple(pdev))
1722 ahci_mcp89_apple_enable(pdev);
1723
1724 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1725 * At the moment, we can only use the AHCI mode. Let the users know
1726 * that for SAS drives they're out of luck.
1727 */
1728 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1729 dev_info(&pdev->dev,
1730 "PDC42819 can only drive SATA devices with this driver\n");
1731
1732 /* Some devices use non-standard BARs */
1733 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1734 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1735 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1736 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1737 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1738 if (pdev->device == 0xa01c)
1739 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1740 if (pdev->device == 0xa084)
1741 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1742 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1743 if (pdev->device == 0x7a08)
1744 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
1745 }
1746
1747 /* acquire resources */
1748 rc = pcim_enable_device(pdev);
1749 if (rc)
1750 return rc;
1751
1752 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1753 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1754 u8 map;
1755
1756 /* ICH6s share the same PCI ID for both piix and ahci
1757 * modes. Enabling ahci mode while MAP indicates
1758 * combined mode is a bad idea. Yield to ata_piix.
1759 */
1760 pci_read_config_byte(pdev, ICH_MAP, &map);
1761 if (map & 0x3) {
1762 dev_info(&pdev->dev,
1763 "controller is in combined mode, can't enable AHCI mode\n");
1764 return -ENODEV;
1765 }
1766 }
1767
1768 /* AHCI controllers often implement SFF compatible interface.
1769 * Grab all PCI BARs just in case.
1770 */
1771 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1772 if (rc == -EBUSY)
1773 pcim_pin_device(pdev);
1774 if (rc)
1775 return rc;
1776
1777 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1778 if (!hpriv)
1779 return -ENOMEM;
1780 hpriv->flags |= (unsigned long)pi.private_data;
1781
1782 /* MCP65 revision A1 and A2 can't do MSI */
1783 if (board_id == board_ahci_mcp65 &&
1784 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1785 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1786
1787 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1788 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1789 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1790
1791 /* only some SB600s can do 64bit DMA */
1792 if (ahci_sb600_enable_64bit(pdev))
1793 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1794
1795 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1796
1797 /* detect remapped nvme devices */
1798 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1799
1800 sysfs_add_file_to_group(&pdev->dev.kobj,
1801 &dev_attr_remapped_nvme.attr,
1802 NULL);
1803
1804 /* must set flag prior to save config in order to take effect */
1805 if (ahci_broken_devslp(pdev))
1806 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1807
1808 #ifdef CONFIG_ARM64
1809 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1810 pdev->device == 0xa235 &&
1811 pdev->revision < 0x30)
1812 hpriv->flags |= AHCI_HFLAG_NO_SXS;
1813
1814 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1815 hpriv->irq_handler = ahci_thunderx_irq_handler;
1816 #endif
1817
1818 /* save initial config */
1819 ahci_pci_save_initial_config(pdev, hpriv);
1820
1821 /* prepare host */
1822 if (hpriv->cap & HOST_CAP_NCQ) {
1823 pi.flags |= ATA_FLAG_NCQ;
1824 /*
1825 * Auto-activate optimization is supposed to be
1826 * supported on all AHCI controllers indicating NCQ
1827 * capability, but it seems to be broken on some
1828 * chipsets including NVIDIAs.
1829 */
1830 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1831 pi.flags |= ATA_FLAG_FPDMA_AA;
1832
1833 /*
1834 * All AHCI controllers should be forward-compatible
1835 * with the new auxiliary field. This code should be
1836 * conditionalized if any buggy AHCI controllers are
1837 * encountered.
1838 */
1839 pi.flags |= ATA_FLAG_FPDMA_AUX;
1840 }
1841
1842 if (hpriv->cap & HOST_CAP_PMP)
1843 pi.flags |= ATA_FLAG_PMP;
1844
1845 ahci_set_em_messages(hpriv, &pi);
1846
1847 if (ahci_broken_system_poweroff(pdev)) {
1848 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1849 dev_info(&pdev->dev,
1850 "quirky BIOS, skipping spindown on poweroff\n");
1851 }
1852
1853 if (ahci_broken_lpm(pdev)) {
1854 pi.flags |= ATA_FLAG_NO_LPM;
1855 dev_warn(&pdev->dev,
1856 "BIOS update required for Link Power Management support\n");
1857 }
1858
1859 if (ahci_broken_suspend(pdev)) {
1860 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1861 dev_warn(&pdev->dev,
1862 "BIOS update required for suspend/resume\n");
1863 }
1864
1865 if (ahci_broken_online(pdev)) {
1866 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1867 dev_info(&pdev->dev,
1868 "online status unreliable, applying workaround\n");
1869 }
1870
1871
1872 /* Acer SA5-271 workaround modifies private_data */
1873 acer_sa5_271_workaround(hpriv, pdev);
1874
1875 /* CAP.NP sometimes indicate the index of the last enabled
1876 * port, at other times, that of the last possible port, so
1877 * determining the maximum port number requires looking at
1878 * both CAP.NP and port_map.
1879 */
1880 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1881
1882 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1883 if (!host)
1884 return -ENOMEM;
1885 host->private_data = hpriv;
1886
1887 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1888 /* legacy intx interrupts */
1889 pci_intx(pdev, 1);
1890 }
1891 hpriv->irq = pci_irq_vector(pdev, 0);
1892
1893 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1894 host->flags |= ATA_HOST_PARALLEL_SCAN;
1895 else
1896 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1897
1898 if (!(hpriv->cap & HOST_CAP_PART))
1899 host->flags |= ATA_HOST_NO_PART;
1900
1901 if (!(hpriv->cap & HOST_CAP_SSC))
1902 host->flags |= ATA_HOST_NO_SSC;
1903
1904 if (!(hpriv->cap2 & HOST_CAP2_SDS))
1905 host->flags |= ATA_HOST_NO_DEVSLP;
1906
1907 if (pi.flags & ATA_FLAG_EM)
1908 ahci_reset_em(host);
1909
1910 for (i = 0; i < host->n_ports; i++) {
1911 struct ata_port *ap = host->ports[i];
1912
1913 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1914 ata_port_pbar_desc(ap, ahci_pci_bar,
1915 0x100 + ap->port_no * 0x80, "port");
1916
1917 /* set enclosure management message type */
1918 if (ap->flags & ATA_FLAG_EM)
1919 ap->em_message_type = hpriv->em_msg_type;
1920
1921 ahci_update_initial_lpm_policy(ap, hpriv);
1922
1923 /* disabled/not-implemented port */
1924 if (!(hpriv->port_map & (1 << i)))
1925 ap->ops = &ata_dummy_port_ops;
1926 }
1927
1928 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1929 ahci_p5wdh_workaround(host);
1930
1931 /* apply gtf filter quirk */
1932 ahci_gtf_filter_workaround(host);
1933
1934 /* initialize adapter */
1935 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1936 if (rc)
1937 return rc;
1938
1939 rc = ahci_pci_reset_controller(host);
1940 if (rc)
1941 return rc;
1942
1943 ahci_pci_init_controller(host);
1944 ahci_pci_print_info(host);
1945
1946 pci_set_master(pdev);
1947
1948 rc = ahci_host_activate(host, &ahci_sht);
1949 if (rc)
1950 return rc;
1951
1952 pm_runtime_put_noidle(&pdev->dev);
1953 return 0;
1954 }
1955
ahci_shutdown_one(struct pci_dev * pdev)1956 static void ahci_shutdown_one(struct pci_dev *pdev)
1957 {
1958 ata_pci_shutdown_one(pdev);
1959 }
1960
ahci_remove_one(struct pci_dev * pdev)1961 static void ahci_remove_one(struct pci_dev *pdev)
1962 {
1963 sysfs_remove_file_from_group(&pdev->dev.kobj,
1964 &dev_attr_remapped_nvme.attr,
1965 NULL);
1966 pm_runtime_get_noresume(&pdev->dev);
1967 ata_pci_remove_one(pdev);
1968 }
1969
1970 module_pci_driver(ahci_pci_driver);
1971
1972 MODULE_AUTHOR("Jeff Garzik");
1973 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1974 MODULE_LICENSE("GPL");
1975 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1976 MODULE_VERSION(DRV_VERSION);
1977