1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2 /* Copyright(c) 2020 Intel Corporation */
3 #include "adf_gen2_hw_data.h"
4 #include "icp_qat_hw.h"
5 #include <linux/pci.h>
6
adf_gen2_cfg_iov_thds(struct adf_accel_dev * accel_dev,bool enable,int num_a_regs,int num_b_regs)7 void adf_gen2_cfg_iov_thds(struct adf_accel_dev *accel_dev, bool enable,
8 int num_a_regs, int num_b_regs)
9 {
10 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
11 void __iomem *pmisc_addr;
12 struct adf_bar *pmisc;
13 int pmisc_id, i;
14 u32 reg;
15
16 pmisc_id = hw_data->get_misc_bar_id(hw_data);
17 pmisc = &GET_BARS(accel_dev)[pmisc_id];
18 pmisc_addr = pmisc->virt_addr;
19
20 /* Set/Unset Valid bit in AE Thread to PCIe Function Mapping Group A */
21 for (i = 0; i < num_a_regs; i++) {
22 reg = READ_CSR_AE2FUNCTION_MAP_A(pmisc_addr, i);
23 if (enable)
24 reg |= AE2FUNCTION_MAP_VALID;
25 else
26 reg &= ~AE2FUNCTION_MAP_VALID;
27 WRITE_CSR_AE2FUNCTION_MAP_A(pmisc_addr, i, reg);
28 }
29
30 /* Set/Unset Valid bit in AE Thread to PCIe Function Mapping Group B */
31 for (i = 0; i < num_b_regs; i++) {
32 reg = READ_CSR_AE2FUNCTION_MAP_B(pmisc_addr, i);
33 if (enable)
34 reg |= AE2FUNCTION_MAP_VALID;
35 else
36 reg &= ~AE2FUNCTION_MAP_VALID;
37 WRITE_CSR_AE2FUNCTION_MAP_B(pmisc_addr, i, reg);
38 }
39 }
40 EXPORT_SYMBOL_GPL(adf_gen2_cfg_iov_thds);
41
adf_gen2_get_admin_info(struct admin_info * admin_csrs_info)42 void adf_gen2_get_admin_info(struct admin_info *admin_csrs_info)
43 {
44 admin_csrs_info->mailbox_offset = ADF_MAILBOX_BASE_OFFSET;
45 admin_csrs_info->admin_msg_ur = ADF_ADMINMSGUR_OFFSET;
46 admin_csrs_info->admin_msg_lr = ADF_ADMINMSGLR_OFFSET;
47 }
48 EXPORT_SYMBOL_GPL(adf_gen2_get_admin_info);
49
adf_gen2_get_arb_info(struct arb_info * arb_info)50 void adf_gen2_get_arb_info(struct arb_info *arb_info)
51 {
52 arb_info->arb_cfg = ADF_ARB_CONFIG;
53 arb_info->arb_offset = ADF_ARB_OFFSET;
54 arb_info->wt2sam_offset = ADF_ARB_WRK_2_SER_MAP_OFFSET;
55 }
56 EXPORT_SYMBOL_GPL(adf_gen2_get_arb_info);
57
build_csr_ring_base_addr(dma_addr_t addr,u32 size)58 static u64 build_csr_ring_base_addr(dma_addr_t addr, u32 size)
59 {
60 return BUILD_RING_BASE_ADDR(addr, size);
61 }
62
read_csr_ring_head(void __iomem * csr_base_addr,u32 bank,u32 ring)63 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring)
64 {
65 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring);
66 }
67
write_csr_ring_head(void __iomem * csr_base_addr,u32 bank,u32 ring,u32 value)68 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring,
69 u32 value)
70 {
71 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value);
72 }
73
read_csr_ring_tail(void __iomem * csr_base_addr,u32 bank,u32 ring)74 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring)
75 {
76 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring);
77 }
78
write_csr_ring_tail(void __iomem * csr_base_addr,u32 bank,u32 ring,u32 value)79 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring,
80 u32 value)
81 {
82 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value);
83 }
84
read_csr_e_stat(void __iomem * csr_base_addr,u32 bank)85 static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank)
86 {
87 return READ_CSR_E_STAT(csr_base_addr, bank);
88 }
89
write_csr_ring_config(void __iomem * csr_base_addr,u32 bank,u32 ring,u32 value)90 static void write_csr_ring_config(void __iomem *csr_base_addr, u32 bank,
91 u32 ring, u32 value)
92 {
93 WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value);
94 }
95
write_csr_ring_base(void __iomem * csr_base_addr,u32 bank,u32 ring,dma_addr_t addr)96 static void write_csr_ring_base(void __iomem *csr_base_addr, u32 bank, u32 ring,
97 dma_addr_t addr)
98 {
99 WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr);
100 }
101
write_csr_int_flag(void __iomem * csr_base_addr,u32 bank,u32 value)102 static void write_csr_int_flag(void __iomem *csr_base_addr, u32 bank, u32 value)
103 {
104 WRITE_CSR_INT_FLAG(csr_base_addr, bank, value);
105 }
106
write_csr_int_srcsel(void __iomem * csr_base_addr,u32 bank)107 static void write_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank)
108 {
109 WRITE_CSR_INT_SRCSEL(csr_base_addr, bank);
110 }
111
write_csr_int_col_en(void __iomem * csr_base_addr,u32 bank,u32 value)112 static void write_csr_int_col_en(void __iomem *csr_base_addr, u32 bank,
113 u32 value)
114 {
115 WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value);
116 }
117
write_csr_int_col_ctl(void __iomem * csr_base_addr,u32 bank,u32 value)118 static void write_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank,
119 u32 value)
120 {
121 WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value);
122 }
123
write_csr_int_flag_and_col(void __iomem * csr_base_addr,u32 bank,u32 value)124 static void write_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank,
125 u32 value)
126 {
127 WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value);
128 }
129
write_csr_ring_srv_arb_en(void __iomem * csr_base_addr,u32 bank,u32 value)130 static void write_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank,
131 u32 value)
132 {
133 WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value);
134 }
135
adf_gen2_init_hw_csr_ops(struct adf_hw_csr_ops * csr_ops)136 void adf_gen2_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops)
137 {
138 csr_ops->build_csr_ring_base_addr = build_csr_ring_base_addr;
139 csr_ops->read_csr_ring_head = read_csr_ring_head;
140 csr_ops->write_csr_ring_head = write_csr_ring_head;
141 csr_ops->read_csr_ring_tail = read_csr_ring_tail;
142 csr_ops->write_csr_ring_tail = write_csr_ring_tail;
143 csr_ops->read_csr_e_stat = read_csr_e_stat;
144 csr_ops->write_csr_ring_config = write_csr_ring_config;
145 csr_ops->write_csr_ring_base = write_csr_ring_base;
146 csr_ops->write_csr_int_flag = write_csr_int_flag;
147 csr_ops->write_csr_int_srcsel = write_csr_int_srcsel;
148 csr_ops->write_csr_int_col_en = write_csr_int_col_en;
149 csr_ops->write_csr_int_col_ctl = write_csr_int_col_ctl;
150 csr_ops->write_csr_int_flag_and_col = write_csr_int_flag_and_col;
151 csr_ops->write_csr_ring_srv_arb_en = write_csr_ring_srv_arb_en;
152 }
153 EXPORT_SYMBOL_GPL(adf_gen2_init_hw_csr_ops);
154
adf_gen2_get_accel_cap(struct adf_accel_dev * accel_dev)155 u32 adf_gen2_get_accel_cap(struct adf_accel_dev *accel_dev)
156 {
157 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
158 struct pci_dev *pdev = accel_dev->accel_pci_dev.pci_dev;
159 u32 straps = hw_data->straps;
160 u32 fuses = hw_data->fuses;
161 u32 legfuses;
162 u32 capabilities = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |
163 ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
164 ICP_ACCEL_CAPABILITIES_AUTHENTICATION |
165 ICP_ACCEL_CAPABILITIES_CIPHER |
166 ICP_ACCEL_CAPABILITIES_COMPRESSION;
167
168 /* Read accelerator capabilities mask */
169 pci_read_config_dword(pdev, ADF_DEVICE_LEGFUSE_OFFSET, &legfuses);
170
171 /* A set bit in legfuses means the feature is OFF in this SKU */
172 if (legfuses & ICP_ACCEL_MASK_CIPHER_SLICE) {
173 capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;
174 capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
175 }
176 if (legfuses & ICP_ACCEL_MASK_PKE_SLICE)
177 capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
178 if (legfuses & ICP_ACCEL_MASK_AUTH_SLICE) {
179 capabilities &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
180 capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
181 }
182 if (legfuses & ICP_ACCEL_MASK_COMPRESS_SLICE)
183 capabilities &= ~ICP_ACCEL_CAPABILITIES_COMPRESSION;
184
185 if ((straps | fuses) & ADF_POWERGATE_PKE)
186 capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
187
188 if ((straps | fuses) & ADF_POWERGATE_DC)
189 capabilities &= ~ICP_ACCEL_CAPABILITIES_COMPRESSION;
190
191 return capabilities;
192 }
193 EXPORT_SYMBOL_GPL(adf_gen2_get_accel_cap);
194
adf_gen2_set_ssm_wdtimer(struct adf_accel_dev * accel_dev)195 void adf_gen2_set_ssm_wdtimer(struct adf_accel_dev *accel_dev)
196 {
197 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
198 u32 timer_val_pke = ADF_SSM_WDT_PKE_DEFAULT_VALUE;
199 u32 timer_val = ADF_SSM_WDT_DEFAULT_VALUE;
200 unsigned long accel_mask = hw_data->accel_mask;
201 void __iomem *pmisc_addr;
202 struct adf_bar *pmisc;
203 int pmisc_id;
204 u32 i = 0;
205
206 pmisc_id = hw_data->get_misc_bar_id(hw_data);
207 pmisc = &GET_BARS(accel_dev)[pmisc_id];
208 pmisc_addr = pmisc->virt_addr;
209
210 /* Configures WDT timers */
211 for_each_set_bit(i, &accel_mask, hw_data->num_accel) {
212 /* Enable WDT for sym and dc */
213 ADF_CSR_WR(pmisc_addr, ADF_SSMWDT(i), timer_val);
214 /* Enable WDT for pke */
215 ADF_CSR_WR(pmisc_addr, ADF_SSMWDTPKE(i), timer_val_pke);
216 }
217 }
218 EXPORT_SYMBOL_GPL(adf_gen2_set_ssm_wdtimer);
219