1 #ifndef A5XX_XML
2 #define A5XX_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12 - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24
25 Copyright (C) 2013-2021 by the following authors:
26 - Rob Clark <robdclark@gmail.com> (robclark)
27 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28
29 Permission is hereby granted, free of charge, to any person obtaining
30 a copy of this software and associated documentation files (the
31 "Software"), to deal in the Software without restriction, including
32 without limitation the rights to use, copy, modify, merge, publish,
33 distribute, sublicense, and/or sell copies of the Software, and to
34 permit persons to whom the Software is furnished to do so, subject to
35 the following conditions:
36
37 The above copyright notice and this permission notice (including the
38 next paragraph) shall be included in all copies or substantial
39 portions of the Software.
40
41 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
42 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
43 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
44 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
45 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
46 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
47 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50
51 enum a5xx_color_fmt {
52 RB5_A8_UNORM = 2,
53 RB5_R8_UNORM = 3,
54 RB5_R8_SNORM = 4,
55 RB5_R8_UINT = 5,
56 RB5_R8_SINT = 6,
57 RB5_R4G4B4A4_UNORM = 8,
58 RB5_R5G5B5A1_UNORM = 10,
59 RB5_R5G6B5_UNORM = 14,
60 RB5_R8G8_UNORM = 15,
61 RB5_R8G8_SNORM = 16,
62 RB5_R8G8_UINT = 17,
63 RB5_R8G8_SINT = 18,
64 RB5_R16_UNORM = 21,
65 RB5_R16_SNORM = 22,
66 RB5_R16_FLOAT = 23,
67 RB5_R16_UINT = 24,
68 RB5_R16_SINT = 25,
69 RB5_R8G8B8A8_UNORM = 48,
70 RB5_R8G8B8_UNORM = 49,
71 RB5_R8G8B8A8_SNORM = 50,
72 RB5_R8G8B8A8_UINT = 51,
73 RB5_R8G8B8A8_SINT = 52,
74 RB5_R10G10B10A2_UNORM = 55,
75 RB5_R10G10B10A2_UINT = 58,
76 RB5_R11G11B10_FLOAT = 66,
77 RB5_R16G16_UNORM = 67,
78 RB5_R16G16_SNORM = 68,
79 RB5_R16G16_FLOAT = 69,
80 RB5_R16G16_UINT = 70,
81 RB5_R16G16_SINT = 71,
82 RB5_R32_FLOAT = 74,
83 RB5_R32_UINT = 75,
84 RB5_R32_SINT = 76,
85 RB5_R16G16B16A16_UNORM = 96,
86 RB5_R16G16B16A16_SNORM = 97,
87 RB5_R16G16B16A16_FLOAT = 98,
88 RB5_R16G16B16A16_UINT = 99,
89 RB5_R16G16B16A16_SINT = 100,
90 RB5_R32G32_FLOAT = 103,
91 RB5_R32G32_UINT = 104,
92 RB5_R32G32_SINT = 105,
93 RB5_R32G32B32A32_FLOAT = 130,
94 RB5_R32G32B32A32_UINT = 131,
95 RB5_R32G32B32A32_SINT = 132,
96 RB5_NONE = 255,
97 };
98
99 enum a5xx_tile_mode {
100 TILE5_LINEAR = 0,
101 TILE5_2 = 2,
102 TILE5_3 = 3,
103 };
104
105 enum a5xx_vtx_fmt {
106 VFMT5_8_UNORM = 3,
107 VFMT5_8_SNORM = 4,
108 VFMT5_8_UINT = 5,
109 VFMT5_8_SINT = 6,
110 VFMT5_8_8_UNORM = 15,
111 VFMT5_8_8_SNORM = 16,
112 VFMT5_8_8_UINT = 17,
113 VFMT5_8_8_SINT = 18,
114 VFMT5_16_UNORM = 21,
115 VFMT5_16_SNORM = 22,
116 VFMT5_16_FLOAT = 23,
117 VFMT5_16_UINT = 24,
118 VFMT5_16_SINT = 25,
119 VFMT5_8_8_8_UNORM = 33,
120 VFMT5_8_8_8_SNORM = 34,
121 VFMT5_8_8_8_UINT = 35,
122 VFMT5_8_8_8_SINT = 36,
123 VFMT5_8_8_8_8_UNORM = 48,
124 VFMT5_8_8_8_8_SNORM = 50,
125 VFMT5_8_8_8_8_UINT = 51,
126 VFMT5_8_8_8_8_SINT = 52,
127 VFMT5_10_10_10_2_UNORM = 54,
128 VFMT5_10_10_10_2_SNORM = 57,
129 VFMT5_10_10_10_2_UINT = 58,
130 VFMT5_10_10_10_2_SINT = 59,
131 VFMT5_11_11_10_FLOAT = 66,
132 VFMT5_16_16_UNORM = 67,
133 VFMT5_16_16_SNORM = 68,
134 VFMT5_16_16_FLOAT = 69,
135 VFMT5_16_16_UINT = 70,
136 VFMT5_16_16_SINT = 71,
137 VFMT5_32_UNORM = 72,
138 VFMT5_32_SNORM = 73,
139 VFMT5_32_FLOAT = 74,
140 VFMT5_32_UINT = 75,
141 VFMT5_32_SINT = 76,
142 VFMT5_32_FIXED = 77,
143 VFMT5_16_16_16_UNORM = 88,
144 VFMT5_16_16_16_SNORM = 89,
145 VFMT5_16_16_16_FLOAT = 90,
146 VFMT5_16_16_16_UINT = 91,
147 VFMT5_16_16_16_SINT = 92,
148 VFMT5_16_16_16_16_UNORM = 96,
149 VFMT5_16_16_16_16_SNORM = 97,
150 VFMT5_16_16_16_16_FLOAT = 98,
151 VFMT5_16_16_16_16_UINT = 99,
152 VFMT5_16_16_16_16_SINT = 100,
153 VFMT5_32_32_UNORM = 101,
154 VFMT5_32_32_SNORM = 102,
155 VFMT5_32_32_FLOAT = 103,
156 VFMT5_32_32_UINT = 104,
157 VFMT5_32_32_SINT = 105,
158 VFMT5_32_32_FIXED = 106,
159 VFMT5_32_32_32_UNORM = 112,
160 VFMT5_32_32_32_SNORM = 113,
161 VFMT5_32_32_32_UINT = 114,
162 VFMT5_32_32_32_SINT = 115,
163 VFMT5_32_32_32_FLOAT = 116,
164 VFMT5_32_32_32_FIXED = 117,
165 VFMT5_32_32_32_32_UNORM = 128,
166 VFMT5_32_32_32_32_SNORM = 129,
167 VFMT5_32_32_32_32_FLOAT = 130,
168 VFMT5_32_32_32_32_UINT = 131,
169 VFMT5_32_32_32_32_SINT = 132,
170 VFMT5_32_32_32_32_FIXED = 133,
171 VFMT5_NONE = 255,
172 };
173
174 enum a5xx_tex_fmt {
175 TFMT5_A8_UNORM = 2,
176 TFMT5_8_UNORM = 3,
177 TFMT5_8_SNORM = 4,
178 TFMT5_8_UINT = 5,
179 TFMT5_8_SINT = 6,
180 TFMT5_4_4_4_4_UNORM = 8,
181 TFMT5_5_5_5_1_UNORM = 10,
182 TFMT5_5_6_5_UNORM = 14,
183 TFMT5_8_8_UNORM = 15,
184 TFMT5_8_8_SNORM = 16,
185 TFMT5_8_8_UINT = 17,
186 TFMT5_8_8_SINT = 18,
187 TFMT5_L8_A8_UNORM = 19,
188 TFMT5_16_UNORM = 21,
189 TFMT5_16_SNORM = 22,
190 TFMT5_16_FLOAT = 23,
191 TFMT5_16_UINT = 24,
192 TFMT5_16_SINT = 25,
193 TFMT5_8_8_8_8_UNORM = 48,
194 TFMT5_8_8_8_UNORM = 49,
195 TFMT5_8_8_8_8_SNORM = 50,
196 TFMT5_8_8_8_8_UINT = 51,
197 TFMT5_8_8_8_8_SINT = 52,
198 TFMT5_9_9_9_E5_FLOAT = 53,
199 TFMT5_10_10_10_2_UNORM = 54,
200 TFMT5_10_10_10_2_UINT = 58,
201 TFMT5_11_11_10_FLOAT = 66,
202 TFMT5_16_16_UNORM = 67,
203 TFMT5_16_16_SNORM = 68,
204 TFMT5_16_16_FLOAT = 69,
205 TFMT5_16_16_UINT = 70,
206 TFMT5_16_16_SINT = 71,
207 TFMT5_32_FLOAT = 74,
208 TFMT5_32_UINT = 75,
209 TFMT5_32_SINT = 76,
210 TFMT5_16_16_16_16_UNORM = 96,
211 TFMT5_16_16_16_16_SNORM = 97,
212 TFMT5_16_16_16_16_FLOAT = 98,
213 TFMT5_16_16_16_16_UINT = 99,
214 TFMT5_16_16_16_16_SINT = 100,
215 TFMT5_32_32_FLOAT = 103,
216 TFMT5_32_32_UINT = 104,
217 TFMT5_32_32_SINT = 105,
218 TFMT5_32_32_32_UINT = 114,
219 TFMT5_32_32_32_SINT = 115,
220 TFMT5_32_32_32_FLOAT = 116,
221 TFMT5_32_32_32_32_FLOAT = 130,
222 TFMT5_32_32_32_32_UINT = 131,
223 TFMT5_32_32_32_32_SINT = 132,
224 TFMT5_X8Z24_UNORM = 160,
225 TFMT5_ETC2_RG11_UNORM = 171,
226 TFMT5_ETC2_RG11_SNORM = 172,
227 TFMT5_ETC2_R11_UNORM = 173,
228 TFMT5_ETC2_R11_SNORM = 174,
229 TFMT5_ETC1 = 175,
230 TFMT5_ETC2_RGB8 = 176,
231 TFMT5_ETC2_RGBA8 = 177,
232 TFMT5_ETC2_RGB8A1 = 178,
233 TFMT5_DXT1 = 179,
234 TFMT5_DXT3 = 180,
235 TFMT5_DXT5 = 181,
236 TFMT5_RGTC1_UNORM = 183,
237 TFMT5_RGTC1_SNORM = 184,
238 TFMT5_RGTC2_UNORM = 187,
239 TFMT5_RGTC2_SNORM = 188,
240 TFMT5_BPTC_UFLOAT = 190,
241 TFMT5_BPTC_FLOAT = 191,
242 TFMT5_BPTC = 192,
243 TFMT5_ASTC_4x4 = 193,
244 TFMT5_ASTC_5x4 = 194,
245 TFMT5_ASTC_5x5 = 195,
246 TFMT5_ASTC_6x5 = 196,
247 TFMT5_ASTC_6x6 = 197,
248 TFMT5_ASTC_8x5 = 198,
249 TFMT5_ASTC_8x6 = 199,
250 TFMT5_ASTC_8x8 = 200,
251 TFMT5_ASTC_10x5 = 201,
252 TFMT5_ASTC_10x6 = 202,
253 TFMT5_ASTC_10x8 = 203,
254 TFMT5_ASTC_10x10 = 204,
255 TFMT5_ASTC_12x10 = 205,
256 TFMT5_ASTC_12x12 = 206,
257 TFMT5_NONE = 255,
258 };
259
260 enum a5xx_depth_format {
261 DEPTH5_NONE = 0,
262 DEPTH5_16 = 1,
263 DEPTH5_24_8 = 2,
264 DEPTH5_32 = 4,
265 };
266
267 enum a5xx_blit_buf {
268 BLIT_MRT0 = 0,
269 BLIT_MRT1 = 1,
270 BLIT_MRT2 = 2,
271 BLIT_MRT3 = 3,
272 BLIT_MRT4 = 4,
273 BLIT_MRT5 = 5,
274 BLIT_MRT6 = 6,
275 BLIT_MRT7 = 7,
276 BLIT_ZS = 8,
277 BLIT_S = 9,
278 };
279
280 enum a5xx_cp_perfcounter_select {
281 PERF_CP_ALWAYS_COUNT = 0,
282 PERF_CP_BUSY_GFX_CORE_IDLE = 1,
283 PERF_CP_BUSY_CYCLES = 2,
284 PERF_CP_PFP_IDLE = 3,
285 PERF_CP_PFP_BUSY_WORKING = 4,
286 PERF_CP_PFP_STALL_CYCLES_ANY = 5,
287 PERF_CP_PFP_STARVE_CYCLES_ANY = 6,
288 PERF_CP_PFP_ICACHE_MISS = 7,
289 PERF_CP_PFP_ICACHE_HIT = 8,
290 PERF_CP_PFP_MATCH_PM4_PKT_PROFILE = 9,
291 PERF_CP_ME_BUSY_WORKING = 10,
292 PERF_CP_ME_IDLE = 11,
293 PERF_CP_ME_STARVE_CYCLES_ANY = 12,
294 PERF_CP_ME_FIFO_EMPTY_PFP_IDLE = 13,
295 PERF_CP_ME_FIFO_EMPTY_PFP_BUSY = 14,
296 PERF_CP_ME_FIFO_FULL_ME_BUSY = 15,
297 PERF_CP_ME_FIFO_FULL_ME_NON_WORKING = 16,
298 PERF_CP_ME_STALL_CYCLES_ANY = 17,
299 PERF_CP_ME_ICACHE_MISS = 18,
300 PERF_CP_ME_ICACHE_HIT = 19,
301 PERF_CP_NUM_PREEMPTIONS = 20,
302 PERF_CP_PREEMPTION_REACTION_DELAY = 21,
303 PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 22,
304 PERF_CP_PREEMPTION_SWITCH_IN_TIME = 23,
305 PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 24,
306 PERF_CP_PREDICATED_DRAWS_KILLED = 25,
307 PERF_CP_MODE_SWITCH = 26,
308 PERF_CP_ZPASS_DONE = 27,
309 PERF_CP_CONTEXT_DONE = 28,
310 PERF_CP_CACHE_FLUSH = 29,
311 PERF_CP_LONG_PREEMPTIONS = 30,
312 };
313
314 enum a5xx_rbbm_perfcounter_select {
315 PERF_RBBM_ALWAYS_COUNT = 0,
316 PERF_RBBM_ALWAYS_ON = 1,
317 PERF_RBBM_TSE_BUSY = 2,
318 PERF_RBBM_RAS_BUSY = 3,
319 PERF_RBBM_PC_DCALL_BUSY = 4,
320 PERF_RBBM_PC_VSD_BUSY = 5,
321 PERF_RBBM_STATUS_MASKED = 6,
322 PERF_RBBM_COM_BUSY = 7,
323 PERF_RBBM_DCOM_BUSY = 8,
324 PERF_RBBM_VBIF_BUSY = 9,
325 PERF_RBBM_VSC_BUSY = 10,
326 PERF_RBBM_TESS_BUSY = 11,
327 PERF_RBBM_UCHE_BUSY = 12,
328 PERF_RBBM_HLSQ_BUSY = 13,
329 };
330
331 enum a5xx_pc_perfcounter_select {
332 PERF_PC_BUSY_CYCLES = 0,
333 PERF_PC_WORKING_CYCLES = 1,
334 PERF_PC_STALL_CYCLES_VFD = 2,
335 PERF_PC_STALL_CYCLES_TSE = 3,
336 PERF_PC_STALL_CYCLES_VPC = 4,
337 PERF_PC_STALL_CYCLES_UCHE = 5,
338 PERF_PC_STALL_CYCLES_TESS = 6,
339 PERF_PC_STALL_CYCLES_TSE_ONLY = 7,
340 PERF_PC_STALL_CYCLES_VPC_ONLY = 8,
341 PERF_PC_PASS1_TF_STALL_CYCLES = 9,
342 PERF_PC_STARVE_CYCLES_FOR_INDEX = 10,
343 PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11,
344 PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12,
345 PERF_PC_STARVE_CYCLES_FOR_POSITION = 13,
346 PERF_PC_STARVE_CYCLES_DI = 14,
347 PERF_PC_VIS_STREAMS_LOADED = 15,
348 PERF_PC_INSTANCES = 16,
349 PERF_PC_VPC_PRIMITIVES = 17,
350 PERF_PC_DEAD_PRIM = 18,
351 PERF_PC_LIVE_PRIM = 19,
352 PERF_PC_VERTEX_HITS = 20,
353 PERF_PC_IA_VERTICES = 21,
354 PERF_PC_IA_PRIMITIVES = 22,
355 PERF_PC_GS_PRIMITIVES = 23,
356 PERF_PC_HS_INVOCATIONS = 24,
357 PERF_PC_DS_INVOCATIONS = 25,
358 PERF_PC_VS_INVOCATIONS = 26,
359 PERF_PC_GS_INVOCATIONS = 27,
360 PERF_PC_DS_PRIMITIVES = 28,
361 PERF_PC_VPC_POS_DATA_TRANSACTION = 29,
362 PERF_PC_3D_DRAWCALLS = 30,
363 PERF_PC_2D_DRAWCALLS = 31,
364 PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32,
365 PERF_TESS_BUSY_CYCLES = 33,
366 PERF_TESS_WORKING_CYCLES = 34,
367 PERF_TESS_STALL_CYCLES_PC = 35,
368 PERF_TESS_STARVE_CYCLES_PC = 36,
369 };
370
371 enum a5xx_vfd_perfcounter_select {
372 PERF_VFD_BUSY_CYCLES = 0,
373 PERF_VFD_STALL_CYCLES_UCHE = 1,
374 PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2,
375 PERF_VFD_STALL_CYCLES_MISS_VB = 3,
376 PERF_VFD_STALL_CYCLES_MISS_Q = 4,
377 PERF_VFD_STALL_CYCLES_SP_INFO = 5,
378 PERF_VFD_STALL_CYCLES_SP_ATTR = 6,
379 PERF_VFD_STALL_CYCLES_VFDP_VB = 7,
380 PERF_VFD_STALL_CYCLES_VFDP_Q = 8,
381 PERF_VFD_DECODER_PACKER_STALL = 9,
382 PERF_VFD_STARVE_CYCLES_UCHE = 10,
383 PERF_VFD_RBUFFER_FULL = 11,
384 PERF_VFD_ATTR_INFO_FIFO_FULL = 12,
385 PERF_VFD_DECODED_ATTRIBUTE_BYTES = 13,
386 PERF_VFD_NUM_ATTRIBUTES = 14,
387 PERF_VFD_INSTRUCTIONS = 15,
388 PERF_VFD_UPPER_SHADER_FIBERS = 16,
389 PERF_VFD_LOWER_SHADER_FIBERS = 17,
390 PERF_VFD_MODE_0_FIBERS = 18,
391 PERF_VFD_MODE_1_FIBERS = 19,
392 PERF_VFD_MODE_2_FIBERS = 20,
393 PERF_VFD_MODE_3_FIBERS = 21,
394 PERF_VFD_MODE_4_FIBERS = 22,
395 PERF_VFD_TOTAL_VERTICES = 23,
396 PERF_VFD_NUM_ATTR_MISS = 24,
397 PERF_VFD_1_BURST_REQ = 25,
398 PERF_VFDP_STALL_CYCLES_VFD = 26,
399 PERF_VFDP_STALL_CYCLES_VFD_INDEX = 27,
400 PERF_VFDP_STALL_CYCLES_VFD_PROG = 28,
401 PERF_VFDP_STARVE_CYCLES_PC = 29,
402 PERF_VFDP_VS_STAGE_32_WAVES = 30,
403 };
404
405 enum a5xx_hlsq_perfcounter_select {
406 PERF_HLSQ_BUSY_CYCLES = 0,
407 PERF_HLSQ_STALL_CYCLES_UCHE = 1,
408 PERF_HLSQ_STALL_CYCLES_SP_STATE = 2,
409 PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3,
410 PERF_HLSQ_UCHE_LATENCY_CYCLES = 4,
411 PERF_HLSQ_UCHE_LATENCY_COUNT = 5,
412 PERF_HLSQ_FS_STAGE_32_WAVES = 6,
413 PERF_HLSQ_FS_STAGE_64_WAVES = 7,
414 PERF_HLSQ_QUADS = 8,
415 PERF_HLSQ_SP_STATE_COPY_TRANS_FS_STAGE = 9,
416 PERF_HLSQ_SP_STATE_COPY_TRANS_VS_STAGE = 10,
417 PERF_HLSQ_TP_STATE_COPY_TRANS_FS_STAGE = 11,
418 PERF_HLSQ_TP_STATE_COPY_TRANS_VS_STAGE = 12,
419 PERF_HLSQ_CS_INVOCATIONS = 13,
420 PERF_HLSQ_COMPUTE_DRAWCALLS = 14,
421 };
422
423 enum a5xx_vpc_perfcounter_select {
424 PERF_VPC_BUSY_CYCLES = 0,
425 PERF_VPC_WORKING_CYCLES = 1,
426 PERF_VPC_STALL_CYCLES_UCHE = 2,
427 PERF_VPC_STALL_CYCLES_VFD_WACK = 3,
428 PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4,
429 PERF_VPC_STALL_CYCLES_PC = 5,
430 PERF_VPC_STALL_CYCLES_SP_LM = 6,
431 PERF_VPC_POS_EXPORT_STALL_CYCLES = 7,
432 PERF_VPC_STARVE_CYCLES_SP = 8,
433 PERF_VPC_STARVE_CYCLES_LRZ = 9,
434 PERF_VPC_PC_PRIMITIVES = 10,
435 PERF_VPC_SP_COMPONENTS = 11,
436 PERF_VPC_SP_LM_PRIMITIVES = 12,
437 PERF_VPC_SP_LM_COMPONENTS = 13,
438 PERF_VPC_SP_LM_DWORDS = 14,
439 PERF_VPC_STREAMOUT_COMPONENTS = 15,
440 PERF_VPC_GRANT_PHASES = 16,
441 };
442
443 enum a5xx_tse_perfcounter_select {
444 PERF_TSE_BUSY_CYCLES = 0,
445 PERF_TSE_CLIPPING_CYCLES = 1,
446 PERF_TSE_STALL_CYCLES_RAS = 2,
447 PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3,
448 PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4,
449 PERF_TSE_STARVE_CYCLES_PC = 5,
450 PERF_TSE_INPUT_PRIM = 6,
451 PERF_TSE_INPUT_NULL_PRIM = 7,
452 PERF_TSE_TRIVAL_REJ_PRIM = 8,
453 PERF_TSE_CLIPPED_PRIM = 9,
454 PERF_TSE_ZERO_AREA_PRIM = 10,
455 PERF_TSE_FACENESS_CULLED_PRIM = 11,
456 PERF_TSE_ZERO_PIXEL_PRIM = 12,
457 PERF_TSE_OUTPUT_NULL_PRIM = 13,
458 PERF_TSE_OUTPUT_VISIBLE_PRIM = 14,
459 PERF_TSE_CINVOCATION = 15,
460 PERF_TSE_CPRIMITIVES = 16,
461 PERF_TSE_2D_INPUT_PRIM = 17,
462 PERF_TSE_2D_ALIVE_CLCLES = 18,
463 };
464
465 enum a5xx_ras_perfcounter_select {
466 PERF_RAS_BUSY_CYCLES = 0,
467 PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1,
468 PERF_RAS_STALL_CYCLES_LRZ = 2,
469 PERF_RAS_STARVE_CYCLES_TSE = 3,
470 PERF_RAS_SUPER_TILES = 4,
471 PERF_RAS_8X4_TILES = 5,
472 PERF_RAS_MASKGEN_ACTIVE = 6,
473 PERF_RAS_FULLY_COVERED_SUPER_TILES = 7,
474 PERF_RAS_FULLY_COVERED_8X4_TILES = 8,
475 PERF_RAS_PRIM_KILLED_INVISILBE = 9,
476 };
477
478 enum a5xx_lrz_perfcounter_select {
479 PERF_LRZ_BUSY_CYCLES = 0,
480 PERF_LRZ_STARVE_CYCLES_RAS = 1,
481 PERF_LRZ_STALL_CYCLES_RB = 2,
482 PERF_LRZ_STALL_CYCLES_VSC = 3,
483 PERF_LRZ_STALL_CYCLES_VPC = 4,
484 PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5,
485 PERF_LRZ_STALL_CYCLES_UCHE = 6,
486 PERF_LRZ_LRZ_READ = 7,
487 PERF_LRZ_LRZ_WRITE = 8,
488 PERF_LRZ_READ_LATENCY = 9,
489 PERF_LRZ_MERGE_CACHE_UPDATING = 10,
490 PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11,
491 PERF_LRZ_PRIM_KILLED_BY_LRZ = 12,
492 PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13,
493 PERF_LRZ_FULL_8X8_TILES = 14,
494 PERF_LRZ_PARTIAL_8X8_TILES = 15,
495 PERF_LRZ_TILE_KILLED = 16,
496 PERF_LRZ_TOTAL_PIXEL = 17,
497 PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18,
498 };
499
500 enum a5xx_uche_perfcounter_select {
501 PERF_UCHE_BUSY_CYCLES = 0,
502 PERF_UCHE_STALL_CYCLES_VBIF = 1,
503 PERF_UCHE_VBIF_LATENCY_CYCLES = 2,
504 PERF_UCHE_VBIF_LATENCY_SAMPLES = 3,
505 PERF_UCHE_VBIF_READ_BEATS_TP = 4,
506 PERF_UCHE_VBIF_READ_BEATS_VFD = 5,
507 PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6,
508 PERF_UCHE_VBIF_READ_BEATS_LRZ = 7,
509 PERF_UCHE_VBIF_READ_BEATS_SP = 8,
510 PERF_UCHE_READ_REQUESTS_TP = 9,
511 PERF_UCHE_READ_REQUESTS_VFD = 10,
512 PERF_UCHE_READ_REQUESTS_HLSQ = 11,
513 PERF_UCHE_READ_REQUESTS_LRZ = 12,
514 PERF_UCHE_READ_REQUESTS_SP = 13,
515 PERF_UCHE_WRITE_REQUESTS_LRZ = 14,
516 PERF_UCHE_WRITE_REQUESTS_SP = 15,
517 PERF_UCHE_WRITE_REQUESTS_VPC = 16,
518 PERF_UCHE_WRITE_REQUESTS_VSC = 17,
519 PERF_UCHE_EVICTS = 18,
520 PERF_UCHE_BANK_REQ0 = 19,
521 PERF_UCHE_BANK_REQ1 = 20,
522 PERF_UCHE_BANK_REQ2 = 21,
523 PERF_UCHE_BANK_REQ3 = 22,
524 PERF_UCHE_BANK_REQ4 = 23,
525 PERF_UCHE_BANK_REQ5 = 24,
526 PERF_UCHE_BANK_REQ6 = 25,
527 PERF_UCHE_BANK_REQ7 = 26,
528 PERF_UCHE_VBIF_READ_BEATS_CH0 = 27,
529 PERF_UCHE_VBIF_READ_BEATS_CH1 = 28,
530 PERF_UCHE_GMEM_READ_BEATS = 29,
531 PERF_UCHE_FLAG_COUNT = 30,
532 };
533
534 enum a5xx_tp_perfcounter_select {
535 PERF_TP_BUSY_CYCLES = 0,
536 PERF_TP_STALL_CYCLES_UCHE = 1,
537 PERF_TP_LATENCY_CYCLES = 2,
538 PERF_TP_LATENCY_TRANS = 3,
539 PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4,
540 PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5,
541 PERF_TP_L1_CACHELINE_REQUESTS = 6,
542 PERF_TP_L1_CACHELINE_MISSES = 7,
543 PERF_TP_SP_TP_TRANS = 8,
544 PERF_TP_TP_SP_TRANS = 9,
545 PERF_TP_OUTPUT_PIXELS = 10,
546 PERF_TP_FILTER_WORKLOAD_16BIT = 11,
547 PERF_TP_FILTER_WORKLOAD_32BIT = 12,
548 PERF_TP_QUADS_RECEIVED = 13,
549 PERF_TP_QUADS_OFFSET = 14,
550 PERF_TP_QUADS_SHADOW = 15,
551 PERF_TP_QUADS_ARRAY = 16,
552 PERF_TP_QUADS_GRADIENT = 17,
553 PERF_TP_QUADS_1D = 18,
554 PERF_TP_QUADS_2D = 19,
555 PERF_TP_QUADS_BUFFER = 20,
556 PERF_TP_QUADS_3D = 21,
557 PERF_TP_QUADS_CUBE = 22,
558 PERF_TP_STATE_CACHE_REQUESTS = 23,
559 PERF_TP_STATE_CACHE_MISSES = 24,
560 PERF_TP_DIVERGENT_QUADS_RECEIVED = 25,
561 PERF_TP_BINDLESS_STATE_CACHE_REQUESTS = 26,
562 PERF_TP_BINDLESS_STATE_CACHE_MISSES = 27,
563 PERF_TP_PRT_NON_RESIDENT_EVENTS = 28,
564 PERF_TP_OUTPUT_PIXELS_POINT = 29,
565 PERF_TP_OUTPUT_PIXELS_BILINEAR = 30,
566 PERF_TP_OUTPUT_PIXELS_MIP = 31,
567 PERF_TP_OUTPUT_PIXELS_ANISO = 32,
568 PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 33,
569 PERF_TP_FLAG_CACHE_REQUESTS = 34,
570 PERF_TP_FLAG_CACHE_MISSES = 35,
571 PERF_TP_L1_5_L2_REQUESTS = 36,
572 PERF_TP_2D_OUTPUT_PIXELS = 37,
573 PERF_TP_2D_OUTPUT_PIXELS_POINT = 38,
574 PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 39,
575 PERF_TP_2D_FILTER_WORKLOAD_16BIT = 40,
576 PERF_TP_2D_FILTER_WORKLOAD_32BIT = 41,
577 };
578
579 enum a5xx_sp_perfcounter_select {
580 PERF_SP_BUSY_CYCLES = 0,
581 PERF_SP_ALU_WORKING_CYCLES = 1,
582 PERF_SP_EFU_WORKING_CYCLES = 2,
583 PERF_SP_STALL_CYCLES_VPC = 3,
584 PERF_SP_STALL_CYCLES_TP = 4,
585 PERF_SP_STALL_CYCLES_UCHE = 5,
586 PERF_SP_STALL_CYCLES_RB = 6,
587 PERF_SP_SCHEDULER_NON_WORKING = 7,
588 PERF_SP_WAVE_CONTEXTS = 8,
589 PERF_SP_WAVE_CONTEXT_CYCLES = 9,
590 PERF_SP_FS_STAGE_WAVE_CYCLES = 10,
591 PERF_SP_FS_STAGE_WAVE_SAMPLES = 11,
592 PERF_SP_VS_STAGE_WAVE_CYCLES = 12,
593 PERF_SP_VS_STAGE_WAVE_SAMPLES = 13,
594 PERF_SP_FS_STAGE_DURATION_CYCLES = 14,
595 PERF_SP_VS_STAGE_DURATION_CYCLES = 15,
596 PERF_SP_WAVE_CTRL_CYCLES = 16,
597 PERF_SP_WAVE_LOAD_CYCLES = 17,
598 PERF_SP_WAVE_EMIT_CYCLES = 18,
599 PERF_SP_WAVE_NOP_CYCLES = 19,
600 PERF_SP_WAVE_WAIT_CYCLES = 20,
601 PERF_SP_WAVE_FETCH_CYCLES = 21,
602 PERF_SP_WAVE_IDLE_CYCLES = 22,
603 PERF_SP_WAVE_END_CYCLES = 23,
604 PERF_SP_WAVE_LONG_SYNC_CYCLES = 24,
605 PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25,
606 PERF_SP_WAVE_JOIN_CYCLES = 26,
607 PERF_SP_LM_LOAD_INSTRUCTIONS = 27,
608 PERF_SP_LM_STORE_INSTRUCTIONS = 28,
609 PERF_SP_LM_ATOMICS = 29,
610 PERF_SP_GM_LOAD_INSTRUCTIONS = 30,
611 PERF_SP_GM_STORE_INSTRUCTIONS = 31,
612 PERF_SP_GM_ATOMICS = 32,
613 PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33,
614 PERF_SP_VS_STAGE_CFLOW_INSTRUCTIONS = 34,
615 PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 35,
616 PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 36,
617 PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 37,
618 PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 38,
619 PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 39,
620 PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 40,
621 PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 41,
622 PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 42,
623 PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 43,
624 PERF_SP_VS_INSTRUCTIONS = 44,
625 PERF_SP_FS_INSTRUCTIONS = 45,
626 PERF_SP_ADDR_LOCK_COUNT = 46,
627 PERF_SP_UCHE_READ_TRANS = 47,
628 PERF_SP_UCHE_WRITE_TRANS = 48,
629 PERF_SP_EXPORT_VPC_TRANS = 49,
630 PERF_SP_EXPORT_RB_TRANS = 50,
631 PERF_SP_PIXELS_KILLED = 51,
632 PERF_SP_ICL1_REQUESTS = 52,
633 PERF_SP_ICL1_MISSES = 53,
634 PERF_SP_ICL0_REQUESTS = 54,
635 PERF_SP_ICL0_MISSES = 55,
636 PERF_SP_HS_INSTRUCTIONS = 56,
637 PERF_SP_DS_INSTRUCTIONS = 57,
638 PERF_SP_GS_INSTRUCTIONS = 58,
639 PERF_SP_CS_INSTRUCTIONS = 59,
640 PERF_SP_GPR_READ = 60,
641 PERF_SP_GPR_WRITE = 61,
642 PERF_SP_LM_CH0_REQUESTS = 62,
643 PERF_SP_LM_CH1_REQUESTS = 63,
644 PERF_SP_LM_BANK_CONFLICTS = 64,
645 };
646
647 enum a5xx_rb_perfcounter_select {
648 PERF_RB_BUSY_CYCLES = 0,
649 PERF_RB_STALL_CYCLES_CCU = 1,
650 PERF_RB_STALL_CYCLES_HLSQ = 2,
651 PERF_RB_STALL_CYCLES_FIFO0_FULL = 3,
652 PERF_RB_STALL_CYCLES_FIFO1_FULL = 4,
653 PERF_RB_STALL_CYCLES_FIFO2_FULL = 5,
654 PERF_RB_STARVE_CYCLES_SP = 6,
655 PERF_RB_STARVE_CYCLES_LRZ_TILE = 7,
656 PERF_RB_STARVE_CYCLES_CCU = 8,
657 PERF_RB_STARVE_CYCLES_Z_PLANE = 9,
658 PERF_RB_STARVE_CYCLES_BARY_PLANE = 10,
659 PERF_RB_Z_WORKLOAD = 11,
660 PERF_RB_HLSQ_ACTIVE = 12,
661 PERF_RB_Z_READ = 13,
662 PERF_RB_Z_WRITE = 14,
663 PERF_RB_C_READ = 15,
664 PERF_RB_C_WRITE = 16,
665 PERF_RB_TOTAL_PASS = 17,
666 PERF_RB_Z_PASS = 18,
667 PERF_RB_Z_FAIL = 19,
668 PERF_RB_S_FAIL = 20,
669 PERF_RB_BLENDED_FXP_COMPONENTS = 21,
670 PERF_RB_BLENDED_FP16_COMPONENTS = 22,
671 RB_RESERVED = 23,
672 PERF_RB_2D_ALIVE_CYCLES = 24,
673 PERF_RB_2D_STALL_CYCLES_A2D = 25,
674 PERF_RB_2D_STARVE_CYCLES_SRC = 26,
675 PERF_RB_2D_STARVE_CYCLES_SP = 27,
676 PERF_RB_2D_STARVE_CYCLES_DST = 28,
677 PERF_RB_2D_VALID_PIXELS = 29,
678 };
679
680 enum a5xx_rb_samples_perfcounter_select {
681 TOTAL_SAMPLES = 0,
682 ZPASS_SAMPLES = 1,
683 ZFAIL_SAMPLES = 2,
684 SFAIL_SAMPLES = 3,
685 };
686
687 enum a5xx_vsc_perfcounter_select {
688 PERF_VSC_BUSY_CYCLES = 0,
689 PERF_VSC_WORKING_CYCLES = 1,
690 PERF_VSC_STALL_CYCLES_UCHE = 2,
691 PERF_VSC_EOT_NUM = 3,
692 };
693
694 enum a5xx_ccu_perfcounter_select {
695 PERF_CCU_BUSY_CYCLES = 0,
696 PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1,
697 PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2,
698 PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3,
699 PERF_CCU_DEPTH_BLOCKS = 4,
700 PERF_CCU_COLOR_BLOCKS = 5,
701 PERF_CCU_DEPTH_BLOCK_HIT = 6,
702 PERF_CCU_COLOR_BLOCK_HIT = 7,
703 PERF_CCU_PARTIAL_BLOCK_READ = 8,
704 PERF_CCU_GMEM_READ = 9,
705 PERF_CCU_GMEM_WRITE = 10,
706 PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11,
707 PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12,
708 PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13,
709 PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14,
710 PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15,
711 PERF_CCU_COLOR_READ_FLAG0_COUNT = 16,
712 PERF_CCU_COLOR_READ_FLAG1_COUNT = 17,
713 PERF_CCU_COLOR_READ_FLAG2_COUNT = 18,
714 PERF_CCU_COLOR_READ_FLAG3_COUNT = 19,
715 PERF_CCU_COLOR_READ_FLAG4_COUNT = 20,
716 PERF_CCU_2D_BUSY_CYCLES = 21,
717 PERF_CCU_2D_RD_REQ = 22,
718 PERF_CCU_2D_WR_REQ = 23,
719 PERF_CCU_2D_REORDER_STARVE_CYCLES = 24,
720 PERF_CCU_2D_PIXELS = 25,
721 };
722
723 enum a5xx_cmp_perfcounter_select {
724 PERF_CMPDECMP_STALL_CYCLES_VBIF = 0,
725 PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1,
726 PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2,
727 PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3,
728 PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4,
729 PERF_CMPDECMP_VBIF_READ_REQUEST = 5,
730 PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6,
731 PERF_CMPDECMP_VBIF_READ_DATA = 7,
732 PERF_CMPDECMP_VBIF_WRITE_DATA = 8,
733 PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9,
734 PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10,
735 PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11,
736 PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12,
737 PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13,
738 PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14,
739 PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 15,
740 PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 16,
741 PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 17,
742 PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 18,
743 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 19,
744 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 20,
745 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 21,
746 PERF_CMPDECMP_2D_RD_DATA = 22,
747 PERF_CMPDECMP_2D_WR_DATA = 23,
748 };
749
750 enum a5xx_vbif_perfcounter_select {
751 AXI_READ_REQUESTS_ID_0 = 0,
752 AXI_READ_REQUESTS_ID_1 = 1,
753 AXI_READ_REQUESTS_ID_2 = 2,
754 AXI_READ_REQUESTS_ID_3 = 3,
755 AXI_READ_REQUESTS_ID_4 = 4,
756 AXI_READ_REQUESTS_ID_5 = 5,
757 AXI_READ_REQUESTS_ID_6 = 6,
758 AXI_READ_REQUESTS_ID_7 = 7,
759 AXI_READ_REQUESTS_ID_8 = 8,
760 AXI_READ_REQUESTS_ID_9 = 9,
761 AXI_READ_REQUESTS_ID_10 = 10,
762 AXI_READ_REQUESTS_ID_11 = 11,
763 AXI_READ_REQUESTS_ID_12 = 12,
764 AXI_READ_REQUESTS_ID_13 = 13,
765 AXI_READ_REQUESTS_ID_14 = 14,
766 AXI_READ_REQUESTS_ID_15 = 15,
767 AXI0_READ_REQUESTS_TOTAL = 16,
768 AXI1_READ_REQUESTS_TOTAL = 17,
769 AXI2_READ_REQUESTS_TOTAL = 18,
770 AXI3_READ_REQUESTS_TOTAL = 19,
771 AXI_READ_REQUESTS_TOTAL = 20,
772 AXI_WRITE_REQUESTS_ID_0 = 21,
773 AXI_WRITE_REQUESTS_ID_1 = 22,
774 AXI_WRITE_REQUESTS_ID_2 = 23,
775 AXI_WRITE_REQUESTS_ID_3 = 24,
776 AXI_WRITE_REQUESTS_ID_4 = 25,
777 AXI_WRITE_REQUESTS_ID_5 = 26,
778 AXI_WRITE_REQUESTS_ID_6 = 27,
779 AXI_WRITE_REQUESTS_ID_7 = 28,
780 AXI_WRITE_REQUESTS_ID_8 = 29,
781 AXI_WRITE_REQUESTS_ID_9 = 30,
782 AXI_WRITE_REQUESTS_ID_10 = 31,
783 AXI_WRITE_REQUESTS_ID_11 = 32,
784 AXI_WRITE_REQUESTS_ID_12 = 33,
785 AXI_WRITE_REQUESTS_ID_13 = 34,
786 AXI_WRITE_REQUESTS_ID_14 = 35,
787 AXI_WRITE_REQUESTS_ID_15 = 36,
788 AXI0_WRITE_REQUESTS_TOTAL = 37,
789 AXI1_WRITE_REQUESTS_TOTAL = 38,
790 AXI2_WRITE_REQUESTS_TOTAL = 39,
791 AXI3_WRITE_REQUESTS_TOTAL = 40,
792 AXI_WRITE_REQUESTS_TOTAL = 41,
793 AXI_TOTAL_REQUESTS = 42,
794 AXI_READ_DATA_BEATS_ID_0 = 43,
795 AXI_READ_DATA_BEATS_ID_1 = 44,
796 AXI_READ_DATA_BEATS_ID_2 = 45,
797 AXI_READ_DATA_BEATS_ID_3 = 46,
798 AXI_READ_DATA_BEATS_ID_4 = 47,
799 AXI_READ_DATA_BEATS_ID_5 = 48,
800 AXI_READ_DATA_BEATS_ID_6 = 49,
801 AXI_READ_DATA_BEATS_ID_7 = 50,
802 AXI_READ_DATA_BEATS_ID_8 = 51,
803 AXI_READ_DATA_BEATS_ID_9 = 52,
804 AXI_READ_DATA_BEATS_ID_10 = 53,
805 AXI_READ_DATA_BEATS_ID_11 = 54,
806 AXI_READ_DATA_BEATS_ID_12 = 55,
807 AXI_READ_DATA_BEATS_ID_13 = 56,
808 AXI_READ_DATA_BEATS_ID_14 = 57,
809 AXI_READ_DATA_BEATS_ID_15 = 58,
810 AXI0_READ_DATA_BEATS_TOTAL = 59,
811 AXI1_READ_DATA_BEATS_TOTAL = 60,
812 AXI2_READ_DATA_BEATS_TOTAL = 61,
813 AXI3_READ_DATA_BEATS_TOTAL = 62,
814 AXI_READ_DATA_BEATS_TOTAL = 63,
815 AXI_WRITE_DATA_BEATS_ID_0 = 64,
816 AXI_WRITE_DATA_BEATS_ID_1 = 65,
817 AXI_WRITE_DATA_BEATS_ID_2 = 66,
818 AXI_WRITE_DATA_BEATS_ID_3 = 67,
819 AXI_WRITE_DATA_BEATS_ID_4 = 68,
820 AXI_WRITE_DATA_BEATS_ID_5 = 69,
821 AXI_WRITE_DATA_BEATS_ID_6 = 70,
822 AXI_WRITE_DATA_BEATS_ID_7 = 71,
823 AXI_WRITE_DATA_BEATS_ID_8 = 72,
824 AXI_WRITE_DATA_BEATS_ID_9 = 73,
825 AXI_WRITE_DATA_BEATS_ID_10 = 74,
826 AXI_WRITE_DATA_BEATS_ID_11 = 75,
827 AXI_WRITE_DATA_BEATS_ID_12 = 76,
828 AXI_WRITE_DATA_BEATS_ID_13 = 77,
829 AXI_WRITE_DATA_BEATS_ID_14 = 78,
830 AXI_WRITE_DATA_BEATS_ID_15 = 79,
831 AXI0_WRITE_DATA_BEATS_TOTAL = 80,
832 AXI1_WRITE_DATA_BEATS_TOTAL = 81,
833 AXI2_WRITE_DATA_BEATS_TOTAL = 82,
834 AXI3_WRITE_DATA_BEATS_TOTAL = 83,
835 AXI_WRITE_DATA_BEATS_TOTAL = 84,
836 AXI_DATA_BEATS_TOTAL = 85,
837 };
838
839 enum a5xx_tex_filter {
840 A5XX_TEX_NEAREST = 0,
841 A5XX_TEX_LINEAR = 1,
842 A5XX_TEX_ANISO = 2,
843 };
844
845 enum a5xx_tex_clamp {
846 A5XX_TEX_REPEAT = 0,
847 A5XX_TEX_CLAMP_TO_EDGE = 1,
848 A5XX_TEX_MIRROR_REPEAT = 2,
849 A5XX_TEX_CLAMP_TO_BORDER = 3,
850 A5XX_TEX_MIRROR_CLAMP = 4,
851 };
852
853 enum a5xx_tex_aniso {
854 A5XX_TEX_ANISO_1 = 0,
855 A5XX_TEX_ANISO_2 = 1,
856 A5XX_TEX_ANISO_4 = 2,
857 A5XX_TEX_ANISO_8 = 3,
858 A5XX_TEX_ANISO_16 = 4,
859 };
860
861 enum a5xx_tex_swiz {
862 A5XX_TEX_X = 0,
863 A5XX_TEX_Y = 1,
864 A5XX_TEX_Z = 2,
865 A5XX_TEX_W = 3,
866 A5XX_TEX_ZERO = 4,
867 A5XX_TEX_ONE = 5,
868 };
869
870 enum a5xx_tex_type {
871 A5XX_TEX_1D = 0,
872 A5XX_TEX_2D = 1,
873 A5XX_TEX_CUBE = 2,
874 A5XX_TEX_3D = 3,
875 };
876
877 #define A5XX_INT0_RBBM_GPU_IDLE 0x00000001
878 #define A5XX_INT0_RBBM_AHB_ERROR 0x00000002
879 #define A5XX_INT0_RBBM_TRANSFER_TIMEOUT 0x00000004
880 #define A5XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
881 #define A5XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
882 #define A5XX_INT0_RBBM_ETS_MS_TIMEOUT 0x00000020
883 #define A5XX_INT0_RBBM_ATB_ASYNC_OVERFLOW 0x00000040
884 #define A5XX_INT0_RBBM_GPC_ERROR 0x00000080
885 #define A5XX_INT0_CP_SW 0x00000100
886 #define A5XX_INT0_CP_HW_ERROR 0x00000200
887 #define A5XX_INT0_CP_CCU_FLUSH_DEPTH_TS 0x00000400
888 #define A5XX_INT0_CP_CCU_FLUSH_COLOR_TS 0x00000800
889 #define A5XX_INT0_CP_CCU_RESOLVE_TS 0x00001000
890 #define A5XX_INT0_CP_IB2 0x00002000
891 #define A5XX_INT0_CP_IB1 0x00004000
892 #define A5XX_INT0_CP_RB 0x00008000
893 #define A5XX_INT0_CP_UNUSED_1 0x00010000
894 #define A5XX_INT0_CP_RB_DONE_TS 0x00020000
895 #define A5XX_INT0_CP_WT_DONE_TS 0x00040000
896 #define A5XX_INT0_UNKNOWN_1 0x00080000
897 #define A5XX_INT0_CP_CACHE_FLUSH_TS 0x00100000
898 #define A5XX_INT0_UNUSED_2 0x00200000
899 #define A5XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00400000
900 #define A5XX_INT0_MISC_HANG_DETECT 0x00800000
901 #define A5XX_INT0_UCHE_OOB_ACCESS 0x01000000
902 #define A5XX_INT0_UCHE_TRAP_INTR 0x02000000
903 #define A5XX_INT0_DEBBUS_INTR_0 0x04000000
904 #define A5XX_INT0_DEBBUS_INTR_1 0x08000000
905 #define A5XX_INT0_GPMU_VOLTAGE_DROOP 0x10000000
906 #define A5XX_INT0_GPMU_FIRMWARE 0x20000000
907 #define A5XX_INT0_ISDB_CPU_IRQ 0x40000000
908 #define A5XX_INT0_ISDB_UNDER_DEBUG 0x80000000
909 #define A5XX_CP_INT_CP_OPCODE_ERROR 0x00000001
910 #define A5XX_CP_INT_CP_RESERVED_BIT_ERROR 0x00000002
911 #define A5XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004
912 #define A5XX_CP_INT_CP_DMA_ERROR 0x00000008
913 #define A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010
914 #define A5XX_CP_INT_CP_AHB_ERROR 0x00000020
915 #define REG_A5XX_CP_RB_BASE 0x00000800
916
917 #define REG_A5XX_CP_RB_BASE_HI 0x00000801
918
919 #define REG_A5XX_CP_RB_CNTL 0x00000802
920
921 #define REG_A5XX_CP_RB_RPTR_ADDR 0x00000804
922
923 #define REG_A5XX_CP_RB_RPTR_ADDR_HI 0x00000805
924
925 #define REG_A5XX_CP_RB_RPTR 0x00000806
926
927 #define REG_A5XX_CP_RB_WPTR 0x00000807
928
929 #define REG_A5XX_CP_PFP_STAT_ADDR 0x00000808
930
931 #define REG_A5XX_CP_PFP_STAT_DATA 0x00000809
932
933 #define REG_A5XX_CP_DRAW_STATE_ADDR 0x0000080b
934
935 #define REG_A5XX_CP_DRAW_STATE_DATA 0x0000080c
936
937 #define REG_A5XX_CP_ME_NRT_ADDR_LO 0x0000080d
938
939 #define REG_A5XX_CP_ME_NRT_ADDR_HI 0x0000080e
940
941 #define REG_A5XX_CP_ME_NRT_DATA 0x00000810
942
943 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_LO 0x00000817
944
945 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_HI 0x00000818
946
947 #define REG_A5XX_CP_CRASH_DUMP_CNTL 0x00000819
948
949 #define REG_A5XX_CP_ME_STAT_ADDR 0x0000081a
950
951 #define REG_A5XX_CP_ROQ_THRESHOLDS_1 0x0000081f
952
953 #define REG_A5XX_CP_ROQ_THRESHOLDS_2 0x00000820
954
955 #define REG_A5XX_CP_ROQ_DBG_ADDR 0x00000821
956
957 #define REG_A5XX_CP_ROQ_DBG_DATA 0x00000822
958
959 #define REG_A5XX_CP_MEQ_DBG_ADDR 0x00000823
960
961 #define REG_A5XX_CP_MEQ_DBG_DATA 0x00000824
962
963 #define REG_A5XX_CP_MEQ_THRESHOLDS 0x00000825
964
965 #define REG_A5XX_CP_MERCIU_SIZE 0x00000826
966
967 #define REG_A5XX_CP_MERCIU_DBG_ADDR 0x00000827
968
969 #define REG_A5XX_CP_MERCIU_DBG_DATA_1 0x00000828
970
971 #define REG_A5XX_CP_MERCIU_DBG_DATA_2 0x00000829
972
973 #define REG_A5XX_CP_PFP_UCODE_DBG_ADDR 0x0000082a
974
975 #define REG_A5XX_CP_PFP_UCODE_DBG_DATA 0x0000082b
976
977 #define REG_A5XX_CP_ME_UCODE_DBG_ADDR 0x0000082f
978
979 #define REG_A5XX_CP_ME_UCODE_DBG_DATA 0x00000830
980
981 #define REG_A5XX_CP_CNTL 0x00000831
982
983 #define REG_A5XX_CP_PFP_ME_CNTL 0x00000832
984
985 #define REG_A5XX_CP_CHICKEN_DBG 0x00000833
986
987 #define REG_A5XX_CP_PFP_INSTR_BASE_LO 0x00000835
988
989 #define REG_A5XX_CP_PFP_INSTR_BASE_HI 0x00000836
990
991 #define REG_A5XX_CP_ME_INSTR_BASE_LO 0x00000838
992
993 #define REG_A5XX_CP_ME_INSTR_BASE_HI 0x00000839
994
995 #define REG_A5XX_CP_CONTEXT_SWITCH_CNTL 0x0000083b
996
997 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO 0x0000083c
998
999 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI 0x0000083d
1000
1001 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO 0x0000083e
1002
1003 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI 0x0000083f
1004
1005 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x00000840
1006
1007 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x00000841
1008
1009 #define REG_A5XX_CP_ADDR_MODE_CNTL 0x00000860
1010
1011 #define REG_A5XX_CP_ME_STAT_DATA 0x00000b14
1012
1013 #define REG_A5XX_CP_WFI_PEND_CTR 0x00000b15
1014
1015 #define REG_A5XX_CP_INTERRUPT_STATUS 0x00000b18
1016
1017 #define REG_A5XX_CP_HW_FAULT 0x00000b1a
1018
1019 #define REG_A5XX_CP_PROTECT_STATUS 0x00000b1c
1020
1021 #define REG_A5XX_CP_IB1_BASE 0x00000b1f
1022
1023 #define REG_A5XX_CP_IB1_BASE_HI 0x00000b20
1024
1025 #define REG_A5XX_CP_IB1_BUFSZ 0x00000b21
1026
1027 #define REG_A5XX_CP_IB2_BASE 0x00000b22
1028
1029 #define REG_A5XX_CP_IB2_BASE_HI 0x00000b23
1030
1031 #define REG_A5XX_CP_IB2_BUFSZ 0x00000b24
1032
REG_A5XX_CP_SCRATCH(uint32_t i0)1033 static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; }
1034
REG_A5XX_CP_SCRATCH_REG(uint32_t i0)1035 static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; }
1036
REG_A5XX_CP_PROTECT(uint32_t i0)1037 static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; }
1038
REG_A5XX_CP_PROTECT_REG(uint32_t i0)1039 static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; }
1040 #define A5XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff
1041 #define A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)1042 static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
1043 {
1044 return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK;
1045 }
1046 #define A5XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000
1047 #define A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24
A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)1048 static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
1049 {
1050 return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK;
1051 }
1052 #define A5XX_CP_PROTECT_REG_TRAP_WRITE__MASK 0x20000000
1053 #define A5XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT 29
A5XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val)1054 static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val)
1055 {
1056 return ((val) << A5XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_WRITE__MASK;
1057 }
1058 #define A5XX_CP_PROTECT_REG_TRAP_READ__MASK 0x40000000
1059 #define A5XX_CP_PROTECT_REG_TRAP_READ__SHIFT 30
A5XX_CP_PROTECT_REG_TRAP_READ(uint32_t val)1060 static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_READ(uint32_t val)
1061 {
1062 return ((val) << A5XX_CP_PROTECT_REG_TRAP_READ__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_READ__MASK;
1063 }
1064
1065 #define REG_A5XX_CP_PROTECT_CNTL 0x000008a0
1066
1067 #define REG_A5XX_CP_AHB_FAULT 0x00000b1b
1068
1069 #define REG_A5XX_CP_PERFCTR_CP_SEL_0 0x00000bb0
1070
1071 #define REG_A5XX_CP_PERFCTR_CP_SEL_1 0x00000bb1
1072
1073 #define REG_A5XX_CP_PERFCTR_CP_SEL_2 0x00000bb2
1074
1075 #define REG_A5XX_CP_PERFCTR_CP_SEL_3 0x00000bb3
1076
1077 #define REG_A5XX_CP_PERFCTR_CP_SEL_4 0x00000bb4
1078
1079 #define REG_A5XX_CP_PERFCTR_CP_SEL_5 0x00000bb5
1080
1081 #define REG_A5XX_CP_PERFCTR_CP_SEL_6 0x00000bb6
1082
1083 #define REG_A5XX_CP_PERFCTR_CP_SEL_7 0x00000bb7
1084
1085 #define REG_A5XX_VSC_ADDR_MODE_CNTL 0x00000bc1
1086
1087 #define REG_A5XX_CP_POWERCTR_CP_SEL_0 0x00000bba
1088
1089 #define REG_A5XX_CP_POWERCTR_CP_SEL_1 0x00000bbb
1090
1091 #define REG_A5XX_CP_POWERCTR_CP_SEL_2 0x00000bbc
1092
1093 #define REG_A5XX_CP_POWERCTR_CP_SEL_3 0x00000bbd
1094
1095 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_A 0x00000004
1096
1097 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_B 0x00000005
1098
1099 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_C 0x00000006
1100
1101 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_D 0x00000007
1102
1103 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLT 0x00000008
1104
1105 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLM 0x00000009
1106
1107 #define REG_A5XX_RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT 0x00000018
1108
1109 #define REG_A5XX_RBBM_CFG_DBGBUS_OPL 0x0000000a
1110
1111 #define REG_A5XX_RBBM_CFG_DBGBUS_OPE 0x0000000b
1112
1113 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_0 0x0000000c
1114
1115 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_1 0x0000000d
1116
1117 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_2 0x0000000e
1118
1119 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_3 0x0000000f
1120
1121 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_0 0x00000010
1122
1123 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_1 0x00000011
1124
1125 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_2 0x00000012
1126
1127 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_3 0x00000013
1128
1129 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_0 0x00000014
1130
1131 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_1 0x00000015
1132
1133 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_0 0x00000016
1134
1135 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_1 0x00000017
1136
1137 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_2 0x00000018
1138
1139 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_3 0x00000019
1140
1141 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_0 0x0000001a
1142
1143 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_1 0x0000001b
1144
1145 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_2 0x0000001c
1146
1147 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_3 0x0000001d
1148
1149 #define REG_A5XX_RBBM_CFG_DBGBUS_NIBBLEE 0x0000001e
1150
1151 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC0 0x0000001f
1152
1153 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC1 0x00000020
1154
1155 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADREG 0x00000021
1156
1157 #define REG_A5XX_RBBM_CFG_DBGBUS_IDX 0x00000022
1158
1159 #define REG_A5XX_RBBM_CFG_DBGBUS_CLRC 0x00000023
1160
1161 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADIVT 0x00000024
1162
1163 #define REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000002f
1164
1165 #define REG_A5XX_RBBM_INT_CLEAR_CMD 0x00000037
1166
1167 #define REG_A5XX_RBBM_INT_0_MASK 0x00000038
1168 #define A5XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001
1169 #define A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR 0x00000002
1170 #define A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT 0x00000004
1171 #define A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT 0x00000008
1172 #define A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT 0x00000010
1173 #define A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT 0x00000020
1174 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW 0x00000040
1175 #define A5XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080
1176 #define A5XX_RBBM_INT_0_MASK_CP_SW 0x00000100
1177 #define A5XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200
1178 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400
1179 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800
1180 #define A5XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000
1181 #define A5XX_RBBM_INT_0_MASK_CP_IB2 0x00002000
1182 #define A5XX_RBBM_INT_0_MASK_CP_IB1 0x00004000
1183 #define A5XX_RBBM_INT_0_MASK_CP_RB 0x00008000
1184 #define A5XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000
1185 #define A5XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000
1186 #define A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000
1187 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000
1188 #define A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT 0x00800000
1189 #define A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000
1190 #define A5XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000
1191 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000
1192 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000
1193 #define A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP 0x10000000
1194 #define A5XX_RBBM_INT_0_MASK_GPMU_FIRMWARE 0x20000000
1195 #define A5XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000
1196 #define A5XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000
1197
1198 #define REG_A5XX_RBBM_AHB_DBG_CNTL 0x0000003f
1199
1200 #define REG_A5XX_RBBM_EXT_VBIF_DBG_CNTL 0x00000041
1201
1202 #define REG_A5XX_RBBM_SW_RESET_CMD 0x00000043
1203
1204 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
1205
1206 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046
1207
1208 #define REG_A5XX_RBBM_DBG_LO_HI_GPIO 0x00000048
1209
1210 #define REG_A5XX_RBBM_EXT_TRACE_BUS_CNTL 0x00000049
1211
1212 #define REG_A5XX_RBBM_CLOCK_CNTL_TP0 0x0000004a
1213
1214 #define REG_A5XX_RBBM_CLOCK_CNTL_TP1 0x0000004b
1215
1216 #define REG_A5XX_RBBM_CLOCK_CNTL_TP2 0x0000004c
1217
1218 #define REG_A5XX_RBBM_CLOCK_CNTL_TP3 0x0000004d
1219
1220 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP0 0x0000004e
1221
1222 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP1 0x0000004f
1223
1224 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP2 0x00000050
1225
1226 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP3 0x00000051
1227
1228 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP0 0x00000052
1229
1230 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP1 0x00000053
1231
1232 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP2 0x00000054
1233
1234 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP3 0x00000055
1235
1236 #define REG_A5XX_RBBM_READ_AHB_THROUGH_DBG 0x00000059
1237
1238 #define REG_A5XX_RBBM_CLOCK_CNTL_UCHE 0x0000005a
1239
1240 #define REG_A5XX_RBBM_CLOCK_CNTL2_UCHE 0x0000005b
1241
1242 #define REG_A5XX_RBBM_CLOCK_CNTL3_UCHE 0x0000005c
1243
1244 #define REG_A5XX_RBBM_CLOCK_CNTL4_UCHE 0x0000005d
1245
1246 #define REG_A5XX_RBBM_CLOCK_HYST_UCHE 0x0000005e
1247
1248 #define REG_A5XX_RBBM_CLOCK_DELAY_UCHE 0x0000005f
1249
1250 #define REG_A5XX_RBBM_CLOCK_MODE_GPC 0x00000060
1251
1252 #define REG_A5XX_RBBM_CLOCK_DELAY_GPC 0x00000061
1253
1254 #define REG_A5XX_RBBM_CLOCK_HYST_GPC 0x00000062
1255
1256 #define REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000063
1257
1258 #define REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x00000064
1259
1260 #define REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000065
1261
1262 #define REG_A5XX_RBBM_CLOCK_DELAY_HLSQ 0x00000066
1263
1264 #define REG_A5XX_RBBM_CLOCK_CNTL 0x00000067
1265
1266 #define REG_A5XX_RBBM_CLOCK_CNTL_SP0 0x00000068
1267
1268 #define REG_A5XX_RBBM_CLOCK_CNTL_SP1 0x00000069
1269
1270 #define REG_A5XX_RBBM_CLOCK_CNTL_SP2 0x0000006a
1271
1272 #define REG_A5XX_RBBM_CLOCK_CNTL_SP3 0x0000006b
1273
1274 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP0 0x0000006c
1275
1276 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP1 0x0000006d
1277
1278 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP2 0x0000006e
1279
1280 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP3 0x0000006f
1281
1282 #define REG_A5XX_RBBM_CLOCK_HYST_SP0 0x00000070
1283
1284 #define REG_A5XX_RBBM_CLOCK_HYST_SP1 0x00000071
1285
1286 #define REG_A5XX_RBBM_CLOCK_HYST_SP2 0x00000072
1287
1288 #define REG_A5XX_RBBM_CLOCK_HYST_SP3 0x00000073
1289
1290 #define REG_A5XX_RBBM_CLOCK_DELAY_SP0 0x00000074
1291
1292 #define REG_A5XX_RBBM_CLOCK_DELAY_SP1 0x00000075
1293
1294 #define REG_A5XX_RBBM_CLOCK_DELAY_SP2 0x00000076
1295
1296 #define REG_A5XX_RBBM_CLOCK_DELAY_SP3 0x00000077
1297
1298 #define REG_A5XX_RBBM_CLOCK_CNTL_RB0 0x00000078
1299
1300 #define REG_A5XX_RBBM_CLOCK_CNTL_RB1 0x00000079
1301
1302 #define REG_A5XX_RBBM_CLOCK_CNTL_RB2 0x0000007a
1303
1304 #define REG_A5XX_RBBM_CLOCK_CNTL_RB3 0x0000007b
1305
1306 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB0 0x0000007c
1307
1308 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB1 0x0000007d
1309
1310 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB2 0x0000007e
1311
1312 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB3 0x0000007f
1313
1314 #define REG_A5XX_RBBM_CLOCK_HYST_RAC 0x00000080
1315
1316 #define REG_A5XX_RBBM_CLOCK_DELAY_RAC 0x00000081
1317
1318 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU0 0x00000082
1319
1320 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU1 0x00000083
1321
1322 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU2 0x00000084
1323
1324 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU3 0x00000085
1325
1326 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000086
1327
1328 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000087
1329
1330 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000088
1331
1332 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000089
1333
1334 #define REG_A5XX_RBBM_CLOCK_CNTL_RAC 0x0000008a
1335
1336 #define REG_A5XX_RBBM_CLOCK_CNTL2_RAC 0x0000008b
1337
1338 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0 0x0000008c
1339
1340 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1 0x0000008d
1341
1342 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2 0x0000008e
1343
1344 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3 0x0000008f
1345
1346 #define REG_A5XX_RBBM_CLOCK_HYST_VFD 0x00000090
1347
1348 #define REG_A5XX_RBBM_CLOCK_MODE_VFD 0x00000091
1349
1350 #define REG_A5XX_RBBM_CLOCK_DELAY_VFD 0x00000092
1351
1352 #define REG_A5XX_RBBM_AHB_CNTL0 0x00000093
1353
1354 #define REG_A5XX_RBBM_AHB_CNTL1 0x00000094
1355
1356 #define REG_A5XX_RBBM_AHB_CNTL2 0x00000095
1357
1358 #define REG_A5XX_RBBM_AHB_CMD 0x00000096
1359
1360 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11 0x0000009c
1361
1362 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12 0x0000009d
1363
1364 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13 0x0000009e
1365
1366 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14 0x0000009f
1367
1368 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15 0x000000a0
1369
1370 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16 0x000000a1
1371
1372 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17 0x000000a2
1373
1374 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18 0x000000a3
1375
1376 #define REG_A5XX_RBBM_CLOCK_DELAY_TP0 0x000000a4
1377
1378 #define REG_A5XX_RBBM_CLOCK_DELAY_TP1 0x000000a5
1379
1380 #define REG_A5XX_RBBM_CLOCK_DELAY_TP2 0x000000a6
1381
1382 #define REG_A5XX_RBBM_CLOCK_DELAY_TP3 0x000000a7
1383
1384 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP0 0x000000a8
1385
1386 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP1 0x000000a9
1387
1388 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP2 0x000000aa
1389
1390 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP3 0x000000ab
1391
1392 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP0 0x000000ac
1393
1394 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP1 0x000000ad
1395
1396 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP2 0x000000ae
1397
1398 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP3 0x000000af
1399
1400 #define REG_A5XX_RBBM_CLOCK_HYST_TP0 0x000000b0
1401
1402 #define REG_A5XX_RBBM_CLOCK_HYST_TP1 0x000000b1
1403
1404 #define REG_A5XX_RBBM_CLOCK_HYST_TP2 0x000000b2
1405
1406 #define REG_A5XX_RBBM_CLOCK_HYST_TP3 0x000000b3
1407
1408 #define REG_A5XX_RBBM_CLOCK_HYST2_TP0 0x000000b4
1409
1410 #define REG_A5XX_RBBM_CLOCK_HYST2_TP1 0x000000b5
1411
1412 #define REG_A5XX_RBBM_CLOCK_HYST2_TP2 0x000000b6
1413
1414 #define REG_A5XX_RBBM_CLOCK_HYST2_TP3 0x000000b7
1415
1416 #define REG_A5XX_RBBM_CLOCK_HYST3_TP0 0x000000b8
1417
1418 #define REG_A5XX_RBBM_CLOCK_HYST3_TP1 0x000000b9
1419
1420 #define REG_A5XX_RBBM_CLOCK_HYST3_TP2 0x000000ba
1421
1422 #define REG_A5XX_RBBM_CLOCK_HYST3_TP3 0x000000bb
1423
1424 #define REG_A5XX_RBBM_CLOCK_CNTL_GPMU 0x000000c8
1425
1426 #define REG_A5XX_RBBM_CLOCK_DELAY_GPMU 0x000000c9
1427
1428 #define REG_A5XX_RBBM_CLOCK_HYST_GPMU 0x000000ca
1429
1430 #define REG_A5XX_RBBM_PERFCTR_CP_0_LO 0x000003a0
1431
1432 #define REG_A5XX_RBBM_PERFCTR_CP_0_HI 0x000003a1
1433
1434 #define REG_A5XX_RBBM_PERFCTR_CP_1_LO 0x000003a2
1435
1436 #define REG_A5XX_RBBM_PERFCTR_CP_1_HI 0x000003a3
1437
1438 #define REG_A5XX_RBBM_PERFCTR_CP_2_LO 0x000003a4
1439
1440 #define REG_A5XX_RBBM_PERFCTR_CP_2_HI 0x000003a5
1441
1442 #define REG_A5XX_RBBM_PERFCTR_CP_3_LO 0x000003a6
1443
1444 #define REG_A5XX_RBBM_PERFCTR_CP_3_HI 0x000003a7
1445
1446 #define REG_A5XX_RBBM_PERFCTR_CP_4_LO 0x000003a8
1447
1448 #define REG_A5XX_RBBM_PERFCTR_CP_4_HI 0x000003a9
1449
1450 #define REG_A5XX_RBBM_PERFCTR_CP_5_LO 0x000003aa
1451
1452 #define REG_A5XX_RBBM_PERFCTR_CP_5_HI 0x000003ab
1453
1454 #define REG_A5XX_RBBM_PERFCTR_CP_6_LO 0x000003ac
1455
1456 #define REG_A5XX_RBBM_PERFCTR_CP_6_HI 0x000003ad
1457
1458 #define REG_A5XX_RBBM_PERFCTR_CP_7_LO 0x000003ae
1459
1460 #define REG_A5XX_RBBM_PERFCTR_CP_7_HI 0x000003af
1461
1462 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_LO 0x000003b0
1463
1464 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_HI 0x000003b1
1465
1466 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_LO 0x000003b2
1467
1468 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_HI 0x000003b3
1469
1470 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_LO 0x000003b4
1471
1472 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_HI 0x000003b5
1473
1474 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_LO 0x000003b6
1475
1476 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_HI 0x000003b7
1477
1478 #define REG_A5XX_RBBM_PERFCTR_PC_0_LO 0x000003b8
1479
1480 #define REG_A5XX_RBBM_PERFCTR_PC_0_HI 0x000003b9
1481
1482 #define REG_A5XX_RBBM_PERFCTR_PC_1_LO 0x000003ba
1483
1484 #define REG_A5XX_RBBM_PERFCTR_PC_1_HI 0x000003bb
1485
1486 #define REG_A5XX_RBBM_PERFCTR_PC_2_LO 0x000003bc
1487
1488 #define REG_A5XX_RBBM_PERFCTR_PC_2_HI 0x000003bd
1489
1490 #define REG_A5XX_RBBM_PERFCTR_PC_3_LO 0x000003be
1491
1492 #define REG_A5XX_RBBM_PERFCTR_PC_3_HI 0x000003bf
1493
1494 #define REG_A5XX_RBBM_PERFCTR_PC_4_LO 0x000003c0
1495
1496 #define REG_A5XX_RBBM_PERFCTR_PC_4_HI 0x000003c1
1497
1498 #define REG_A5XX_RBBM_PERFCTR_PC_5_LO 0x000003c2
1499
1500 #define REG_A5XX_RBBM_PERFCTR_PC_5_HI 0x000003c3
1501
1502 #define REG_A5XX_RBBM_PERFCTR_PC_6_LO 0x000003c4
1503
1504 #define REG_A5XX_RBBM_PERFCTR_PC_6_HI 0x000003c5
1505
1506 #define REG_A5XX_RBBM_PERFCTR_PC_7_LO 0x000003c6
1507
1508 #define REG_A5XX_RBBM_PERFCTR_PC_7_HI 0x000003c7
1509
1510 #define REG_A5XX_RBBM_PERFCTR_VFD_0_LO 0x000003c8
1511
1512 #define REG_A5XX_RBBM_PERFCTR_VFD_0_HI 0x000003c9
1513
1514 #define REG_A5XX_RBBM_PERFCTR_VFD_1_LO 0x000003ca
1515
1516 #define REG_A5XX_RBBM_PERFCTR_VFD_1_HI 0x000003cb
1517
1518 #define REG_A5XX_RBBM_PERFCTR_VFD_2_LO 0x000003cc
1519
1520 #define REG_A5XX_RBBM_PERFCTR_VFD_2_HI 0x000003cd
1521
1522 #define REG_A5XX_RBBM_PERFCTR_VFD_3_LO 0x000003ce
1523
1524 #define REG_A5XX_RBBM_PERFCTR_VFD_3_HI 0x000003cf
1525
1526 #define REG_A5XX_RBBM_PERFCTR_VFD_4_LO 0x000003d0
1527
1528 #define REG_A5XX_RBBM_PERFCTR_VFD_4_HI 0x000003d1
1529
1530 #define REG_A5XX_RBBM_PERFCTR_VFD_5_LO 0x000003d2
1531
1532 #define REG_A5XX_RBBM_PERFCTR_VFD_5_HI 0x000003d3
1533
1534 #define REG_A5XX_RBBM_PERFCTR_VFD_6_LO 0x000003d4
1535
1536 #define REG_A5XX_RBBM_PERFCTR_VFD_6_HI 0x000003d5
1537
1538 #define REG_A5XX_RBBM_PERFCTR_VFD_7_LO 0x000003d6
1539
1540 #define REG_A5XX_RBBM_PERFCTR_VFD_7_HI 0x000003d7
1541
1542 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_LO 0x000003d8
1543
1544 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_HI 0x000003d9
1545
1546 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_LO 0x000003da
1547
1548 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_HI 0x000003db
1549
1550 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_LO 0x000003dc
1551
1552 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_HI 0x000003dd
1553
1554 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_LO 0x000003de
1555
1556 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_HI 0x000003df
1557
1558 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_LO 0x000003e0
1559
1560 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_HI 0x000003e1
1561
1562 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_LO 0x000003e2
1563
1564 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_HI 0x000003e3
1565
1566 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_LO 0x000003e4
1567
1568 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_HI 0x000003e5
1569
1570 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_LO 0x000003e6
1571
1572 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_HI 0x000003e7
1573
1574 #define REG_A5XX_RBBM_PERFCTR_VPC_0_LO 0x000003e8
1575
1576 #define REG_A5XX_RBBM_PERFCTR_VPC_0_HI 0x000003e9
1577
1578 #define REG_A5XX_RBBM_PERFCTR_VPC_1_LO 0x000003ea
1579
1580 #define REG_A5XX_RBBM_PERFCTR_VPC_1_HI 0x000003eb
1581
1582 #define REG_A5XX_RBBM_PERFCTR_VPC_2_LO 0x000003ec
1583
1584 #define REG_A5XX_RBBM_PERFCTR_VPC_2_HI 0x000003ed
1585
1586 #define REG_A5XX_RBBM_PERFCTR_VPC_3_LO 0x000003ee
1587
1588 #define REG_A5XX_RBBM_PERFCTR_VPC_3_HI 0x000003ef
1589
1590 #define REG_A5XX_RBBM_PERFCTR_CCU_0_LO 0x000003f0
1591
1592 #define REG_A5XX_RBBM_PERFCTR_CCU_0_HI 0x000003f1
1593
1594 #define REG_A5XX_RBBM_PERFCTR_CCU_1_LO 0x000003f2
1595
1596 #define REG_A5XX_RBBM_PERFCTR_CCU_1_HI 0x000003f3
1597
1598 #define REG_A5XX_RBBM_PERFCTR_CCU_2_LO 0x000003f4
1599
1600 #define REG_A5XX_RBBM_PERFCTR_CCU_2_HI 0x000003f5
1601
1602 #define REG_A5XX_RBBM_PERFCTR_CCU_3_LO 0x000003f6
1603
1604 #define REG_A5XX_RBBM_PERFCTR_CCU_3_HI 0x000003f7
1605
1606 #define REG_A5XX_RBBM_PERFCTR_TSE_0_LO 0x000003f8
1607
1608 #define REG_A5XX_RBBM_PERFCTR_TSE_0_HI 0x000003f9
1609
1610 #define REG_A5XX_RBBM_PERFCTR_TSE_1_LO 0x000003fa
1611
1612 #define REG_A5XX_RBBM_PERFCTR_TSE_1_HI 0x000003fb
1613
1614 #define REG_A5XX_RBBM_PERFCTR_TSE_2_LO 0x000003fc
1615
1616 #define REG_A5XX_RBBM_PERFCTR_TSE_2_HI 0x000003fd
1617
1618 #define REG_A5XX_RBBM_PERFCTR_TSE_3_LO 0x000003fe
1619
1620 #define REG_A5XX_RBBM_PERFCTR_TSE_3_HI 0x000003ff
1621
1622 #define REG_A5XX_RBBM_PERFCTR_RAS_0_LO 0x00000400
1623
1624 #define REG_A5XX_RBBM_PERFCTR_RAS_0_HI 0x00000401
1625
1626 #define REG_A5XX_RBBM_PERFCTR_RAS_1_LO 0x00000402
1627
1628 #define REG_A5XX_RBBM_PERFCTR_RAS_1_HI 0x00000403
1629
1630 #define REG_A5XX_RBBM_PERFCTR_RAS_2_LO 0x00000404
1631
1632 #define REG_A5XX_RBBM_PERFCTR_RAS_2_HI 0x00000405
1633
1634 #define REG_A5XX_RBBM_PERFCTR_RAS_3_LO 0x00000406
1635
1636 #define REG_A5XX_RBBM_PERFCTR_RAS_3_HI 0x00000407
1637
1638 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_LO 0x00000408
1639
1640 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_HI 0x00000409
1641
1642 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_LO 0x0000040a
1643
1644 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_HI 0x0000040b
1645
1646 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_LO 0x0000040c
1647
1648 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_HI 0x0000040d
1649
1650 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_LO 0x0000040e
1651
1652 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_HI 0x0000040f
1653
1654 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_LO 0x00000410
1655
1656 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_HI 0x00000411
1657
1658 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_LO 0x00000412
1659
1660 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_HI 0x00000413
1661
1662 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_LO 0x00000414
1663
1664 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_HI 0x00000415
1665
1666 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_LO 0x00000416
1667
1668 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_HI 0x00000417
1669
1670 #define REG_A5XX_RBBM_PERFCTR_TP_0_LO 0x00000418
1671
1672 #define REG_A5XX_RBBM_PERFCTR_TP_0_HI 0x00000419
1673
1674 #define REG_A5XX_RBBM_PERFCTR_TP_1_LO 0x0000041a
1675
1676 #define REG_A5XX_RBBM_PERFCTR_TP_1_HI 0x0000041b
1677
1678 #define REG_A5XX_RBBM_PERFCTR_TP_2_LO 0x0000041c
1679
1680 #define REG_A5XX_RBBM_PERFCTR_TP_2_HI 0x0000041d
1681
1682 #define REG_A5XX_RBBM_PERFCTR_TP_3_LO 0x0000041e
1683
1684 #define REG_A5XX_RBBM_PERFCTR_TP_3_HI 0x0000041f
1685
1686 #define REG_A5XX_RBBM_PERFCTR_TP_4_LO 0x00000420
1687
1688 #define REG_A5XX_RBBM_PERFCTR_TP_4_HI 0x00000421
1689
1690 #define REG_A5XX_RBBM_PERFCTR_TP_5_LO 0x00000422
1691
1692 #define REG_A5XX_RBBM_PERFCTR_TP_5_HI 0x00000423
1693
1694 #define REG_A5XX_RBBM_PERFCTR_TP_6_LO 0x00000424
1695
1696 #define REG_A5XX_RBBM_PERFCTR_TP_6_HI 0x00000425
1697
1698 #define REG_A5XX_RBBM_PERFCTR_TP_7_LO 0x00000426
1699
1700 #define REG_A5XX_RBBM_PERFCTR_TP_7_HI 0x00000427
1701
1702 #define REG_A5XX_RBBM_PERFCTR_SP_0_LO 0x00000428
1703
1704 #define REG_A5XX_RBBM_PERFCTR_SP_0_HI 0x00000429
1705
1706 #define REG_A5XX_RBBM_PERFCTR_SP_1_LO 0x0000042a
1707
1708 #define REG_A5XX_RBBM_PERFCTR_SP_1_HI 0x0000042b
1709
1710 #define REG_A5XX_RBBM_PERFCTR_SP_2_LO 0x0000042c
1711
1712 #define REG_A5XX_RBBM_PERFCTR_SP_2_HI 0x0000042d
1713
1714 #define REG_A5XX_RBBM_PERFCTR_SP_3_LO 0x0000042e
1715
1716 #define REG_A5XX_RBBM_PERFCTR_SP_3_HI 0x0000042f
1717
1718 #define REG_A5XX_RBBM_PERFCTR_SP_4_LO 0x00000430
1719
1720 #define REG_A5XX_RBBM_PERFCTR_SP_4_HI 0x00000431
1721
1722 #define REG_A5XX_RBBM_PERFCTR_SP_5_LO 0x00000432
1723
1724 #define REG_A5XX_RBBM_PERFCTR_SP_5_HI 0x00000433
1725
1726 #define REG_A5XX_RBBM_PERFCTR_SP_6_LO 0x00000434
1727
1728 #define REG_A5XX_RBBM_PERFCTR_SP_6_HI 0x00000435
1729
1730 #define REG_A5XX_RBBM_PERFCTR_SP_7_LO 0x00000436
1731
1732 #define REG_A5XX_RBBM_PERFCTR_SP_7_HI 0x00000437
1733
1734 #define REG_A5XX_RBBM_PERFCTR_SP_8_LO 0x00000438
1735
1736 #define REG_A5XX_RBBM_PERFCTR_SP_8_HI 0x00000439
1737
1738 #define REG_A5XX_RBBM_PERFCTR_SP_9_LO 0x0000043a
1739
1740 #define REG_A5XX_RBBM_PERFCTR_SP_9_HI 0x0000043b
1741
1742 #define REG_A5XX_RBBM_PERFCTR_SP_10_LO 0x0000043c
1743
1744 #define REG_A5XX_RBBM_PERFCTR_SP_10_HI 0x0000043d
1745
1746 #define REG_A5XX_RBBM_PERFCTR_SP_11_LO 0x0000043e
1747
1748 #define REG_A5XX_RBBM_PERFCTR_SP_11_HI 0x0000043f
1749
1750 #define REG_A5XX_RBBM_PERFCTR_RB_0_LO 0x00000440
1751
1752 #define REG_A5XX_RBBM_PERFCTR_RB_0_HI 0x00000441
1753
1754 #define REG_A5XX_RBBM_PERFCTR_RB_1_LO 0x00000442
1755
1756 #define REG_A5XX_RBBM_PERFCTR_RB_1_HI 0x00000443
1757
1758 #define REG_A5XX_RBBM_PERFCTR_RB_2_LO 0x00000444
1759
1760 #define REG_A5XX_RBBM_PERFCTR_RB_2_HI 0x00000445
1761
1762 #define REG_A5XX_RBBM_PERFCTR_RB_3_LO 0x00000446
1763
1764 #define REG_A5XX_RBBM_PERFCTR_RB_3_HI 0x00000447
1765
1766 #define REG_A5XX_RBBM_PERFCTR_RB_4_LO 0x00000448
1767
1768 #define REG_A5XX_RBBM_PERFCTR_RB_4_HI 0x00000449
1769
1770 #define REG_A5XX_RBBM_PERFCTR_RB_5_LO 0x0000044a
1771
1772 #define REG_A5XX_RBBM_PERFCTR_RB_5_HI 0x0000044b
1773
1774 #define REG_A5XX_RBBM_PERFCTR_RB_6_LO 0x0000044c
1775
1776 #define REG_A5XX_RBBM_PERFCTR_RB_6_HI 0x0000044d
1777
1778 #define REG_A5XX_RBBM_PERFCTR_RB_7_LO 0x0000044e
1779
1780 #define REG_A5XX_RBBM_PERFCTR_RB_7_HI 0x0000044f
1781
1782 #define REG_A5XX_RBBM_PERFCTR_VSC_0_LO 0x00000450
1783
1784 #define REG_A5XX_RBBM_PERFCTR_VSC_0_HI 0x00000451
1785
1786 #define REG_A5XX_RBBM_PERFCTR_VSC_1_LO 0x00000452
1787
1788 #define REG_A5XX_RBBM_PERFCTR_VSC_1_HI 0x00000453
1789
1790 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_LO 0x00000454
1791
1792 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_HI 0x00000455
1793
1794 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_LO 0x00000456
1795
1796 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_HI 0x00000457
1797
1798 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_LO 0x00000458
1799
1800 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_HI 0x00000459
1801
1802 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_LO 0x0000045a
1803
1804 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_HI 0x0000045b
1805
1806 #define REG_A5XX_RBBM_PERFCTR_CMP_0_LO 0x0000045c
1807
1808 #define REG_A5XX_RBBM_PERFCTR_CMP_0_HI 0x0000045d
1809
1810 #define REG_A5XX_RBBM_PERFCTR_CMP_1_LO 0x0000045e
1811
1812 #define REG_A5XX_RBBM_PERFCTR_CMP_1_HI 0x0000045f
1813
1814 #define REG_A5XX_RBBM_PERFCTR_CMP_2_LO 0x00000460
1815
1816 #define REG_A5XX_RBBM_PERFCTR_CMP_2_HI 0x00000461
1817
1818 #define REG_A5XX_RBBM_PERFCTR_CMP_3_LO 0x00000462
1819
1820 #define REG_A5XX_RBBM_PERFCTR_CMP_3_HI 0x00000463
1821
1822 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b
1823
1824 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c
1825
1826 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d
1827
1828 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e
1829
1830 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_LO 0x000004d2
1831
1832 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI 0x000004d3
1833
1834 #define REG_A5XX_RBBM_STATUS 0x000004f5
1835 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__MASK 0x80000000
1836 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__SHIFT 31
A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB(uint32_t val)1837 static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB(uint32_t val)
1838 {
1839 return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__MASK;
1840 }
1841 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__MASK 0x40000000
1842 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__SHIFT 30
A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP(uint32_t val)1843 static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP(uint32_t val)
1844 {
1845 return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__MASK;
1846 }
1847 #define A5XX_RBBM_STATUS_HLSQ_BUSY__MASK 0x20000000
1848 #define A5XX_RBBM_STATUS_HLSQ_BUSY__SHIFT 29
A5XX_RBBM_STATUS_HLSQ_BUSY(uint32_t val)1849 static inline uint32_t A5XX_RBBM_STATUS_HLSQ_BUSY(uint32_t val)
1850 {
1851 return ((val) << A5XX_RBBM_STATUS_HLSQ_BUSY__SHIFT) & A5XX_RBBM_STATUS_HLSQ_BUSY__MASK;
1852 }
1853 #define A5XX_RBBM_STATUS_VSC_BUSY__MASK 0x10000000
1854 #define A5XX_RBBM_STATUS_VSC_BUSY__SHIFT 28
A5XX_RBBM_STATUS_VSC_BUSY(uint32_t val)1855 static inline uint32_t A5XX_RBBM_STATUS_VSC_BUSY(uint32_t val)
1856 {
1857 return ((val) << A5XX_RBBM_STATUS_VSC_BUSY__SHIFT) & A5XX_RBBM_STATUS_VSC_BUSY__MASK;
1858 }
1859 #define A5XX_RBBM_STATUS_TPL1_BUSY__MASK 0x08000000
1860 #define A5XX_RBBM_STATUS_TPL1_BUSY__SHIFT 27
A5XX_RBBM_STATUS_TPL1_BUSY(uint32_t val)1861 static inline uint32_t A5XX_RBBM_STATUS_TPL1_BUSY(uint32_t val)
1862 {
1863 return ((val) << A5XX_RBBM_STATUS_TPL1_BUSY__SHIFT) & A5XX_RBBM_STATUS_TPL1_BUSY__MASK;
1864 }
1865 #define A5XX_RBBM_STATUS_SP_BUSY__MASK 0x04000000
1866 #define A5XX_RBBM_STATUS_SP_BUSY__SHIFT 26
A5XX_RBBM_STATUS_SP_BUSY(uint32_t val)1867 static inline uint32_t A5XX_RBBM_STATUS_SP_BUSY(uint32_t val)
1868 {
1869 return ((val) << A5XX_RBBM_STATUS_SP_BUSY__SHIFT) & A5XX_RBBM_STATUS_SP_BUSY__MASK;
1870 }
1871 #define A5XX_RBBM_STATUS_UCHE_BUSY__MASK 0x02000000
1872 #define A5XX_RBBM_STATUS_UCHE_BUSY__SHIFT 25
A5XX_RBBM_STATUS_UCHE_BUSY(uint32_t val)1873 static inline uint32_t A5XX_RBBM_STATUS_UCHE_BUSY(uint32_t val)
1874 {
1875 return ((val) << A5XX_RBBM_STATUS_UCHE_BUSY__SHIFT) & A5XX_RBBM_STATUS_UCHE_BUSY__MASK;
1876 }
1877 #define A5XX_RBBM_STATUS_VPC_BUSY__MASK 0x01000000
1878 #define A5XX_RBBM_STATUS_VPC_BUSY__SHIFT 24
A5XX_RBBM_STATUS_VPC_BUSY(uint32_t val)1879 static inline uint32_t A5XX_RBBM_STATUS_VPC_BUSY(uint32_t val)
1880 {
1881 return ((val) << A5XX_RBBM_STATUS_VPC_BUSY__SHIFT) & A5XX_RBBM_STATUS_VPC_BUSY__MASK;
1882 }
1883 #define A5XX_RBBM_STATUS_VFDP_BUSY__MASK 0x00800000
1884 #define A5XX_RBBM_STATUS_VFDP_BUSY__SHIFT 23
A5XX_RBBM_STATUS_VFDP_BUSY(uint32_t val)1885 static inline uint32_t A5XX_RBBM_STATUS_VFDP_BUSY(uint32_t val)
1886 {
1887 return ((val) << A5XX_RBBM_STATUS_VFDP_BUSY__SHIFT) & A5XX_RBBM_STATUS_VFDP_BUSY__MASK;
1888 }
1889 #define A5XX_RBBM_STATUS_VFD_BUSY__MASK 0x00400000
1890 #define A5XX_RBBM_STATUS_VFD_BUSY__SHIFT 22
A5XX_RBBM_STATUS_VFD_BUSY(uint32_t val)1891 static inline uint32_t A5XX_RBBM_STATUS_VFD_BUSY(uint32_t val)
1892 {
1893 return ((val) << A5XX_RBBM_STATUS_VFD_BUSY__SHIFT) & A5XX_RBBM_STATUS_VFD_BUSY__MASK;
1894 }
1895 #define A5XX_RBBM_STATUS_TESS_BUSY__MASK 0x00200000
1896 #define A5XX_RBBM_STATUS_TESS_BUSY__SHIFT 21
A5XX_RBBM_STATUS_TESS_BUSY(uint32_t val)1897 static inline uint32_t A5XX_RBBM_STATUS_TESS_BUSY(uint32_t val)
1898 {
1899 return ((val) << A5XX_RBBM_STATUS_TESS_BUSY__SHIFT) & A5XX_RBBM_STATUS_TESS_BUSY__MASK;
1900 }
1901 #define A5XX_RBBM_STATUS_PC_VSD_BUSY__MASK 0x00100000
1902 #define A5XX_RBBM_STATUS_PC_VSD_BUSY__SHIFT 20
A5XX_RBBM_STATUS_PC_VSD_BUSY(uint32_t val)1903 static inline uint32_t A5XX_RBBM_STATUS_PC_VSD_BUSY(uint32_t val)
1904 {
1905 return ((val) << A5XX_RBBM_STATUS_PC_VSD_BUSY__SHIFT) & A5XX_RBBM_STATUS_PC_VSD_BUSY__MASK;
1906 }
1907 #define A5XX_RBBM_STATUS_PC_DCALL_BUSY__MASK 0x00080000
1908 #define A5XX_RBBM_STATUS_PC_DCALL_BUSY__SHIFT 19
A5XX_RBBM_STATUS_PC_DCALL_BUSY(uint32_t val)1909 static inline uint32_t A5XX_RBBM_STATUS_PC_DCALL_BUSY(uint32_t val)
1910 {
1911 return ((val) << A5XX_RBBM_STATUS_PC_DCALL_BUSY__SHIFT) & A5XX_RBBM_STATUS_PC_DCALL_BUSY__MASK;
1912 }
1913 #define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__MASK 0x00040000
1914 #define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__SHIFT 18
A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY(uint32_t val)1915 static inline uint32_t A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY(uint32_t val)
1916 {
1917 return ((val) << A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__SHIFT) & A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__MASK;
1918 }
1919 #define A5XX_RBBM_STATUS_DCOM_BUSY__MASK 0x00020000
1920 #define A5XX_RBBM_STATUS_DCOM_BUSY__SHIFT 17
A5XX_RBBM_STATUS_DCOM_BUSY(uint32_t val)1921 static inline uint32_t A5XX_RBBM_STATUS_DCOM_BUSY(uint32_t val)
1922 {
1923 return ((val) << A5XX_RBBM_STATUS_DCOM_BUSY__SHIFT) & A5XX_RBBM_STATUS_DCOM_BUSY__MASK;
1924 }
1925 #define A5XX_RBBM_STATUS_COM_BUSY__MASK 0x00010000
1926 #define A5XX_RBBM_STATUS_COM_BUSY__SHIFT 16
A5XX_RBBM_STATUS_COM_BUSY(uint32_t val)1927 static inline uint32_t A5XX_RBBM_STATUS_COM_BUSY(uint32_t val)
1928 {
1929 return ((val) << A5XX_RBBM_STATUS_COM_BUSY__SHIFT) & A5XX_RBBM_STATUS_COM_BUSY__MASK;
1930 }
1931 #define A5XX_RBBM_STATUS_LRZ_BUZY__MASK 0x00008000
1932 #define A5XX_RBBM_STATUS_LRZ_BUZY__SHIFT 15
A5XX_RBBM_STATUS_LRZ_BUZY(uint32_t val)1933 static inline uint32_t A5XX_RBBM_STATUS_LRZ_BUZY(uint32_t val)
1934 {
1935 return ((val) << A5XX_RBBM_STATUS_LRZ_BUZY__SHIFT) & A5XX_RBBM_STATUS_LRZ_BUZY__MASK;
1936 }
1937 #define A5XX_RBBM_STATUS_A2D_DSP_BUSY__MASK 0x00004000
1938 #define A5XX_RBBM_STATUS_A2D_DSP_BUSY__SHIFT 14
A5XX_RBBM_STATUS_A2D_DSP_BUSY(uint32_t val)1939 static inline uint32_t A5XX_RBBM_STATUS_A2D_DSP_BUSY(uint32_t val)
1940 {
1941 return ((val) << A5XX_RBBM_STATUS_A2D_DSP_BUSY__SHIFT) & A5XX_RBBM_STATUS_A2D_DSP_BUSY__MASK;
1942 }
1943 #define A5XX_RBBM_STATUS_CCUFCHE_BUSY__MASK 0x00002000
1944 #define A5XX_RBBM_STATUS_CCUFCHE_BUSY__SHIFT 13
A5XX_RBBM_STATUS_CCUFCHE_BUSY(uint32_t val)1945 static inline uint32_t A5XX_RBBM_STATUS_CCUFCHE_BUSY(uint32_t val)
1946 {
1947 return ((val) << A5XX_RBBM_STATUS_CCUFCHE_BUSY__SHIFT) & A5XX_RBBM_STATUS_CCUFCHE_BUSY__MASK;
1948 }
1949 #define A5XX_RBBM_STATUS_RB_BUSY__MASK 0x00001000
1950 #define A5XX_RBBM_STATUS_RB_BUSY__SHIFT 12
A5XX_RBBM_STATUS_RB_BUSY(uint32_t val)1951 static inline uint32_t A5XX_RBBM_STATUS_RB_BUSY(uint32_t val)
1952 {
1953 return ((val) << A5XX_RBBM_STATUS_RB_BUSY__SHIFT) & A5XX_RBBM_STATUS_RB_BUSY__MASK;
1954 }
1955 #define A5XX_RBBM_STATUS_RAS_BUSY__MASK 0x00000800
1956 #define A5XX_RBBM_STATUS_RAS_BUSY__SHIFT 11
A5XX_RBBM_STATUS_RAS_BUSY(uint32_t val)1957 static inline uint32_t A5XX_RBBM_STATUS_RAS_BUSY(uint32_t val)
1958 {
1959 return ((val) << A5XX_RBBM_STATUS_RAS_BUSY__SHIFT) & A5XX_RBBM_STATUS_RAS_BUSY__MASK;
1960 }
1961 #define A5XX_RBBM_STATUS_TSE_BUSY__MASK 0x00000400
1962 #define A5XX_RBBM_STATUS_TSE_BUSY__SHIFT 10
A5XX_RBBM_STATUS_TSE_BUSY(uint32_t val)1963 static inline uint32_t A5XX_RBBM_STATUS_TSE_BUSY(uint32_t val)
1964 {
1965 return ((val) << A5XX_RBBM_STATUS_TSE_BUSY__SHIFT) & A5XX_RBBM_STATUS_TSE_BUSY__MASK;
1966 }
1967 #define A5XX_RBBM_STATUS_VBIF_BUSY__MASK 0x00000200
1968 #define A5XX_RBBM_STATUS_VBIF_BUSY__SHIFT 9
A5XX_RBBM_STATUS_VBIF_BUSY(uint32_t val)1969 static inline uint32_t A5XX_RBBM_STATUS_VBIF_BUSY(uint32_t val)
1970 {
1971 return ((val) << A5XX_RBBM_STATUS_VBIF_BUSY__SHIFT) & A5XX_RBBM_STATUS_VBIF_BUSY__MASK;
1972 }
1973 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__MASK 0x00000100
1974 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__SHIFT 8
A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST(uint32_t val)1975 static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST(uint32_t val)
1976 {
1977 return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__MASK;
1978 }
1979 #define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__MASK 0x00000080
1980 #define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__SHIFT 7
A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST(uint32_t val)1981 static inline uint32_t A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST(uint32_t val)
1982 {
1983 return ((val) << A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__SHIFT) & A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__MASK;
1984 }
1985 #define A5XX_RBBM_STATUS_CP_BUSY__MASK 0x00000040
1986 #define A5XX_RBBM_STATUS_CP_BUSY__SHIFT 6
A5XX_RBBM_STATUS_CP_BUSY(uint32_t val)1987 static inline uint32_t A5XX_RBBM_STATUS_CP_BUSY(uint32_t val)
1988 {
1989 return ((val) << A5XX_RBBM_STATUS_CP_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_BUSY__MASK;
1990 }
1991 #define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__MASK 0x00000020
1992 #define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__SHIFT 5
A5XX_RBBM_STATUS_GPMU_MASTER_BUSY(uint32_t val)1993 static inline uint32_t A5XX_RBBM_STATUS_GPMU_MASTER_BUSY(uint32_t val)
1994 {
1995 return ((val) << A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__SHIFT) & A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__MASK;
1996 }
1997 #define A5XX_RBBM_STATUS_CP_CRASH_BUSY__MASK 0x00000010
1998 #define A5XX_RBBM_STATUS_CP_CRASH_BUSY__SHIFT 4
A5XX_RBBM_STATUS_CP_CRASH_BUSY(uint32_t val)1999 static inline uint32_t A5XX_RBBM_STATUS_CP_CRASH_BUSY(uint32_t val)
2000 {
2001 return ((val) << A5XX_RBBM_STATUS_CP_CRASH_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_CRASH_BUSY__MASK;
2002 }
2003 #define A5XX_RBBM_STATUS_CP_ETS_BUSY__MASK 0x00000008
2004 #define A5XX_RBBM_STATUS_CP_ETS_BUSY__SHIFT 3
A5XX_RBBM_STATUS_CP_ETS_BUSY(uint32_t val)2005 static inline uint32_t A5XX_RBBM_STATUS_CP_ETS_BUSY(uint32_t val)
2006 {
2007 return ((val) << A5XX_RBBM_STATUS_CP_ETS_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_ETS_BUSY__MASK;
2008 }
2009 #define A5XX_RBBM_STATUS_CP_PFP_BUSY__MASK 0x00000004
2010 #define A5XX_RBBM_STATUS_CP_PFP_BUSY__SHIFT 2
A5XX_RBBM_STATUS_CP_PFP_BUSY(uint32_t val)2011 static inline uint32_t A5XX_RBBM_STATUS_CP_PFP_BUSY(uint32_t val)
2012 {
2013 return ((val) << A5XX_RBBM_STATUS_CP_PFP_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_PFP_BUSY__MASK;
2014 }
2015 #define A5XX_RBBM_STATUS_CP_ME_BUSY__MASK 0x00000002
2016 #define A5XX_RBBM_STATUS_CP_ME_BUSY__SHIFT 1
A5XX_RBBM_STATUS_CP_ME_BUSY(uint32_t val)2017 static inline uint32_t A5XX_RBBM_STATUS_CP_ME_BUSY(uint32_t val)
2018 {
2019 return ((val) << A5XX_RBBM_STATUS_CP_ME_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_ME_BUSY__MASK;
2020 }
2021 #define A5XX_RBBM_STATUS_HI_BUSY 0x00000001
2022
2023 #define REG_A5XX_RBBM_STATUS3 0x00000530
2024 #define A5XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000
2025
2026 #define REG_A5XX_RBBM_INT_0_STATUS 0x000004e1
2027
2028 #define REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS 0x000004f0
2029
2030 #define REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS 0x000004f1
2031
2032 #define REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS 0x000004f3
2033
2034 #define REG_A5XX_RBBM_AHB_ERROR_STATUS 0x000004f4
2035
2036 #define REG_A5XX_RBBM_PERFCTR_CNTL 0x00000464
2037
2038 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD0 0x00000465
2039
2040 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD1 0x00000466
2041
2042 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD2 0x00000467
2043
2044 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD3 0x00000468
2045
2046 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000469
2047
2048 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x0000046a
2049
2050 #define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000046f
2051
2052 #define REG_A5XX_RBBM_AHB_ERROR 0x000004ed
2053
2054 #define REG_A5XX_RBBM_CFG_DBGBUS_EVENT_LOGIC 0x00000504
2055
2056 #define REG_A5XX_RBBM_CFG_DBGBUS_OVER 0x00000505
2057
2058 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT0 0x00000506
2059
2060 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT1 0x00000507
2061
2062 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT2 0x00000508
2063
2064 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT3 0x00000509
2065
2066 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT4 0x0000050a
2067
2068 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT5 0x0000050b
2069
2070 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_ADDR 0x0000050c
2071
2072 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF0 0x0000050d
2073
2074 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF1 0x0000050e
2075
2076 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF2 0x0000050f
2077
2078 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF3 0x00000510
2079
2080 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF4 0x00000511
2081
2082 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR0 0x00000512
2083
2084 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR1 0x00000513
2085
2086 #define REG_A5XX_RBBM_ISDB_CNT 0x00000533
2087
2088 #define REG_A5XX_RBBM_SECVID_TRUST_CONFIG 0x0000f000
2089
2090 #define REG_A5XX_RBBM_SECVID_TRUST_CNTL 0x0000f400
2091
2092 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800
2093
2094 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801
2095
2096 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802
2097
2098 #define REG_A5XX_RBBM_SECVID_TSB_CNTL 0x0000f803
2099
2100 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_LO 0x0000f804
2101
2102 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_HI 0x0000f805
2103
2104 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_LO 0x0000f806
2105
2106 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_HI 0x0000f807
2107
2108 #define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810
2109
2110 #define REG_A5XX_VSC_BIN_SIZE 0x00000bc2
2111 #define A5XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff
2112 #define A5XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val)2113 static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
2114 {
2115 return ((val >> 5) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A5XX_VSC_BIN_SIZE_WIDTH__MASK;
2116 }
2117 #define A5XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001fe00
2118 #define A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT 9
A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)2119 static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
2120 {
2121 return ((val >> 5) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK;
2122 }
2123
2124 #define REG_A5XX_VSC_SIZE_ADDRESS_LO 0x00000bc3
2125
2126 #define REG_A5XX_VSC_SIZE_ADDRESS_HI 0x00000bc4
2127
2128 #define REG_A5XX_UNKNOWN_0BC5 0x00000bc5
2129
2130 #define REG_A5XX_UNKNOWN_0BC6 0x00000bc6
2131
REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0)2132 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
2133
REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0)2134 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
2135 #define A5XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
2136 #define A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)2137 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
2138 {
2139 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_X__MASK;
2140 }
2141 #define A5XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
2142 #define A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
A5XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)2143 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
2144 {
2145 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_Y__MASK;
2146 }
2147 #define A5XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000
2148 #define A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
A5XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)2149 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
2150 {
2151 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_W__MASK;
2152 }
2153 #define A5XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000
2154 #define A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24
A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)2155 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
2156 {
2157 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_H__MASK;
2158 }
2159
REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0)2160 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
2161
REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0)2162 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
2163
REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0)2164 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0; }
2165
REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0)2166 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
2167
REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0)2168 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
2169
2170 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_0 0x00000c60
2171
2172 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_1 0x00000c61
2173
2174 #define REG_A5XX_VSC_RESOLVE_CNTL 0x00000cdd
2175 #define A5XX_VSC_RESOLVE_CNTL_WINDOW_OFFSET_DISABLE 0x80000000
2176 #define A5XX_VSC_RESOLVE_CNTL_X__MASK 0x00007fff
2177 #define A5XX_VSC_RESOLVE_CNTL_X__SHIFT 0
A5XX_VSC_RESOLVE_CNTL_X(uint32_t val)2178 static inline uint32_t A5XX_VSC_RESOLVE_CNTL_X(uint32_t val)
2179 {
2180 return ((val) << A5XX_VSC_RESOLVE_CNTL_X__SHIFT) & A5XX_VSC_RESOLVE_CNTL_X__MASK;
2181 }
2182 #define A5XX_VSC_RESOLVE_CNTL_Y__MASK 0x7fff0000
2183 #define A5XX_VSC_RESOLVE_CNTL_Y__SHIFT 16
A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)2184 static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
2185 {
2186 return ((val) << A5XX_VSC_RESOLVE_CNTL_Y__SHIFT) & A5XX_VSC_RESOLVE_CNTL_Y__MASK;
2187 }
2188
2189 #define REG_A5XX_GRAS_ADDR_MODE_CNTL 0x00000c81
2190
2191 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c90
2192
2193 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c91
2194
2195 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c92
2196
2197 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c93
2198
2199 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c94
2200
2201 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c95
2202
2203 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c96
2204
2205 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c97
2206
2207 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_0 0x00000c98
2208
2209 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_1 0x00000c99
2210
2211 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_2 0x00000c9a
2212
2213 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_3 0x00000c9b
2214
2215 #define REG_A5XX_RB_DBG_ECO_CNTL 0x00000cc4
2216
2217 #define REG_A5XX_RB_ADDR_MODE_CNTL 0x00000cc5
2218
2219 #define REG_A5XX_RB_MODE_CNTL 0x00000cc6
2220
2221 #define REG_A5XX_RB_CCU_CNTL 0x00000cc7
2222
2223 #define REG_A5XX_RB_PERFCTR_RB_SEL_0 0x00000cd0
2224
2225 #define REG_A5XX_RB_PERFCTR_RB_SEL_1 0x00000cd1
2226
2227 #define REG_A5XX_RB_PERFCTR_RB_SEL_2 0x00000cd2
2228
2229 #define REG_A5XX_RB_PERFCTR_RB_SEL_3 0x00000cd3
2230
2231 #define REG_A5XX_RB_PERFCTR_RB_SEL_4 0x00000cd4
2232
2233 #define REG_A5XX_RB_PERFCTR_RB_SEL_5 0x00000cd5
2234
2235 #define REG_A5XX_RB_PERFCTR_RB_SEL_6 0x00000cd6
2236
2237 #define REG_A5XX_RB_PERFCTR_RB_SEL_7 0x00000cd7
2238
2239 #define REG_A5XX_RB_PERFCTR_CCU_SEL_0 0x00000cd8
2240
2241 #define REG_A5XX_RB_PERFCTR_CCU_SEL_1 0x00000cd9
2242
2243 #define REG_A5XX_RB_PERFCTR_CCU_SEL_2 0x00000cda
2244
2245 #define REG_A5XX_RB_PERFCTR_CCU_SEL_3 0x00000cdb
2246
2247 #define REG_A5XX_RB_POWERCTR_RB_SEL_0 0x00000ce0
2248
2249 #define REG_A5XX_RB_POWERCTR_RB_SEL_1 0x00000ce1
2250
2251 #define REG_A5XX_RB_POWERCTR_RB_SEL_2 0x00000ce2
2252
2253 #define REG_A5XX_RB_POWERCTR_RB_SEL_3 0x00000ce3
2254
2255 #define REG_A5XX_RB_POWERCTR_CCU_SEL_0 0x00000ce4
2256
2257 #define REG_A5XX_RB_POWERCTR_CCU_SEL_1 0x00000ce5
2258
2259 #define REG_A5XX_RB_PERFCTR_CMP_SEL_0 0x00000cec
2260
2261 #define REG_A5XX_RB_PERFCTR_CMP_SEL_1 0x00000ced
2262
2263 #define REG_A5XX_RB_PERFCTR_CMP_SEL_2 0x00000cee
2264
2265 #define REG_A5XX_RB_PERFCTR_CMP_SEL_3 0x00000cef
2266
2267 #define REG_A5XX_PC_DBG_ECO_CNTL 0x00000d00
2268 #define A5XX_PC_DBG_ECO_CNTL_TWOPASSUSEWFI 0x00000100
2269
2270 #define REG_A5XX_PC_ADDR_MODE_CNTL 0x00000d01
2271
2272 #define REG_A5XX_PC_MODE_CNTL 0x00000d02
2273
2274 #define REG_A5XX_PC_INDEX_BUF_LO 0x00000d04
2275
2276 #define REG_A5XX_PC_INDEX_BUF_HI 0x00000d05
2277
2278 #define REG_A5XX_PC_START_INDEX 0x00000d06
2279
2280 #define REG_A5XX_PC_MAX_INDEX 0x00000d07
2281
2282 #define REG_A5XX_PC_TESSFACTOR_ADDR_LO 0x00000d08
2283
2284 #define REG_A5XX_PC_TESSFACTOR_ADDR_HI 0x00000d09
2285
2286 #define REG_A5XX_PC_PERFCTR_PC_SEL_0 0x00000d10
2287
2288 #define REG_A5XX_PC_PERFCTR_PC_SEL_1 0x00000d11
2289
2290 #define REG_A5XX_PC_PERFCTR_PC_SEL_2 0x00000d12
2291
2292 #define REG_A5XX_PC_PERFCTR_PC_SEL_3 0x00000d13
2293
2294 #define REG_A5XX_PC_PERFCTR_PC_SEL_4 0x00000d14
2295
2296 #define REG_A5XX_PC_PERFCTR_PC_SEL_5 0x00000d15
2297
2298 #define REG_A5XX_PC_PERFCTR_PC_SEL_6 0x00000d16
2299
2300 #define REG_A5XX_PC_PERFCTR_PC_SEL_7 0x00000d17
2301
2302 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0 0x00000e00
2303
2304 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1 0x00000e01
2305
2306 #define REG_A5XX_HLSQ_DBG_ECO_CNTL 0x00000e04
2307
2308 #define REG_A5XX_HLSQ_ADDR_MODE_CNTL 0x00000e05
2309
2310 #define REG_A5XX_HLSQ_MODE_CNTL 0x00000e06
2311
2312 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e10
2313
2314 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e11
2315
2316 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e12
2317
2318 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e13
2319
2320 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e14
2321
2322 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e15
2323
2324 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e16
2325
2326 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e17
2327
2328 #define REG_A5XX_HLSQ_SPTP_RDSEL 0x00000f08
2329
2330 #define REG_A5XX_HLSQ_DBG_READ_SEL 0x0000bc00
2331
2332 #define REG_A5XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000a000
2333
2334 #define REG_A5XX_VFD_ADDR_MODE_CNTL 0x00000e41
2335
2336 #define REG_A5XX_VFD_MODE_CNTL 0x00000e42
2337
2338 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_0 0x00000e50
2339
2340 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_1 0x00000e51
2341
2342 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_2 0x00000e52
2343
2344 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_3 0x00000e53
2345
2346 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_4 0x00000e54
2347
2348 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_5 0x00000e55
2349
2350 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_6 0x00000e56
2351
2352 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 0x00000e57
2353
2354 #define REG_A5XX_VPC_DBG_ECO_CNTL 0x00000e60
2355 #define A5XX_VPC_DBG_ECO_CNTL_ALLFLATOPTDIS 0x00000400
2356
2357 #define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61
2358
2359 #define REG_A5XX_VPC_MODE_CNTL 0x00000e62
2360 #define A5XX_VPC_MODE_CNTL_BINNING_PASS 0x00000001
2361
2362 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_0 0x00000e64
2363
2364 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_1 0x00000e65
2365
2366 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_2 0x00000e66
2367
2368 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_3 0x00000e67
2369
2370 #define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80
2371
2372 #define REG_A5XX_UCHE_MODE_CNTL 0x00000e81
2373
2374 #define REG_A5XX_UCHE_SVM_CNTL 0x00000e82
2375
2376 #define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87
2377
2378 #define REG_A5XX_UCHE_WRITE_THRU_BASE_HI 0x00000e88
2379
2380 #define REG_A5XX_UCHE_TRAP_BASE_LO 0x00000e89
2381
2382 #define REG_A5XX_UCHE_TRAP_BASE_HI 0x00000e8a
2383
2384 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e8b
2385
2386 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e8c
2387
2388 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e8d
2389
2390 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e8e
2391
2392 #define REG_A5XX_UCHE_DBG_ECO_CNTL_2 0x00000e8f
2393
2394 #define REG_A5XX_UCHE_DBG_ECO_CNTL 0x00000e90
2395
2396 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO 0x00000e91
2397
2398 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_HI 0x00000e92
2399
2400 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_LO 0x00000e93
2401
2402 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_HI 0x00000e94
2403
2404 #define REG_A5XX_UCHE_CACHE_INVALIDATE 0x00000e95
2405
2406 #define REG_A5XX_UCHE_CACHE_WAYS 0x00000e96
2407
2408 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000ea0
2409
2410 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000ea1
2411
2412 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000ea2
2413
2414 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000ea3
2415
2416 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000ea4
2417
2418 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000ea5
2419
2420 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000ea6
2421
2422 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000ea7
2423
2424 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_0 0x00000ea8
2425
2426 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_1 0x00000ea9
2427
2428 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_2 0x00000eaa
2429
2430 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_3 0x00000eab
2431
2432 #define REG_A5XX_UCHE_TRAP_LOG_LO 0x00000eb1
2433
2434 #define REG_A5XX_UCHE_TRAP_LOG_HI 0x00000eb2
2435
2436 #define REG_A5XX_SP_DBG_ECO_CNTL 0x00000ec0
2437
2438 #define REG_A5XX_SP_ADDR_MODE_CNTL 0x00000ec1
2439
2440 #define REG_A5XX_SP_MODE_CNTL 0x00000ec2
2441
2442 #define REG_A5XX_SP_PERFCTR_SP_SEL_0 0x00000ed0
2443
2444 #define REG_A5XX_SP_PERFCTR_SP_SEL_1 0x00000ed1
2445
2446 #define REG_A5XX_SP_PERFCTR_SP_SEL_2 0x00000ed2
2447
2448 #define REG_A5XX_SP_PERFCTR_SP_SEL_3 0x00000ed3
2449
2450 #define REG_A5XX_SP_PERFCTR_SP_SEL_4 0x00000ed4
2451
2452 #define REG_A5XX_SP_PERFCTR_SP_SEL_5 0x00000ed5
2453
2454 #define REG_A5XX_SP_PERFCTR_SP_SEL_6 0x00000ed6
2455
2456 #define REG_A5XX_SP_PERFCTR_SP_SEL_7 0x00000ed7
2457
2458 #define REG_A5XX_SP_PERFCTR_SP_SEL_8 0x00000ed8
2459
2460 #define REG_A5XX_SP_PERFCTR_SP_SEL_9 0x00000ed9
2461
2462 #define REG_A5XX_SP_PERFCTR_SP_SEL_10 0x00000eda
2463
2464 #define REG_A5XX_SP_PERFCTR_SP_SEL_11 0x00000edb
2465
2466 #define REG_A5XX_SP_POWERCTR_SP_SEL_0 0x00000edc
2467
2468 #define REG_A5XX_SP_POWERCTR_SP_SEL_1 0x00000edd
2469
2470 #define REG_A5XX_SP_POWERCTR_SP_SEL_2 0x00000ede
2471
2472 #define REG_A5XX_SP_POWERCTR_SP_SEL_3 0x00000edf
2473
2474 #define REG_A5XX_TPL1_ADDR_MODE_CNTL 0x00000f01
2475
2476 #define REG_A5XX_TPL1_MODE_CNTL 0x00000f02
2477
2478 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_0 0x00000f10
2479
2480 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_1 0x00000f11
2481
2482 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_2 0x00000f12
2483
2484 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_3 0x00000f13
2485
2486 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_4 0x00000f14
2487
2488 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_5 0x00000f15
2489
2490 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_6 0x00000f16
2491
2492 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_7 0x00000f17
2493
2494 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_0 0x00000f18
2495
2496 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_1 0x00000f19
2497
2498 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_2 0x00000f1a
2499
2500 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_3 0x00000f1b
2501
2502 #define REG_A5XX_VBIF_VERSION 0x00003000
2503
2504 #define REG_A5XX_VBIF_CLKON 0x00003001
2505
2506 #define REG_A5XX_VBIF_ABIT_SORT 0x00003028
2507
2508 #define REG_A5XX_VBIF_ABIT_SORT_CONF 0x00003029
2509
2510 #define REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
2511
2512 #define REG_A5XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
2513
2514 #define REG_A5XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
2515
2516 #define REG_A5XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
2517
2518 #define REG_A5XX_VBIF_XIN_HALT_CTRL0 0x00003080
2519
2520 #define REG_A5XX_VBIF_XIN_HALT_CTRL1 0x00003081
2521
2522 #define REG_A5XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084
2523
2524 #define REG_A5XX_VBIF_TEST_BUS1_CTRL0 0x00003085
2525
2526 #define REG_A5XX_VBIF_TEST_BUS1_CTRL1 0x00003086
2527
2528 #define REG_A5XX_VBIF_TEST_BUS2_CTRL0 0x00003087
2529
2530 #define REG_A5XX_VBIF_TEST_BUS2_CTRL1 0x00003088
2531
2532 #define REG_A5XX_VBIF_TEST_BUS_OUT 0x0000308c
2533
2534 #define REG_A5XX_VBIF_PERF_CNT_EN0 0x000030c0
2535
2536 #define REG_A5XX_VBIF_PERF_CNT_EN1 0x000030c1
2537
2538 #define REG_A5XX_VBIF_PERF_CNT_EN2 0x000030c2
2539
2540 #define REG_A5XX_VBIF_PERF_CNT_EN3 0x000030c3
2541
2542 #define REG_A5XX_VBIF_PERF_CNT_CLR0 0x000030c8
2543
2544 #define REG_A5XX_VBIF_PERF_CNT_CLR1 0x000030c9
2545
2546 #define REG_A5XX_VBIF_PERF_CNT_CLR2 0x000030ca
2547
2548 #define REG_A5XX_VBIF_PERF_CNT_CLR3 0x000030cb
2549
2550 #define REG_A5XX_VBIF_PERF_CNT_SEL0 0x000030d0
2551
2552 #define REG_A5XX_VBIF_PERF_CNT_SEL1 0x000030d1
2553
2554 #define REG_A5XX_VBIF_PERF_CNT_SEL2 0x000030d2
2555
2556 #define REG_A5XX_VBIF_PERF_CNT_SEL3 0x000030d3
2557
2558 #define REG_A5XX_VBIF_PERF_CNT_LOW0 0x000030d8
2559
2560 #define REG_A5XX_VBIF_PERF_CNT_LOW1 0x000030d9
2561
2562 #define REG_A5XX_VBIF_PERF_CNT_LOW2 0x000030da
2563
2564 #define REG_A5XX_VBIF_PERF_CNT_LOW3 0x000030db
2565
2566 #define REG_A5XX_VBIF_PERF_CNT_HIGH0 0x000030e0
2567
2568 #define REG_A5XX_VBIF_PERF_CNT_HIGH1 0x000030e1
2569
2570 #define REG_A5XX_VBIF_PERF_CNT_HIGH2 0x000030e2
2571
2572 #define REG_A5XX_VBIF_PERF_CNT_HIGH3 0x000030e3
2573
2574 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
2575
2576 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
2577
2578 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
2579
2580 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110
2581
2582 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111
2583
2584 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112
2585
2586 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118
2587
2588 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119
2589
2590 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
2591
2592 #define REG_A5XX_GPMU_INST_RAM_BASE 0x00008800
2593
2594 #define REG_A5XX_GPMU_DATA_RAM_BASE 0x00009800
2595
2596 #define REG_A5XX_GPMU_SP_POWER_CNTL 0x0000a881
2597
2598 #define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL 0x0000a886
2599
2600 #define REG_A5XX_GPMU_RBCCU_POWER_CNTL 0x0000a887
2601
2602 #define REG_A5XX_GPMU_SP_PWR_CLK_STATUS 0x0000a88b
2603 #define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON 0x00100000
2604
2605 #define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS 0x0000a88d
2606 #define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON 0x00100000
2607
2608 #define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY 0x0000a891
2609
2610 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL 0x0000a892
2611
2612 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST 0x0000a893
2613
2614 #define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL 0x0000a894
2615
2616 #define REG_A5XX_GPMU_WFI_CONFIG 0x0000a8c1
2617
2618 #define REG_A5XX_GPMU_RBBM_INTR_INFO 0x0000a8d6
2619
2620 #define REG_A5XX_GPMU_CM3_SYSRESET 0x0000a8d8
2621
2622 #define REG_A5XX_GPMU_GENERAL_0 0x0000a8e0
2623
2624 #define REG_A5XX_GPMU_GENERAL_1 0x0000a8e1
2625
2626 #define REG_A5XX_SP_POWER_COUNTER_0_LO 0x0000a840
2627
2628 #define REG_A5XX_SP_POWER_COUNTER_0_HI 0x0000a841
2629
2630 #define REG_A5XX_SP_POWER_COUNTER_1_LO 0x0000a842
2631
2632 #define REG_A5XX_SP_POWER_COUNTER_1_HI 0x0000a843
2633
2634 #define REG_A5XX_SP_POWER_COUNTER_2_LO 0x0000a844
2635
2636 #define REG_A5XX_SP_POWER_COUNTER_2_HI 0x0000a845
2637
2638 #define REG_A5XX_SP_POWER_COUNTER_3_LO 0x0000a846
2639
2640 #define REG_A5XX_SP_POWER_COUNTER_3_HI 0x0000a847
2641
2642 #define REG_A5XX_TP_POWER_COUNTER_0_LO 0x0000a848
2643
2644 #define REG_A5XX_TP_POWER_COUNTER_0_HI 0x0000a849
2645
2646 #define REG_A5XX_TP_POWER_COUNTER_1_LO 0x0000a84a
2647
2648 #define REG_A5XX_TP_POWER_COUNTER_1_HI 0x0000a84b
2649
2650 #define REG_A5XX_TP_POWER_COUNTER_2_LO 0x0000a84c
2651
2652 #define REG_A5XX_TP_POWER_COUNTER_2_HI 0x0000a84d
2653
2654 #define REG_A5XX_TP_POWER_COUNTER_3_LO 0x0000a84e
2655
2656 #define REG_A5XX_TP_POWER_COUNTER_3_HI 0x0000a84f
2657
2658 #define REG_A5XX_RB_POWER_COUNTER_0_LO 0x0000a850
2659
2660 #define REG_A5XX_RB_POWER_COUNTER_0_HI 0x0000a851
2661
2662 #define REG_A5XX_RB_POWER_COUNTER_1_LO 0x0000a852
2663
2664 #define REG_A5XX_RB_POWER_COUNTER_1_HI 0x0000a853
2665
2666 #define REG_A5XX_RB_POWER_COUNTER_2_LO 0x0000a854
2667
2668 #define REG_A5XX_RB_POWER_COUNTER_2_HI 0x0000a855
2669
2670 #define REG_A5XX_RB_POWER_COUNTER_3_LO 0x0000a856
2671
2672 #define REG_A5XX_RB_POWER_COUNTER_3_HI 0x0000a857
2673
2674 #define REG_A5XX_CCU_POWER_COUNTER_0_LO 0x0000a858
2675
2676 #define REG_A5XX_CCU_POWER_COUNTER_0_HI 0x0000a859
2677
2678 #define REG_A5XX_CCU_POWER_COUNTER_1_LO 0x0000a85a
2679
2680 #define REG_A5XX_CCU_POWER_COUNTER_1_HI 0x0000a85b
2681
2682 #define REG_A5XX_UCHE_POWER_COUNTER_0_LO 0x0000a85c
2683
2684 #define REG_A5XX_UCHE_POWER_COUNTER_0_HI 0x0000a85d
2685
2686 #define REG_A5XX_UCHE_POWER_COUNTER_1_LO 0x0000a85e
2687
2688 #define REG_A5XX_UCHE_POWER_COUNTER_1_HI 0x0000a85f
2689
2690 #define REG_A5XX_UCHE_POWER_COUNTER_2_LO 0x0000a860
2691
2692 #define REG_A5XX_UCHE_POWER_COUNTER_2_HI 0x0000a861
2693
2694 #define REG_A5XX_UCHE_POWER_COUNTER_3_LO 0x0000a862
2695
2696 #define REG_A5XX_UCHE_POWER_COUNTER_3_HI 0x0000a863
2697
2698 #define REG_A5XX_CP_POWER_COUNTER_0_LO 0x0000a864
2699
2700 #define REG_A5XX_CP_POWER_COUNTER_0_HI 0x0000a865
2701
2702 #define REG_A5XX_CP_POWER_COUNTER_1_LO 0x0000a866
2703
2704 #define REG_A5XX_CP_POWER_COUNTER_1_HI 0x0000a867
2705
2706 #define REG_A5XX_CP_POWER_COUNTER_2_LO 0x0000a868
2707
2708 #define REG_A5XX_CP_POWER_COUNTER_2_HI 0x0000a869
2709
2710 #define REG_A5XX_CP_POWER_COUNTER_3_LO 0x0000a86a
2711
2712 #define REG_A5XX_CP_POWER_COUNTER_3_HI 0x0000a86b
2713
2714 #define REG_A5XX_GPMU_POWER_COUNTER_0_LO 0x0000a86c
2715
2716 #define REG_A5XX_GPMU_POWER_COUNTER_0_HI 0x0000a86d
2717
2718 #define REG_A5XX_GPMU_POWER_COUNTER_1_LO 0x0000a86e
2719
2720 #define REG_A5XX_GPMU_POWER_COUNTER_1_HI 0x0000a86f
2721
2722 #define REG_A5XX_GPMU_POWER_COUNTER_2_LO 0x0000a870
2723
2724 #define REG_A5XX_GPMU_POWER_COUNTER_2_HI 0x0000a871
2725
2726 #define REG_A5XX_GPMU_POWER_COUNTER_3_LO 0x0000a872
2727
2728 #define REG_A5XX_GPMU_POWER_COUNTER_3_HI 0x0000a873
2729
2730 #define REG_A5XX_GPMU_POWER_COUNTER_4_LO 0x0000a874
2731
2732 #define REG_A5XX_GPMU_POWER_COUNTER_4_HI 0x0000a875
2733
2734 #define REG_A5XX_GPMU_POWER_COUNTER_5_LO 0x0000a876
2735
2736 #define REG_A5XX_GPMU_POWER_COUNTER_5_HI 0x0000a877
2737
2738 #define REG_A5XX_GPMU_POWER_COUNTER_ENABLE 0x0000a878
2739
2740 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_LO 0x0000a879
2741
2742 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_HI 0x0000a87a
2743
2744 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_RESET 0x0000a87b
2745
2746 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_0 0x0000a87c
2747
2748 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_1 0x0000a87d
2749
2750 #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3
2751
2752 #define REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL 0x0000a8a8
2753
2754 #define REG_A5XX_GPMU_TEMP_SENSOR_ID 0x0000ac00
2755
2756 #define REG_A5XX_GPMU_TEMP_SENSOR_CONFIG 0x0000ac01
2757
2758 #define REG_A5XX_GPMU_TEMP_VAL 0x0000ac02
2759
2760 #define REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD 0x0000ac03
2761
2762 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_STATUS 0x0000ac05
2763
2764 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK 0x0000ac06
2765
2766 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_0_1 0x0000ac40
2767
2768 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_2_3 0x0000ac41
2769
2770 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_0_1 0x0000ac42
2771
2772 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_2_3 0x0000ac43
2773
2774 #define REG_A5XX_GPMU_BASE_LEAKAGE 0x0000ac46
2775
2776 #define REG_A5XX_GPMU_GPMU_VOLTAGE 0x0000ac60
2777
2778 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_STATUS 0x0000ac61
2779
2780 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK 0x0000ac62
2781
2782 #define REG_A5XX_GPMU_GPMU_PWR_THRESHOLD 0x0000ac80
2783
2784 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL 0x0000acc4
2785
2786 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS 0x0000acc5
2787
2788 #define REG_A5XX_GDPM_CONFIG1 0x0000b80c
2789
2790 #define REG_A5XX_GDPM_CONFIG2 0x0000b80d
2791
2792 #define REG_A5XX_GDPM_INT_EN 0x0000b80f
2793
2794 #define REG_A5XX_GDPM_INT_MASK 0x0000b811
2795
2796 #define REG_A5XX_GPMU_BEC_ENABLE 0x0000b9a0
2797
2798 #define REG_A5XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000c41a
2799
2800 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000c41d
2801
2802 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000c41f
2803
2804 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x0000c421
2805
2806 #define REG_A5XX_GPU_CS_ENABLE_REG 0x0000c520
2807
2808 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x0000c557
2809
2810 #define REG_A5XX_GRAS_CL_CNTL 0x0000e000
2811 #define A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040
2812
2813 #define REG_A5XX_GRAS_VS_CL_CNTL 0x0000e001
2814 #define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
2815 #define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT 0
A5XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)2816 static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)
2817 {
2818 return ((val) << A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK;
2819 }
2820 #define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
2821 #define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT 8
A5XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)2822 static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)
2823 {
2824 return ((val) << A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK;
2825 }
2826
2827 #define REG_A5XX_UNKNOWN_E004 0x0000e004
2828
2829 #define REG_A5XX_GRAS_CNTL 0x0000e005
2830 #define A5XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001
2831 #define A5XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002
2832 #define A5XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004
2833 #define A5XX_GRAS_CNTL_SIZE 0x00000008
2834 #define A5XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0
2835 #define A5XX_GRAS_CNTL_COORD_MASK__SHIFT 6
A5XX_GRAS_CNTL_COORD_MASK(uint32_t val)2836 static inline uint32_t A5XX_GRAS_CNTL_COORD_MASK(uint32_t val)
2837 {
2838 return ((val) << A5XX_GRAS_CNTL_COORD_MASK__SHIFT) & A5XX_GRAS_CNTL_COORD_MASK__MASK;
2839 }
2840
2841 #define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x0000e006
2842 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff
2843 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0
A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)2844 static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
2845 {
2846 return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK;
2847 }
2848 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x000ffc00
2849 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10
A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)2850 static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
2851 {
2852 return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
2853 }
2854
2855 #define REG_A5XX_GRAS_CL_VPORT_XOFFSET_0 0x0000e010
2856 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
2857 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
A5XX_GRAS_CL_VPORT_XOFFSET_0(float val)2858 static inline uint32_t A5XX_GRAS_CL_VPORT_XOFFSET_0(float val)
2859 {
2860 return ((fui(val)) << A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
2861 }
2862
2863 #define REG_A5XX_GRAS_CL_VPORT_XSCALE_0 0x0000e011
2864 #define A5XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
2865 #define A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
A5XX_GRAS_CL_VPORT_XSCALE_0(float val)2866 static inline uint32_t A5XX_GRAS_CL_VPORT_XSCALE_0(float val)
2867 {
2868 return ((fui(val)) << A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_XSCALE_0__MASK;
2869 }
2870
2871 #define REG_A5XX_GRAS_CL_VPORT_YOFFSET_0 0x0000e012
2872 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
2873 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
A5XX_GRAS_CL_VPORT_YOFFSET_0(float val)2874 static inline uint32_t A5XX_GRAS_CL_VPORT_YOFFSET_0(float val)
2875 {
2876 return ((fui(val)) << A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
2877 }
2878
2879 #define REG_A5XX_GRAS_CL_VPORT_YSCALE_0 0x0000e013
2880 #define A5XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
2881 #define A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
A5XX_GRAS_CL_VPORT_YSCALE_0(float val)2882 static inline uint32_t A5XX_GRAS_CL_VPORT_YSCALE_0(float val)
2883 {
2884 return ((fui(val)) << A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_YSCALE_0__MASK;
2885 }
2886
2887 #define REG_A5XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000e014
2888 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
2889 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val)2890 static inline uint32_t A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
2891 {
2892 return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
2893 }
2894
2895 #define REG_A5XX_GRAS_CL_VPORT_ZSCALE_0 0x0000e015
2896 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
2897 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
A5XX_GRAS_CL_VPORT_ZSCALE_0(float val)2898 static inline uint32_t A5XX_GRAS_CL_VPORT_ZSCALE_0(float val)
2899 {
2900 return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
2901 }
2902
2903 #define REG_A5XX_GRAS_SU_CNTL 0x0000e090
2904 #define A5XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001
2905 #define A5XX_GRAS_SU_CNTL_CULL_BACK 0x00000002
2906 #define A5XX_GRAS_SU_CNTL_FRONT_CW 0x00000004
2907 #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8
2908 #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3
A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)2909 static inline uint32_t A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
2910 {
2911 return ((((int32_t)(val * 4.0))) << A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
2912 }
2913 #define A5XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800
2914 #define A5XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000
2915
2916 #define REG_A5XX_GRAS_SU_POINT_MINMAX 0x0000e091
2917 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
2918 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
A5XX_GRAS_SU_POINT_MINMAX_MIN(float val)2919 static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MIN(float val)
2920 {
2921 return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
2922 }
2923 #define A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
2924 #define A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
A5XX_GRAS_SU_POINT_MINMAX_MAX(float val)2925 static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MAX(float val)
2926 {
2927 return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
2928 }
2929
2930 #define REG_A5XX_GRAS_SU_POINT_SIZE 0x0000e092
2931 #define A5XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
2932 #define A5XX_GRAS_SU_POINT_SIZE__SHIFT 0
A5XX_GRAS_SU_POINT_SIZE(float val)2933 static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val)
2934 {
2935 return ((((int32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_SIZE__SHIFT) & A5XX_GRAS_SU_POINT_SIZE__MASK;
2936 }
2937
2938 #define REG_A5XX_GRAS_SU_LAYERED 0x0000e093
2939
2940 #define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL 0x0000e094
2941 #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
2942 #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1 0x00000002
2943
2944 #define REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000e095
2945 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
2946 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val)2947 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
2948 {
2949 return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
2950 }
2951
2952 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000e096
2953 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
2954 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)2955 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
2956 {
2957 return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
2958 }
2959
2960 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x0000e097
2961 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff
2962 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0
A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)2963 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
2964 {
2965 return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK;
2966 }
2967
2968 #define REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO 0x0000e098
2969 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
2970 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)2971 static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)
2972 {
2973 return ((val) << A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
2974 }
2975
2976 #define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x0000e099
2977
2978 #define REG_A5XX_GRAS_SC_CNTL 0x0000e0a0
2979 #define A5XX_GRAS_SC_CNTL_BINNING_PASS 0x00000001
2980 #define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED 0x00008000
2981
2982 #define REG_A5XX_GRAS_SC_BIN_CNTL 0x0000e0a1
2983
2984 #define REG_A5XX_GRAS_SC_RAS_MSAA_CNTL 0x0000e0a2
2985 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
2986 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)2987 static inline uint32_t A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2988 {
2989 return ((val) << A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK;
2990 }
2991
2992 #define REG_A5XX_GRAS_SC_DEST_MSAA_CNTL 0x0000e0a3
2993 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
2994 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)2995 static inline uint32_t A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2996 {
2997 return ((val) << A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK;
2998 }
2999 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
3000
3001 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL 0x0000e0a4
3002
3003 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0 0x0000e0aa
3004 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
3005 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK 0x00007fff
3006 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT 0
A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val)3007 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val)
3008 {
3009 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK;
3010 }
3011 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK 0x7fff0000
3012 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT 16
A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val)3013 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val)
3014 {
3015 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK;
3016 }
3017
3018 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0 0x0000e0ab
3019 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
3020 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK 0x00007fff
3021 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT 0
A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val)3022 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val)
3023 {
3024 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK;
3025 }
3026 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK 0x7fff0000
3027 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT 16
A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val)3028 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val)
3029 {
3030 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK;
3031 }
3032
3033 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 0x0000e0ca
3034 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
3035 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK 0x00007fff
3036 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT 0
A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val)3037 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val)
3038 {
3039 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK;
3040 }
3041 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK 0x7fff0000
3042 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT 16
A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val)3043 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val)
3044 {
3045 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK;
3046 }
3047
3048 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 0x0000e0cb
3049 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
3050 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK 0x00007fff
3051 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT 0
A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val)3052 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val)
3053 {
3054 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK;
3055 }
3056 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK 0x7fff0000
3057 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT 16
A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val)3058 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val)
3059 {
3060 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK;
3061 }
3062
3063 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000e0ea
3064 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
3065 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
3066 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)3067 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
3068 {
3069 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
3070 }
3071 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
3072 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)3073 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
3074 {
3075 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
3076 }
3077
3078 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000e0eb
3079 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
3080 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
3081 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)3082 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
3083 {
3084 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
3085 }
3086 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
3087 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)3088 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
3089 {
3090 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
3091 }
3092
3093 #define REG_A5XX_GRAS_LRZ_CNTL 0x0000e100
3094 #define A5XX_GRAS_LRZ_CNTL_ENABLE 0x00000001
3095 #define A5XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002
3096 #define A5XX_GRAS_LRZ_CNTL_GREATER 0x00000004
3097
3098 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO 0x0000e101
3099
3100 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_HI 0x0000e102
3101
3102 #define REG_A5XX_GRAS_LRZ_BUFFER_PITCH 0x0000e103
3103 #define A5XX_GRAS_LRZ_BUFFER_PITCH__MASK 0xffffffff
3104 #define A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT 0
A5XX_GRAS_LRZ_BUFFER_PITCH(uint32_t val)3105 static inline uint32_t A5XX_GRAS_LRZ_BUFFER_PITCH(uint32_t val)
3106 {
3107 return ((val >> 5) << A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT) & A5XX_GRAS_LRZ_BUFFER_PITCH__MASK;
3108 }
3109
3110 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x0000e104
3111
3112 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x0000e105
3113
3114 #define REG_A5XX_RB_CNTL 0x0000e140
3115 #define A5XX_RB_CNTL_WIDTH__MASK 0x000000ff
3116 #define A5XX_RB_CNTL_WIDTH__SHIFT 0
A5XX_RB_CNTL_WIDTH(uint32_t val)3117 static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val)
3118 {
3119 return ((val >> 5) << A5XX_RB_CNTL_WIDTH__SHIFT) & A5XX_RB_CNTL_WIDTH__MASK;
3120 }
3121 #define A5XX_RB_CNTL_HEIGHT__MASK 0x0001fe00
3122 #define A5XX_RB_CNTL_HEIGHT__SHIFT 9
A5XX_RB_CNTL_HEIGHT(uint32_t val)3123 static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val)
3124 {
3125 return ((val >> 5) << A5XX_RB_CNTL_HEIGHT__SHIFT) & A5XX_RB_CNTL_HEIGHT__MASK;
3126 }
3127 #define A5XX_RB_CNTL_BYPASS 0x00020000
3128
3129 #define REG_A5XX_RB_RENDER_CNTL 0x0000e141
3130 #define A5XX_RB_RENDER_CNTL_BINNING_PASS 0x00000001
3131 #define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED 0x00000040
3132 #define A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE 0x00000080
3133 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000
3134 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2 0x00008000
3135 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000
3136 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16
A5XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)3137 static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
3138 {
3139 return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
3140 }
3141 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK 0xff000000
3142 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT 24
A5XX_RB_RENDER_CNTL_FLAG_MRTS2(uint32_t val)3143 static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS2(uint32_t val)
3144 {
3145 return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK;
3146 }
3147
3148 #define REG_A5XX_RB_RAS_MSAA_CNTL 0x0000e142
3149 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
3150 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)3151 static inline uint32_t A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3152 {
3153 return ((val) << A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
3154 }
3155
3156 #define REG_A5XX_RB_DEST_MSAA_CNTL 0x0000e143
3157 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
3158 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)3159 static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3160 {
3161 return ((val) << A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK;
3162 }
3163 #define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
3164
3165 #define REG_A5XX_RB_RENDER_CONTROL0 0x0000e144
3166 #define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001
3167 #define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002
3168 #define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004
3169 #define A5XX_RB_RENDER_CONTROL0_SIZE 0x00000008
3170 #define A5XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0
3171 #define A5XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6
A5XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)3172 static inline uint32_t A5XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)
3173 {
3174 return ((val) << A5XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A5XX_RB_RENDER_CONTROL0_COORD_MASK__MASK;
3175 }
3176
3177 #define REG_A5XX_RB_RENDER_CONTROL1 0x0000e145
3178 #define A5XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001
3179 #define A5XX_RB_RENDER_CONTROL1_FACENESS 0x00000002
3180 #define A5XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000004
3181
3182 #define REG_A5XX_RB_FS_OUTPUT_CNTL 0x0000e146
3183 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
3184 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT 0
A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val)3185 static inline uint32_t A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val)
3186 {
3187 return ((val) << A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK;
3188 }
3189 #define A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z 0x00000020
3190
3191 #define REG_A5XX_RB_RENDER_COMPONENTS 0x0000e147
3192 #define A5XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
3193 #define A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
A5XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)3194 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
3195 {
3196 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT0__MASK;
3197 }
3198 #define A5XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
3199 #define A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
A5XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)3200 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
3201 {
3202 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT1__MASK;
3203 }
3204 #define A5XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
3205 #define A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
A5XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)3206 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
3207 {
3208 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT2__MASK;
3209 }
3210 #define A5XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
3211 #define A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
A5XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)3212 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
3213 {
3214 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT3__MASK;
3215 }
3216 #define A5XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
3217 #define A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
A5XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)3218 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
3219 {
3220 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT4__MASK;
3221 }
3222 #define A5XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
3223 #define A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
A5XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)3224 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
3225 {
3226 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT5__MASK;
3227 }
3228 #define A5XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
3229 #define A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
A5XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)3230 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
3231 {
3232 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT6__MASK;
3233 }
3234 #define A5XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
3235 #define A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)3236 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
3237 {
3238 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT7__MASK;
3239 }
3240
REG_A5XX_RB_MRT(uint32_t i0)3241 static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0) { return 0x0000e150 + 0x7*i0; }
3242
REG_A5XX_RB_MRT_CONTROL(uint32_t i0)3243 static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; }
3244 #define A5XX_RB_MRT_CONTROL_BLEND 0x00000001
3245 #define A5XX_RB_MRT_CONTROL_BLEND2 0x00000002
3246 #define A5XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004
3247 #define A5XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078
3248 #define A5XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3
A5XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)3249 static inline uint32_t A5XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
3250 {
3251 return ((val) << A5XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A5XX_RB_MRT_CONTROL_ROP_CODE__MASK;
3252 }
3253 #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780
3254 #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7
A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)3255 static inline uint32_t A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
3256 {
3257 return ((val) << A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
3258 }
3259
REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0)3260 static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x0000e151 + 0x7*i0; }
3261 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
3262 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)3263 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
3264 {
3265 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
3266 }
3267 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
3268 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)3269 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3270 {
3271 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
3272 }
3273 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
3274 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)3275 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
3276 {
3277 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
3278 }
3279 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
3280 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)3281 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
3282 {
3283 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
3284 }
3285 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
3286 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)3287 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3288 {
3289 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
3290 }
3291 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
3292 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)3293 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
3294 {
3295 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
3296 }
3297
REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0)3298 static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x0000e152 + 0x7*i0; }
3299 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff
3300 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)3301 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
3302 {
3303 return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
3304 }
3305 #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300
3306 #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8
A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val)3307 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val)
3308 {
3309 return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
3310 }
3311 #define A5XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00001800
3312 #define A5XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 11
A5XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)3313 static inline uint32_t A5XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
3314 {
3315 return ((val) << A5XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK;
3316 }
3317 #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000
3318 #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13
A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)3319 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3320 {
3321 return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
3322 }
3323 #define A5XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00008000
3324
REG_A5XX_RB_MRT_PITCH(uint32_t i0)3325 static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { return 0x0000e153 + 0x7*i0; }
3326 #define A5XX_RB_MRT_PITCH__MASK 0xffffffff
3327 #define A5XX_RB_MRT_PITCH__SHIFT 0
A5XX_RB_MRT_PITCH(uint32_t val)3328 static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val)
3329 {
3330 return ((val >> 6) << A5XX_RB_MRT_PITCH__SHIFT) & A5XX_RB_MRT_PITCH__MASK;
3331 }
3332
REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0)3333 static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e154 + 0x7*i0; }
3334 #define A5XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff
3335 #define A5XX_RB_MRT_ARRAY_PITCH__SHIFT 0
A5XX_RB_MRT_ARRAY_PITCH(uint32_t val)3336 static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val)
3337 {
3338 return ((val >> 6) << A5XX_RB_MRT_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_ARRAY_PITCH__MASK;
3339 }
3340
REG_A5XX_RB_MRT_BASE_LO(uint32_t i0)3341 static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x0000e155 + 0x7*i0; }
3342
REG_A5XX_RB_MRT_BASE_HI(uint32_t i0)3343 static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x0000e156 + 0x7*i0; }
3344
3345 #define REG_A5XX_RB_BLEND_RED 0x0000e1a0
3346 #define A5XX_RB_BLEND_RED_UINT__MASK 0x000000ff
3347 #define A5XX_RB_BLEND_RED_UINT__SHIFT 0
A5XX_RB_BLEND_RED_UINT(uint32_t val)3348 static inline uint32_t A5XX_RB_BLEND_RED_UINT(uint32_t val)
3349 {
3350 return ((val) << A5XX_RB_BLEND_RED_UINT__SHIFT) & A5XX_RB_BLEND_RED_UINT__MASK;
3351 }
3352 #define A5XX_RB_BLEND_RED_SINT__MASK 0x0000ff00
3353 #define A5XX_RB_BLEND_RED_SINT__SHIFT 8
A5XX_RB_BLEND_RED_SINT(uint32_t val)3354 static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val)
3355 {
3356 return ((val) << A5XX_RB_BLEND_RED_SINT__SHIFT) & A5XX_RB_BLEND_RED_SINT__MASK;
3357 }
3358 #define A5XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
3359 #define A5XX_RB_BLEND_RED_FLOAT__SHIFT 16
A5XX_RB_BLEND_RED_FLOAT(float val)3360 static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val)
3361 {
3362 return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK;
3363 }
3364
3365 #define REG_A5XX_RB_BLEND_RED_F32 0x0000e1a1
3366 #define A5XX_RB_BLEND_RED_F32__MASK 0xffffffff
3367 #define A5XX_RB_BLEND_RED_F32__SHIFT 0
A5XX_RB_BLEND_RED_F32(float val)3368 static inline uint32_t A5XX_RB_BLEND_RED_F32(float val)
3369 {
3370 return ((fui(val)) << A5XX_RB_BLEND_RED_F32__SHIFT) & A5XX_RB_BLEND_RED_F32__MASK;
3371 }
3372
3373 #define REG_A5XX_RB_BLEND_GREEN 0x0000e1a2
3374 #define A5XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff
3375 #define A5XX_RB_BLEND_GREEN_UINT__SHIFT 0
A5XX_RB_BLEND_GREEN_UINT(uint32_t val)3376 static inline uint32_t A5XX_RB_BLEND_GREEN_UINT(uint32_t val)
3377 {
3378 return ((val) << A5XX_RB_BLEND_GREEN_UINT__SHIFT) & A5XX_RB_BLEND_GREEN_UINT__MASK;
3379 }
3380 #define A5XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00
3381 #define A5XX_RB_BLEND_GREEN_SINT__SHIFT 8
A5XX_RB_BLEND_GREEN_SINT(uint32_t val)3382 static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val)
3383 {
3384 return ((val) << A5XX_RB_BLEND_GREEN_SINT__SHIFT) & A5XX_RB_BLEND_GREEN_SINT__MASK;
3385 }
3386 #define A5XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
3387 #define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
A5XX_RB_BLEND_GREEN_FLOAT(float val)3388 static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val)
3389 {
3390 return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK;
3391 }
3392
3393 #define REG_A5XX_RB_BLEND_GREEN_F32 0x0000e1a3
3394 #define A5XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
3395 #define A5XX_RB_BLEND_GREEN_F32__SHIFT 0
A5XX_RB_BLEND_GREEN_F32(float val)3396 static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val)
3397 {
3398 return ((fui(val)) << A5XX_RB_BLEND_GREEN_F32__SHIFT) & A5XX_RB_BLEND_GREEN_F32__MASK;
3399 }
3400
3401 #define REG_A5XX_RB_BLEND_BLUE 0x0000e1a4
3402 #define A5XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff
3403 #define A5XX_RB_BLEND_BLUE_UINT__SHIFT 0
A5XX_RB_BLEND_BLUE_UINT(uint32_t val)3404 static inline uint32_t A5XX_RB_BLEND_BLUE_UINT(uint32_t val)
3405 {
3406 return ((val) << A5XX_RB_BLEND_BLUE_UINT__SHIFT) & A5XX_RB_BLEND_BLUE_UINT__MASK;
3407 }
3408 #define A5XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00
3409 #define A5XX_RB_BLEND_BLUE_SINT__SHIFT 8
A5XX_RB_BLEND_BLUE_SINT(uint32_t val)3410 static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val)
3411 {
3412 return ((val) << A5XX_RB_BLEND_BLUE_SINT__SHIFT) & A5XX_RB_BLEND_BLUE_SINT__MASK;
3413 }
3414 #define A5XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
3415 #define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
A5XX_RB_BLEND_BLUE_FLOAT(float val)3416 static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val)
3417 {
3418 return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK;
3419 }
3420
3421 #define REG_A5XX_RB_BLEND_BLUE_F32 0x0000e1a5
3422 #define A5XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
3423 #define A5XX_RB_BLEND_BLUE_F32__SHIFT 0
A5XX_RB_BLEND_BLUE_F32(float val)3424 static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val)
3425 {
3426 return ((fui(val)) << A5XX_RB_BLEND_BLUE_F32__SHIFT) & A5XX_RB_BLEND_BLUE_F32__MASK;
3427 }
3428
3429 #define REG_A5XX_RB_BLEND_ALPHA 0x0000e1a6
3430 #define A5XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff
3431 #define A5XX_RB_BLEND_ALPHA_UINT__SHIFT 0
A5XX_RB_BLEND_ALPHA_UINT(uint32_t val)3432 static inline uint32_t A5XX_RB_BLEND_ALPHA_UINT(uint32_t val)
3433 {
3434 return ((val) << A5XX_RB_BLEND_ALPHA_UINT__SHIFT) & A5XX_RB_BLEND_ALPHA_UINT__MASK;
3435 }
3436 #define A5XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00
3437 #define A5XX_RB_BLEND_ALPHA_SINT__SHIFT 8
A5XX_RB_BLEND_ALPHA_SINT(uint32_t val)3438 static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val)
3439 {
3440 return ((val) << A5XX_RB_BLEND_ALPHA_SINT__SHIFT) & A5XX_RB_BLEND_ALPHA_SINT__MASK;
3441 }
3442 #define A5XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
3443 #define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
A5XX_RB_BLEND_ALPHA_FLOAT(float val)3444 static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val)
3445 {
3446 return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK;
3447 }
3448
3449 #define REG_A5XX_RB_BLEND_ALPHA_F32 0x0000e1a7
3450 #define A5XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
3451 #define A5XX_RB_BLEND_ALPHA_F32__SHIFT 0
A5XX_RB_BLEND_ALPHA_F32(float val)3452 static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val)
3453 {
3454 return ((fui(val)) << A5XX_RB_BLEND_ALPHA_F32__SHIFT) & A5XX_RB_BLEND_ALPHA_F32__MASK;
3455 }
3456
3457 #define REG_A5XX_RB_ALPHA_CONTROL 0x0000e1a8
3458 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
3459 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)3460 static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
3461 {
3462 return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
3463 }
3464 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
3465 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
3466 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)3467 static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
3468 {
3469 return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
3470 }
3471
3472 #define REG_A5XX_RB_BLEND_CNTL 0x0000e1a9
3473 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
3474 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)3475 static inline uint32_t A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
3476 {
3477 return ((val) << A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
3478 }
3479 #define A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100
3480 #define A5XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
3481 #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000
3482 #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16
A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)3483 static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
3484 {
3485 return ((val) << A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
3486 }
3487
3488 #define REG_A5XX_RB_DEPTH_PLANE_CNTL 0x0000e1b0
3489 #define A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
3490 #define A5XX_RB_DEPTH_PLANE_CNTL_UNK1 0x00000002
3491
3492 #define REG_A5XX_RB_DEPTH_CNTL 0x0000e1b1
3493 #define A5XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001
3494 #define A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002
3495 #define A5XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c
3496 #define A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2
A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)3497 static inline uint32_t A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
3498 {
3499 return ((val) << A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A5XX_RB_DEPTH_CNTL_ZFUNC__MASK;
3500 }
3501 #define A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040
3502
3503 #define REG_A5XX_RB_DEPTH_BUFFER_INFO 0x0000e1b2
3504 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
3505 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)3506 static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)
3507 {
3508 return ((val) << A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
3509 }
3510
3511 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_LO 0x0000e1b3
3512
3513 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_HI 0x0000e1b4
3514
3515 #define REG_A5XX_RB_DEPTH_BUFFER_PITCH 0x0000e1b5
3516 #define A5XX_RB_DEPTH_BUFFER_PITCH__MASK 0xffffffff
3517 #define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0
A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)3518 static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
3519 {
3520 return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK;
3521 }
3522
3523 #define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x0000e1b6
3524 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0xffffffff
3525 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0
A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)3526 static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
3527 {
3528 return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
3529 }
3530
3531 #define REG_A5XX_RB_STENCIL_CONTROL 0x0000e1c0
3532 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
3533 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
3534 #define A5XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
3535 #define A5XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
3536 #define A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)3537 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
3538 {
3539 return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC__MASK;
3540 }
3541 #define A5XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
3542 #define A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)3543 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
3544 {
3545 return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL__MASK;
3546 }
3547 #define A5XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
3548 #define A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)3549 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
3550 {
3551 return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS__MASK;
3552 }
3553 #define A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
3554 #define A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)3555 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
3556 {
3557 return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
3558 }
3559 #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
3560 #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)3561 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
3562 {
3563 return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
3564 }
3565 #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
3566 #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)3567 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
3568 {
3569 return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
3570 }
3571 #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
3572 #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)3573 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
3574 {
3575 return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
3576 }
3577 #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
3578 #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)3579 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
3580 {
3581 return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
3582 }
3583
3584 #define REG_A5XX_RB_STENCIL_INFO 0x0000e1c1
3585 #define A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
3586
3587 #define REG_A5XX_RB_STENCIL_BASE_LO 0x0000e1c2
3588
3589 #define REG_A5XX_RB_STENCIL_BASE_HI 0x0000e1c3
3590
3591 #define REG_A5XX_RB_STENCIL_PITCH 0x0000e1c4
3592 #define A5XX_RB_STENCIL_PITCH__MASK 0xffffffff
3593 #define A5XX_RB_STENCIL_PITCH__SHIFT 0
A5XX_RB_STENCIL_PITCH(uint32_t val)3594 static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val)
3595 {
3596 return ((val >> 6) << A5XX_RB_STENCIL_PITCH__SHIFT) & A5XX_RB_STENCIL_PITCH__MASK;
3597 }
3598
3599 #define REG_A5XX_RB_STENCIL_ARRAY_PITCH 0x0000e1c5
3600 #define A5XX_RB_STENCIL_ARRAY_PITCH__MASK 0xffffffff
3601 #define A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT 0
A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val)3602 static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val)
3603 {
3604 return ((val >> 6) << A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT) & A5XX_RB_STENCIL_ARRAY_PITCH__MASK;
3605 }
3606
3607 #define REG_A5XX_RB_STENCILREFMASK 0x0000e1c6
3608 #define A5XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
3609 #define A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)3610 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
3611 {
3612 return ((val) << A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILREF__MASK;
3613 }
3614 #define A5XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
3615 #define A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)3616 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
3617 {
3618 return ((val) << A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILMASK__MASK;
3619 }
3620 #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
3621 #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)3622 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
3623 {
3624 return ((val) << A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
3625 }
3626
3627 #define REG_A5XX_RB_STENCILREFMASK_BF 0x0000e1c7
3628 #define A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
3629 #define A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
A5XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)3630 static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
3631 {
3632 return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
3633 }
3634 #define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
3635 #define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
A5XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)3636 static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
3637 {
3638 return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
3639 }
3640 #define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
3641 #define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)3642 static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
3643 {
3644 return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
3645 }
3646
3647 #define REG_A5XX_RB_WINDOW_OFFSET 0x0000e1d0
3648 #define A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
3649 #define A5XX_RB_WINDOW_OFFSET_X__MASK 0x00007fff
3650 #define A5XX_RB_WINDOW_OFFSET_X__SHIFT 0
A5XX_RB_WINDOW_OFFSET_X(uint32_t val)3651 static inline uint32_t A5XX_RB_WINDOW_OFFSET_X(uint32_t val)
3652 {
3653 return ((val) << A5XX_RB_WINDOW_OFFSET_X__SHIFT) & A5XX_RB_WINDOW_OFFSET_X__MASK;
3654 }
3655 #define A5XX_RB_WINDOW_OFFSET_Y__MASK 0x7fff0000
3656 #define A5XX_RB_WINDOW_OFFSET_Y__SHIFT 16
A5XX_RB_WINDOW_OFFSET_Y(uint32_t val)3657 static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val)
3658 {
3659 return ((val) << A5XX_RB_WINDOW_OFFSET_Y__SHIFT) & A5XX_RB_WINDOW_OFFSET_Y__MASK;
3660 }
3661
3662 #define REG_A5XX_RB_SAMPLE_COUNT_CONTROL 0x0000e1d1
3663 #define A5XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
3664
3665 #define REG_A5XX_RB_BLIT_CNTL 0x0000e210
3666 #define A5XX_RB_BLIT_CNTL_BUF__MASK 0x0000000f
3667 #define A5XX_RB_BLIT_CNTL_BUF__SHIFT 0
A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val)3668 static inline uint32_t A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val)
3669 {
3670 return ((val) << A5XX_RB_BLIT_CNTL_BUF__SHIFT) & A5XX_RB_BLIT_CNTL_BUF__MASK;
3671 }
3672
3673 #define REG_A5XX_RB_RESOLVE_CNTL_1 0x0000e211
3674 #define A5XX_RB_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE 0x80000000
3675 #define A5XX_RB_RESOLVE_CNTL_1_X__MASK 0x00007fff
3676 #define A5XX_RB_RESOLVE_CNTL_1_X__SHIFT 0
A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val)3677 static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val)
3678 {
3679 return ((val) << A5XX_RB_RESOLVE_CNTL_1_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_X__MASK;
3680 }
3681 #define A5XX_RB_RESOLVE_CNTL_1_Y__MASK 0x7fff0000
3682 #define A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT 16
A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val)3683 static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val)
3684 {
3685 return ((val) << A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_Y__MASK;
3686 }
3687
3688 #define REG_A5XX_RB_RESOLVE_CNTL_2 0x0000e212
3689 #define A5XX_RB_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE 0x80000000
3690 #define A5XX_RB_RESOLVE_CNTL_2_X__MASK 0x00007fff
3691 #define A5XX_RB_RESOLVE_CNTL_2_X__SHIFT 0
A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val)3692 static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val)
3693 {
3694 return ((val) << A5XX_RB_RESOLVE_CNTL_2_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_X__MASK;
3695 }
3696 #define A5XX_RB_RESOLVE_CNTL_2_Y__MASK 0x7fff0000
3697 #define A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT 16
A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val)3698 static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val)
3699 {
3700 return ((val) << A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_Y__MASK;
3701 }
3702
3703 #define REG_A5XX_RB_RESOLVE_CNTL_3 0x0000e213
3704 #define A5XX_RB_RESOLVE_CNTL_3_TILED 0x00000001
3705
3706 #define REG_A5XX_RB_BLIT_DST_LO 0x0000e214
3707
3708 #define REG_A5XX_RB_BLIT_DST_HI 0x0000e215
3709
3710 #define REG_A5XX_RB_BLIT_DST_PITCH 0x0000e216
3711 #define A5XX_RB_BLIT_DST_PITCH__MASK 0xffffffff
3712 #define A5XX_RB_BLIT_DST_PITCH__SHIFT 0
A5XX_RB_BLIT_DST_PITCH(uint32_t val)3713 static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val)
3714 {
3715 return ((val >> 6) << A5XX_RB_BLIT_DST_PITCH__SHIFT) & A5XX_RB_BLIT_DST_PITCH__MASK;
3716 }
3717
3718 #define REG_A5XX_RB_BLIT_DST_ARRAY_PITCH 0x0000e217
3719 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0xffffffff
3720 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0
A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)3721 static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
3722 {
3723 return ((val >> 6) << A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
3724 }
3725
3726 #define REG_A5XX_RB_CLEAR_COLOR_DW0 0x0000e218
3727
3728 #define REG_A5XX_RB_CLEAR_COLOR_DW1 0x0000e219
3729
3730 #define REG_A5XX_RB_CLEAR_COLOR_DW2 0x0000e21a
3731
3732 #define REG_A5XX_RB_CLEAR_COLOR_DW3 0x0000e21b
3733
3734 #define REG_A5XX_RB_CLEAR_CNTL 0x0000e21c
3735 #define A5XX_RB_CLEAR_CNTL_FAST_CLEAR 0x00000002
3736 #define A5XX_RB_CLEAR_CNTL_MSAA_RESOLVE 0x00000004
3737 #define A5XX_RB_CLEAR_CNTL_MASK__MASK 0x000000f0
3738 #define A5XX_RB_CLEAR_CNTL_MASK__SHIFT 4
A5XX_RB_CLEAR_CNTL_MASK(uint32_t val)3739 static inline uint32_t A5XX_RB_CLEAR_CNTL_MASK(uint32_t val)
3740 {
3741 return ((val) << A5XX_RB_CLEAR_CNTL_MASK__SHIFT) & A5XX_RB_CLEAR_CNTL_MASK__MASK;
3742 }
3743
3744 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x0000e240
3745
3746 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x0000e241
3747
3748 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x0000e242
3749
REG_A5XX_RB_MRT_FLAG_BUFFER(uint32_t i0)3750 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x0000e243 + 0x4*i0; }
3751
REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0)3752 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x0000e243 + 0x4*i0; }
3753
REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0)3754 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x0000e244 + 0x4*i0; }
3755
REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0)3756 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x0000e245 + 0x4*i0; }
3757 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK 0xffffffff
3758 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT 0
A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val)3759 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val)
3760 {
3761 return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK;
3762 }
3763
REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0)3764 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { return 0x0000e246 + 0x4*i0; }
3765 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK 0xffffffff
3766 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)3767 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
3768 {
3769 return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK;
3770 }
3771
3772 #define REG_A5XX_RB_BLIT_FLAG_DST_LO 0x0000e263
3773
3774 #define REG_A5XX_RB_BLIT_FLAG_DST_HI 0x0000e264
3775
3776 #define REG_A5XX_RB_BLIT_FLAG_DST_PITCH 0x0000e265
3777 #define A5XX_RB_BLIT_FLAG_DST_PITCH__MASK 0xffffffff
3778 #define A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT 0
A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val)3779 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val)
3780 {
3781 return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_PITCH__MASK;
3782 }
3783
3784 #define REG_A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH 0x0000e266
3785 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK 0xffffffff
3786 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT 0
A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val)3787 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val)
3788 {
3789 return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK;
3790 }
3791
3792 #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO 0x0000e267
3793
3794 #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_HI 0x0000e268
3795
3796 #define REG_A5XX_VPC_CNTL_0 0x0000e280
3797 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK 0x0000007f
3798 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT 0
A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val)3799 static inline uint32_t A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val)
3800 {
3801 return ((val) << A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT) & A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK;
3802 }
3803 #define A5XX_VPC_CNTL_0_VARYING 0x00000800
3804
REG_A5XX_VPC_VARYING_INTERP(uint32_t i0)3805 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x0000e282 + 0x1*i0; }
3806
REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0)3807 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x0000e282 + 0x1*i0; }
3808
REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0)3809 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000e28a + 0x1*i0; }
3810
REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0)3811 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000e28a + 0x1*i0; }
3812
3813 #define REG_A5XX_UNKNOWN_E292 0x0000e292
3814
3815 #define REG_A5XX_UNKNOWN_E293 0x0000e293
3816
REG_A5XX_VPC_VAR(uint32_t i0)3817 static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
3818
REG_A5XX_VPC_VAR_DISABLE(uint32_t i0)3819 static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
3820
3821 #define REG_A5XX_VPC_GS_SIV_CNTL 0x0000e298
3822
3823 #define REG_A5XX_VPC_CLIP_CNTL 0x0000e29a
3824 #define A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
3825 #define A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT 0
A5XX_VPC_CLIP_CNTL_CLIP_MASK(uint32_t val)3826 static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_MASK(uint32_t val)
3827 {
3828 return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK;
3829 }
3830 #define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00
3831 #define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8
A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)3832 static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
3833 {
3834 return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
3835 }
3836 #define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000
3837 #define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16
A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)3838 static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
3839 {
3840 return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
3841 }
3842
3843 #define REG_A5XX_VPC_PACK 0x0000e29d
3844 #define A5XX_VPC_PACK_NUMNONPOSVAR__MASK 0x000000ff
3845 #define A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT 0
A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val)3846 static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val)
3847 {
3848 return ((val) << A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A5XX_VPC_PACK_NUMNONPOSVAR__MASK;
3849 }
3850 #define A5XX_VPC_PACK_PSIZELOC__MASK 0x0000ff00
3851 #define A5XX_VPC_PACK_PSIZELOC__SHIFT 8
A5XX_VPC_PACK_PSIZELOC(uint32_t val)3852 static inline uint32_t A5XX_VPC_PACK_PSIZELOC(uint32_t val)
3853 {
3854 return ((val) << A5XX_VPC_PACK_PSIZELOC__SHIFT) & A5XX_VPC_PACK_PSIZELOC__MASK;
3855 }
3856
3857 #define REG_A5XX_VPC_FS_PRIMITIVEID_CNTL 0x0000e2a0
3858
3859 #define REG_A5XX_VPC_SO_BUF_CNTL 0x0000e2a1
3860 #define A5XX_VPC_SO_BUF_CNTL_BUF0 0x00000001
3861 #define A5XX_VPC_SO_BUF_CNTL_BUF1 0x00000008
3862 #define A5XX_VPC_SO_BUF_CNTL_BUF2 0x00000040
3863 #define A5XX_VPC_SO_BUF_CNTL_BUF3 0x00000200
3864 #define A5XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000
3865
3866 #define REG_A5XX_VPC_SO_OVERRIDE 0x0000e2a2
3867 #define A5XX_VPC_SO_OVERRIDE_SO_DISABLE 0x00000001
3868
3869 #define REG_A5XX_VPC_SO_CNTL 0x0000e2a3
3870 #define A5XX_VPC_SO_CNTL_ENABLE 0x00010000
3871
3872 #define REG_A5XX_VPC_SO_PROG 0x0000e2a4
3873 #define A5XX_VPC_SO_PROG_A_BUF__MASK 0x00000003
3874 #define A5XX_VPC_SO_PROG_A_BUF__SHIFT 0
A5XX_VPC_SO_PROG_A_BUF(uint32_t val)3875 static inline uint32_t A5XX_VPC_SO_PROG_A_BUF(uint32_t val)
3876 {
3877 return ((val) << A5XX_VPC_SO_PROG_A_BUF__SHIFT) & A5XX_VPC_SO_PROG_A_BUF__MASK;
3878 }
3879 #define A5XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc
3880 #define A5XX_VPC_SO_PROG_A_OFF__SHIFT 2
A5XX_VPC_SO_PROG_A_OFF(uint32_t val)3881 static inline uint32_t A5XX_VPC_SO_PROG_A_OFF(uint32_t val)
3882 {
3883 return ((val >> 2) << A5XX_VPC_SO_PROG_A_OFF__SHIFT) & A5XX_VPC_SO_PROG_A_OFF__MASK;
3884 }
3885 #define A5XX_VPC_SO_PROG_A_EN 0x00000800
3886 #define A5XX_VPC_SO_PROG_B_BUF__MASK 0x00003000
3887 #define A5XX_VPC_SO_PROG_B_BUF__SHIFT 12
A5XX_VPC_SO_PROG_B_BUF(uint32_t val)3888 static inline uint32_t A5XX_VPC_SO_PROG_B_BUF(uint32_t val)
3889 {
3890 return ((val) << A5XX_VPC_SO_PROG_B_BUF__SHIFT) & A5XX_VPC_SO_PROG_B_BUF__MASK;
3891 }
3892 #define A5XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000
3893 #define A5XX_VPC_SO_PROG_B_OFF__SHIFT 14
A5XX_VPC_SO_PROG_B_OFF(uint32_t val)3894 static inline uint32_t A5XX_VPC_SO_PROG_B_OFF(uint32_t val)
3895 {
3896 return ((val >> 2) << A5XX_VPC_SO_PROG_B_OFF__SHIFT) & A5XX_VPC_SO_PROG_B_OFF__MASK;
3897 }
3898 #define A5XX_VPC_SO_PROG_B_EN 0x00800000
3899
REG_A5XX_VPC_SO(uint32_t i0)3900 static inline uint32_t REG_A5XX_VPC_SO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }
3901
REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0)3902 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }
3903
REG_A5XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0)3904 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000e2a8 + 0x7*i0; }
3905
REG_A5XX_VPC_SO_BUFFER_SIZE(uint32_t i0)3906 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000e2a9 + 0x7*i0; }
3907
REG_A5XX_VPC_SO_NCOMP(uint32_t i0)3908 static inline uint32_t REG_A5XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000e2aa + 0x7*i0; }
3909
REG_A5XX_VPC_SO_BUFFER_OFFSET(uint32_t i0)3910 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000e2ab + 0x7*i0; }
3911
REG_A5XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0)3912 static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000e2ac + 0x7*i0; }
3913
REG_A5XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0)3914 static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x0000e2ad + 0x7*i0; }
3915
3916 #define REG_A5XX_PC_PRIMITIVE_CNTL 0x0000e384
3917 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK 0x0000007f
3918 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT 0
A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val)3919 static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val)
3920 {
3921 return ((val) << A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK;
3922 }
3923 #define A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART 0x00000100
3924 #define A5XX_PC_PRIMITIVE_CNTL_COUNT_PRIMITIVES 0x00000200
3925 #define A5XX_PC_PRIMITIVE_CNTL_PROVOKING_VTX_LAST 0x00000400
3926
3927 #define REG_A5XX_PC_PRIM_VTX_CNTL 0x0000e385
3928 #define A5XX_PC_PRIM_VTX_CNTL_PSIZE 0x00000800
3929
3930 #define REG_A5XX_PC_RASTER_CNTL 0x0000e388
3931 #define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x00000007
3932 #define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 0
A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)3933 static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
3934 {
3935 return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK;
3936 }
3937 #define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000038
3938 #define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT 3
A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)3939 static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
3940 {
3941 return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK;
3942 }
3943 #define A5XX_PC_RASTER_CNTL_POLYMODE_ENABLE 0x00000040
3944
3945 #define REG_A5XX_PC_CLIP_CNTL 0x0000e389
3946 #define A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
3947 #define A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT 0
A5XX_PC_CLIP_CNTL_CLIP_MASK(uint32_t val)3948 static inline uint32_t A5XX_PC_CLIP_CNTL_CLIP_MASK(uint32_t val)
3949 {
3950 return ((val) << A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK;
3951 }
3952
3953 #define REG_A5XX_PC_RESTART_INDEX 0x0000e38c
3954
3955 #define REG_A5XX_PC_GS_LAYERED 0x0000e38d
3956
3957 #define REG_A5XX_PC_GS_PARAM 0x0000e38e
3958 #define A5XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff
3959 #define A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0
A5XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)3960 static inline uint32_t A5XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
3961 {
3962 return ((val) << A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A5XX_PC_GS_PARAM_MAX_VERTICES__MASK;
3963 }
3964 #define A5XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800
3965 #define A5XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11
A5XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)3966 static inline uint32_t A5XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
3967 {
3968 return ((val) << A5XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A5XX_PC_GS_PARAM_INVOCATIONS__MASK;
3969 }
3970 #define A5XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000
3971 #define A5XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23
A5XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)3972 static inline uint32_t A5XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
3973 {
3974 return ((val) << A5XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A5XX_PC_GS_PARAM_PRIMTYPE__MASK;
3975 }
3976
3977 #define REG_A5XX_PC_HS_PARAM 0x0000e38f
3978 #define A5XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f
3979 #define A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0
A5XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)3980 static inline uint32_t A5XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
3981 {
3982 return ((val) << A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A5XX_PC_HS_PARAM_VERTICES_OUT__MASK;
3983 }
3984 #define A5XX_PC_HS_PARAM_SPACING__MASK 0x00600000
3985 #define A5XX_PC_HS_PARAM_SPACING__SHIFT 21
A5XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)3986 static inline uint32_t A5XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
3987 {
3988 return ((val) << A5XX_PC_HS_PARAM_SPACING__SHIFT) & A5XX_PC_HS_PARAM_SPACING__MASK;
3989 }
3990 #define A5XX_PC_HS_PARAM_CW 0x00800000
3991 #define A5XX_PC_HS_PARAM_CONNECTED 0x01000000
3992
3993 #define REG_A5XX_PC_POWER_CNTL 0x0000e3b0
3994
3995 #define REG_A5XX_VFD_CONTROL_0 0x0000e400
3996 #define A5XX_VFD_CONTROL_0_VTXCNT__MASK 0x0000003f
3997 #define A5XX_VFD_CONTROL_0_VTXCNT__SHIFT 0
A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val)3998 static inline uint32_t A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val)
3999 {
4000 return ((val) << A5XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A5XX_VFD_CONTROL_0_VTXCNT__MASK;
4001 }
4002
4003 #define REG_A5XX_VFD_CONTROL_1 0x0000e401
4004 #define A5XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff
4005 #define A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0
A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)4006 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
4007 {
4008 return ((val) << A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A5XX_VFD_CONTROL_1_REGID4VTX__MASK;
4009 }
4010 #define A5XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00
4011 #define A5XX_VFD_CONTROL_1_REGID4INST__SHIFT 8
A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val)4012 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
4013 {
4014 return ((val) << A5XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A5XX_VFD_CONTROL_1_REGID4INST__MASK;
4015 }
4016 #define A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000
4017 #define A5XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16
A5XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)4018 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)
4019 {
4020 return ((val) << A5XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK;
4021 }
4022
4023 #define REG_A5XX_VFD_CONTROL_2 0x0000e402
4024 #define A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK 0x000000ff
4025 #define A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT 0
A5XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val)4026 static inline uint32_t A5XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val)
4027 {
4028 return ((val) << A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT) & A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK;
4029 }
4030
4031 #define REG_A5XX_VFD_CONTROL_3 0x0000e403
4032 #define A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK 0x0000ff00
4033 #define A5XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT 8
A5XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val)4034 static inline uint32_t A5XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val)
4035 {
4036 return ((val) << A5XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT) & A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK;
4037 }
4038 #define A5XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
4039 #define A5XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
A5XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)4040 static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
4041 {
4042 return ((val) << A5XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A5XX_VFD_CONTROL_3_REGID_TESSX__MASK;
4043 }
4044 #define A5XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
4045 #define A5XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
A5XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)4046 static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
4047 {
4048 return ((val) << A5XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A5XX_VFD_CONTROL_3_REGID_TESSY__MASK;
4049 }
4050
4051 #define REG_A5XX_VFD_CONTROL_4 0x0000e404
4052
4053 #define REG_A5XX_VFD_CONTROL_5 0x0000e405
4054
4055 #define REG_A5XX_VFD_INDEX_OFFSET 0x0000e408
4056
4057 #define REG_A5XX_VFD_INSTANCE_START_OFFSET 0x0000e409
4058
REG_A5XX_VFD_FETCH(uint32_t i0)4059 static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0) { return 0x0000e40a + 0x4*i0; }
4060
REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0)4061 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000e40a + 0x4*i0; }
4062
REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0)4063 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000e40b + 0x4*i0; }
4064
REG_A5XX_VFD_FETCH_SIZE(uint32_t i0)4065 static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000e40c + 0x4*i0; }
4066
REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0)4067 static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000e40d + 0x4*i0; }
4068
REG_A5XX_VFD_DECODE(uint32_t i0)4069 static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0) { return 0x0000e48a + 0x2*i0; }
4070
REG_A5XX_VFD_DECODE_INSTR(uint32_t i0)4071 static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000e48a + 0x2*i0; }
4072 #define A5XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f
4073 #define A5XX_VFD_DECODE_INSTR_IDX__SHIFT 0
A5XX_VFD_DECODE_INSTR_IDX(uint32_t val)4074 static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val)
4075 {
4076 return ((val) << A5XX_VFD_DECODE_INSTR_IDX__SHIFT) & A5XX_VFD_DECODE_INSTR_IDX__MASK;
4077 }
4078 #define A5XX_VFD_DECODE_INSTR_INSTANCED 0x00020000
4079 #define A5XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000
4080 #define A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20
A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val)4081 static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val)
4082 {
4083 return ((val) << A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A5XX_VFD_DECODE_INSTR_FORMAT__MASK;
4084 }
4085 #define A5XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000
4086 #define A5XX_VFD_DECODE_INSTR_SWAP__SHIFT 28
A5XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)4087 static inline uint32_t A5XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
4088 {
4089 return ((val) << A5XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A5XX_VFD_DECODE_INSTR_SWAP__MASK;
4090 }
4091 #define A5XX_VFD_DECODE_INSTR_UNK30 0x40000000
4092 #define A5XX_VFD_DECODE_INSTR_FLOAT 0x80000000
4093
REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0)4094 static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; }
4095
REG_A5XX_VFD_DEST_CNTL(uint32_t i0)4096 static inline uint32_t REG_A5XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }
4097
REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0)4098 static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }
4099 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f
4100 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0
A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)4101 static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)
4102 {
4103 return ((val) << A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK;
4104 }
4105 #define A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0
4106 #define A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4
A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)4107 static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
4108 {
4109 return ((val) << A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
4110 }
4111
4112 #define REG_A5XX_VFD_POWER_CNTL 0x0000e4f0
4113
4114 #define REG_A5XX_SP_SP_CNTL 0x0000e580
4115
4116 #define REG_A5XX_SP_VS_CONFIG 0x0000e584
4117 #define A5XX_SP_VS_CONFIG_ENABLED 0x00000001
4118 #define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4119 #define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)4120 static inline uint32_t A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4121 {
4122 return ((val) << A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK;
4123 }
4124 #define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4125 #define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8
A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(uint32_t val)4126 static inline uint32_t A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4127 {
4128 return ((val) << A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK;
4129 }
4130
4131 #define REG_A5XX_SP_FS_CONFIG 0x0000e585
4132 #define A5XX_SP_FS_CONFIG_ENABLED 0x00000001
4133 #define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4134 #define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)4135 static inline uint32_t A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4136 {
4137 return ((val) << A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK;
4138 }
4139 #define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4140 #define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8
A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(uint32_t val)4141 static inline uint32_t A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4142 {
4143 return ((val) << A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK;
4144 }
4145
4146 #define REG_A5XX_SP_HS_CONFIG 0x0000e586
4147 #define A5XX_SP_HS_CONFIG_ENABLED 0x00000001
4148 #define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4149 #define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)4150 static inline uint32_t A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4151 {
4152 return ((val) << A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK;
4153 }
4154 #define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4155 #define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8
A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(uint32_t val)4156 static inline uint32_t A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4157 {
4158 return ((val) << A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK;
4159 }
4160
4161 #define REG_A5XX_SP_DS_CONFIG 0x0000e587
4162 #define A5XX_SP_DS_CONFIG_ENABLED 0x00000001
4163 #define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4164 #define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)4165 static inline uint32_t A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4166 {
4167 return ((val) << A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK;
4168 }
4169 #define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4170 #define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8
A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(uint32_t val)4171 static inline uint32_t A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4172 {
4173 return ((val) << A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK;
4174 }
4175
4176 #define REG_A5XX_SP_GS_CONFIG 0x0000e588
4177 #define A5XX_SP_GS_CONFIG_ENABLED 0x00000001
4178 #define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4179 #define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)4180 static inline uint32_t A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4181 {
4182 return ((val) << A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK;
4183 }
4184 #define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4185 #define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8
A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(uint32_t val)4186 static inline uint32_t A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4187 {
4188 return ((val) << A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK;
4189 }
4190
4191 #define REG_A5XX_SP_CS_CONFIG 0x0000e589
4192 #define A5XX_SP_CS_CONFIG_ENABLED 0x00000001
4193 #define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4194 #define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)4195 static inline uint32_t A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4196 {
4197 return ((val) << A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK;
4198 }
4199 #define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4200 #define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8
A5XX_SP_CS_CONFIG_SHADEROBJOFFSET(uint32_t val)4201 static inline uint32_t A5XX_SP_CS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4202 {
4203 return ((val) << A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK;
4204 }
4205
4206 #define REG_A5XX_SP_VS_CONFIG_MAX_CONST 0x0000e58a
4207
4208 #define REG_A5XX_SP_FS_CONFIG_MAX_CONST 0x0000e58b
4209
4210 #define REG_A5XX_SP_VS_CTRL_REG0 0x0000e590
4211 #define A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00000008
4212 #define A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 3
A5XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)4213 static inline uint32_t A5XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4214 {
4215 return ((val) << A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
4216 }
4217 #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
4218 #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)4219 static inline uint32_t A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4220 {
4221 return ((val) << A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4222 }
4223 #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
4224 #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)4225 static inline uint32_t A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4226 {
4227 return ((val) << A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4228 }
4229 #define A5XX_SP_VS_CTRL_REG0_VARYING 0x00010000
4230 #define A5XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00100000
4231 #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
4232 #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 25
A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)4233 static inline uint32_t A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4234 {
4235 return ((val) << A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
4236 }
4237
4238 #define REG_A5XX_SP_PRIMITIVE_CNTL 0x0000e592
4239 #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK 0x0000001f
4240 #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT 0
A5XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val)4241 static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val)
4242 {
4243 return ((val) << A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK;
4244 }
4245
REG_A5XX_SP_VS_OUT(uint32_t i0)4246 static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0) { return 0x0000e593 + 0x1*i0; }
4247
REG_A5XX_SP_VS_OUT_REG(uint32_t i0)4248 static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000e593 + 0x1*i0; }
4249 #define A5XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
4250 #define A5XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val)4251 static inline uint32_t A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
4252 {
4253 return ((val) << A5XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_A_REGID__MASK;
4254 }
4255 #define A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00
4256 #define A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8
A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)4257 static inline uint32_t A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
4258 {
4259 return ((val) << A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
4260 }
4261 #define A5XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000
4262 #define A5XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val)4263 static inline uint32_t A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
4264 {
4265 return ((val) << A5XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_B_REGID__MASK;
4266 }
4267 #define A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000
4268 #define A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24
A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)4269 static inline uint32_t A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
4270 {
4271 return ((val) << A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
4272 }
4273
REG_A5XX_SP_VS_VPC_DST(uint32_t i0)4274 static inline uint32_t REG_A5XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }
4275
REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0)4276 static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }
4277 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
4278 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)4279 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
4280 {
4281 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
4282 }
4283 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
4284 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)4285 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
4286 {
4287 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
4288 }
4289 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
4290 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)4291 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
4292 {
4293 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
4294 }
4295 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
4296 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)4297 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
4298 {
4299 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
4300 }
4301
4302 #define REG_A5XX_UNKNOWN_E5AB 0x0000e5ab
4303
4304 #define REG_A5XX_SP_VS_OBJ_START_LO 0x0000e5ac
4305
4306 #define REG_A5XX_SP_VS_OBJ_START_HI 0x0000e5ad
4307
4308 #define REG_A5XX_SP_FS_CTRL_REG0 0x0000e5c0
4309 #define A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00000008
4310 #define A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 3
A5XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)4311 static inline uint32_t A5XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4312 {
4313 return ((val) << A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
4314 }
4315 #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
4316 #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)4317 static inline uint32_t A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4318 {
4319 return ((val) << A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4320 }
4321 #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
4322 #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)4323 static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4324 {
4325 return ((val) << A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4326 }
4327 #define A5XX_SP_FS_CTRL_REG0_VARYING 0x00010000
4328 #define A5XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00100000
4329 #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
4330 #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 25
A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)4331 static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4332 {
4333 return ((val) << A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
4334 }
4335
4336 #define REG_A5XX_UNKNOWN_E5C2 0x0000e5c2
4337
4338 #define REG_A5XX_SP_FS_OBJ_START_LO 0x0000e5c3
4339
4340 #define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4
4341
4342 #define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9
4343 #define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
4344 #define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
A5XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val)4345 static inline uint32_t A5XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
4346 {
4347 return ((val) << A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK;
4348 }
4349 #define A5XX_SP_BLEND_CNTL_UNK8 0x00000100
4350 #define A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
4351
4352 #define REG_A5XX_SP_FS_OUTPUT_CNTL 0x0000e5ca
4353 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
4354 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT 0
A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val)4355 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val)
4356 {
4357 return ((val) << A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK;
4358 }
4359 #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK 0x00001fe0
4360 #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT 5
A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val)4361 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val)
4362 {
4363 return ((val) << A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK;
4364 }
4365 #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK 0x001fe000
4366 #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT 13
A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val)4367 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val)
4368 {
4369 return ((val) << A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK;
4370 }
4371
REG_A5XX_SP_FS_OUTPUT(uint32_t i0)4372 static inline uint32_t REG_A5XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }
4373
REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0)4374 static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }
4375 #define A5XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
4376 #define A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)4377 static inline uint32_t A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
4378 {
4379 return ((val) << A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_REG_REGID__MASK;
4380 }
4381 #define A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
4382
REG_A5XX_SP_FS_MRT(uint32_t i0)4383 static inline uint32_t REG_A5XX_SP_FS_MRT(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }
4384
REG_A5XX_SP_FS_MRT_REG(uint32_t i0)4385 static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }
4386 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff
4387 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0
A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val)4388 static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val)
4389 {
4390 return ((val) << A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
4391 }
4392 #define A5XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100
4393 #define A5XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200
4394 #define A5XX_SP_FS_MRT_REG_COLOR_SRGB 0x00000400
4395
4396 #define REG_A5XX_UNKNOWN_E5DB 0x0000e5db
4397
4398 #define REG_A5XX_SP_CS_CTRL_REG0 0x0000e5f0
4399 #define A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00000008
4400 #define A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 3
A5XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)4401 static inline uint32_t A5XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4402 {
4403 return ((val) << A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
4404 }
4405 #define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
4406 #define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)4407 static inline uint32_t A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4408 {
4409 return ((val) << A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4410 }
4411 #define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
4412 #define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)4413 static inline uint32_t A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4414 {
4415 return ((val) << A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4416 }
4417 #define A5XX_SP_CS_CTRL_REG0_VARYING 0x00010000
4418 #define A5XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x00100000
4419 #define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
4420 #define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 25
A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)4421 static inline uint32_t A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4422 {
4423 return ((val) << A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
4424 }
4425
4426 #define REG_A5XX_UNKNOWN_E5F2 0x0000e5f2
4427
4428 #define REG_A5XX_SP_CS_OBJ_START_LO 0x0000e5f3
4429
4430 #define REG_A5XX_SP_CS_OBJ_START_HI 0x0000e5f4
4431
4432 #define REG_A5XX_SP_HS_CTRL_REG0 0x0000e600
4433 #define A5XX_SP_HS_CTRL_REG0_THREADSIZE__MASK 0x00000008
4434 #define A5XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT 3
A5XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)4435 static inline uint32_t A5XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4436 {
4437 return ((val) << A5XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_HS_CTRL_REG0_THREADSIZE__MASK;
4438 }
4439 #define A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
4440 #define A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)4441 static inline uint32_t A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4442 {
4443 return ((val) << A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4444 }
4445 #define A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
4446 #define A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)4447 static inline uint32_t A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4448 {
4449 return ((val) << A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4450 }
4451 #define A5XX_SP_HS_CTRL_REG0_VARYING 0x00010000
4452 #define A5XX_SP_HS_CTRL_REG0_PIXLODENABLE 0x00100000
4453 #define A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
4454 #define A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 25
A5XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)4455 static inline uint32_t A5XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4456 {
4457 return ((val) << A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;
4458 }
4459
4460 #define REG_A5XX_UNKNOWN_E602 0x0000e602
4461
4462 #define REG_A5XX_SP_HS_OBJ_START_LO 0x0000e603
4463
4464 #define REG_A5XX_SP_HS_OBJ_START_HI 0x0000e604
4465
4466 #define REG_A5XX_SP_DS_CTRL_REG0 0x0000e610
4467 #define A5XX_SP_DS_CTRL_REG0_THREADSIZE__MASK 0x00000008
4468 #define A5XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT 3
A5XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)4469 static inline uint32_t A5XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4470 {
4471 return ((val) << A5XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_DS_CTRL_REG0_THREADSIZE__MASK;
4472 }
4473 #define A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
4474 #define A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)4475 static inline uint32_t A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4476 {
4477 return ((val) << A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4478 }
4479 #define A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
4480 #define A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)4481 static inline uint32_t A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4482 {
4483 return ((val) << A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4484 }
4485 #define A5XX_SP_DS_CTRL_REG0_VARYING 0x00010000
4486 #define A5XX_SP_DS_CTRL_REG0_PIXLODENABLE 0x00100000
4487 #define A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
4488 #define A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 25
A5XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)4489 static inline uint32_t A5XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4490 {
4491 return ((val) << A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;
4492 }
4493
4494 #define REG_A5XX_UNKNOWN_E62B 0x0000e62b
4495
4496 #define REG_A5XX_SP_DS_OBJ_START_LO 0x0000e62c
4497
4498 #define REG_A5XX_SP_DS_OBJ_START_HI 0x0000e62d
4499
4500 #define REG_A5XX_SP_GS_CTRL_REG0 0x0000e640
4501 #define A5XX_SP_GS_CTRL_REG0_THREADSIZE__MASK 0x00000008
4502 #define A5XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT 3
A5XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)4503 static inline uint32_t A5XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4504 {
4505 return ((val) << A5XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_GS_CTRL_REG0_THREADSIZE__MASK;
4506 }
4507 #define A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
4508 #define A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)4509 static inline uint32_t A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4510 {
4511 return ((val) << A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4512 }
4513 #define A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
4514 #define A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)4515 static inline uint32_t A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4516 {
4517 return ((val) << A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4518 }
4519 #define A5XX_SP_GS_CTRL_REG0_VARYING 0x00010000
4520 #define A5XX_SP_GS_CTRL_REG0_PIXLODENABLE 0x00100000
4521 #define A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
4522 #define A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 25
A5XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)4523 static inline uint32_t A5XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4524 {
4525 return ((val) << A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;
4526 }
4527
4528 #define REG_A5XX_UNKNOWN_E65B 0x0000e65b
4529
4530 #define REG_A5XX_SP_GS_OBJ_START_LO 0x0000e65c
4531
4532 #define REG_A5XX_SP_GS_OBJ_START_HI 0x0000e65d
4533
4534 #define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL 0x0000e704
4535 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
4536 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)4537 static inline uint32_t A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
4538 {
4539 return ((val) << A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
4540 }
4541
4542 #define REG_A5XX_TPL1_TP_DEST_MSAA_CNTL 0x0000e705
4543 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
4544 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)4545 static inline uint32_t A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
4546 {
4547 return ((val) << A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK;
4548 }
4549 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
4550
4551 #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000e706
4552
4553 #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000e707
4554
4555 #define REG_A5XX_TPL1_VS_TEX_COUNT 0x0000e700
4556
4557 #define REG_A5XX_TPL1_HS_TEX_COUNT 0x0000e701
4558
4559 #define REG_A5XX_TPL1_DS_TEX_COUNT 0x0000e702
4560
4561 #define REG_A5XX_TPL1_GS_TEX_COUNT 0x0000e703
4562
4563 #define REG_A5XX_TPL1_VS_TEX_SAMP_LO 0x0000e722
4564
4565 #define REG_A5XX_TPL1_VS_TEX_SAMP_HI 0x0000e723
4566
4567 #define REG_A5XX_TPL1_HS_TEX_SAMP_LO 0x0000e724
4568
4569 #define REG_A5XX_TPL1_HS_TEX_SAMP_HI 0x0000e725
4570
4571 #define REG_A5XX_TPL1_DS_TEX_SAMP_LO 0x0000e726
4572
4573 #define REG_A5XX_TPL1_DS_TEX_SAMP_HI 0x0000e727
4574
4575 #define REG_A5XX_TPL1_GS_TEX_SAMP_LO 0x0000e728
4576
4577 #define REG_A5XX_TPL1_GS_TEX_SAMP_HI 0x0000e729
4578
4579 #define REG_A5XX_TPL1_VS_TEX_CONST_LO 0x0000e72a
4580
4581 #define REG_A5XX_TPL1_VS_TEX_CONST_HI 0x0000e72b
4582
4583 #define REG_A5XX_TPL1_HS_TEX_CONST_LO 0x0000e72c
4584
4585 #define REG_A5XX_TPL1_HS_TEX_CONST_HI 0x0000e72d
4586
4587 #define REG_A5XX_TPL1_DS_TEX_CONST_LO 0x0000e72e
4588
4589 #define REG_A5XX_TPL1_DS_TEX_CONST_HI 0x0000e72f
4590
4591 #define REG_A5XX_TPL1_GS_TEX_CONST_LO 0x0000e730
4592
4593 #define REG_A5XX_TPL1_GS_TEX_CONST_HI 0x0000e731
4594
4595 #define REG_A5XX_TPL1_FS_TEX_COUNT 0x0000e750
4596
4597 #define REG_A5XX_TPL1_CS_TEX_COUNT 0x0000e751
4598
4599 #define REG_A5XX_TPL1_FS_TEX_SAMP_LO 0x0000e75a
4600
4601 #define REG_A5XX_TPL1_FS_TEX_SAMP_HI 0x0000e75b
4602
4603 #define REG_A5XX_TPL1_CS_TEX_SAMP_LO 0x0000e75c
4604
4605 #define REG_A5XX_TPL1_CS_TEX_SAMP_HI 0x0000e75d
4606
4607 #define REG_A5XX_TPL1_FS_TEX_CONST_LO 0x0000e75e
4608
4609 #define REG_A5XX_TPL1_FS_TEX_CONST_HI 0x0000e75f
4610
4611 #define REG_A5XX_TPL1_CS_TEX_CONST_LO 0x0000e760
4612
4613 #define REG_A5XX_TPL1_CS_TEX_CONST_HI 0x0000e761
4614
4615 #define REG_A5XX_TPL1_TP_FS_ROTATION_CNTL 0x0000e764
4616
4617 #define REG_A5XX_HLSQ_CONTROL_0_REG 0x0000e784
4618 #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000001
4619 #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 0
A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)4620 static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
4621 {
4622 return ((val) << A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
4623 }
4624 #define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK 0x00000004
4625 #define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT 2
A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(enum a3xx_threadsize val)4626 static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(enum a3xx_threadsize val)
4627 {
4628 return ((val) << A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK;
4629 }
4630
4631 #define REG_A5XX_HLSQ_CONTROL_1_REG 0x0000e785
4632 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x0000003f
4633 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0
A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val)4634 static inline uint32_t A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val)
4635 {
4636 return ((val) << A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK;
4637 }
4638
4639 #define REG_A5XX_HLSQ_CONTROL_2_REG 0x0000e786
4640 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
4641 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0
A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)4642 static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
4643 {
4644 return ((val) << A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
4645 }
4646 #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00
4647 #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8
A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)4648 static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
4649 {
4650 return ((val) << A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK;
4651 }
4652 #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000
4653 #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16
A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)4654 static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
4655 {
4656 return ((val) << A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
4657 }
4658 #define A5XX_HLSQ_CONTROL_2_REG_SIZE__MASK 0xff000000
4659 #define A5XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT 24
A5XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val)4660 static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val)
4661 {
4662 return ((val) << A5XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SIZE__MASK;
4663 }
4664
4665 #define REG_A5XX_HLSQ_CONTROL_3_REG 0x0000e787
4666 #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff
4667 #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0
A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)4668 static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
4669 {
4670 return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
4671 }
4672 #define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00
4673 #define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8
A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)4674 static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
4675 {
4676 return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
4677 }
4678 #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000
4679 #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16
A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)4680 static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
4681 {
4682 return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
4683 }
4684 #define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000
4685 #define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24
A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)4686 static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
4687 {
4688 return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
4689 }
4690
4691 #define REG_A5XX_HLSQ_CONTROL_4_REG 0x0000e788
4692 #define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff
4693 #define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0
A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)4694 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
4695 {
4696 return ((val) << A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
4697 }
4698 #define A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00
4699 #define A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8
A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)4700 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
4701 {
4702 return ((val) << A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
4703 }
4704 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
4705 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)4706 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
4707 {
4708 return ((val) << A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK;
4709 }
4710 #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000
4711 #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24
A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)4712 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
4713 {
4714 return ((val) << A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
4715 }
4716
4717 #define REG_A5XX_HLSQ_UPDATE_CNTL 0x0000e78a
4718
4719 #define REG_A5XX_HLSQ_VS_CONFIG 0x0000e78b
4720 #define A5XX_HLSQ_VS_CONFIG_ENABLED 0x00000001
4721 #define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4722 #define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)4723 static inline uint32_t A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4724 {
4725 return ((val) << A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK;
4726 }
4727 #define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4728 #define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8
A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(uint32_t val)4729 static inline uint32_t A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4730 {
4731 return ((val) << A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK;
4732 }
4733
4734 #define REG_A5XX_HLSQ_FS_CONFIG 0x0000e78c
4735 #define A5XX_HLSQ_FS_CONFIG_ENABLED 0x00000001
4736 #define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4737 #define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)4738 static inline uint32_t A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4739 {
4740 return ((val) << A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK;
4741 }
4742 #define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4743 #define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8
A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(uint32_t val)4744 static inline uint32_t A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4745 {
4746 return ((val) << A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK;
4747 }
4748
4749 #define REG_A5XX_HLSQ_HS_CONFIG 0x0000e78d
4750 #define A5XX_HLSQ_HS_CONFIG_ENABLED 0x00000001
4751 #define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4752 #define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)4753 static inline uint32_t A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4754 {
4755 return ((val) << A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK;
4756 }
4757 #define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4758 #define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8
A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(uint32_t val)4759 static inline uint32_t A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4760 {
4761 return ((val) << A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK;
4762 }
4763
4764 #define REG_A5XX_HLSQ_DS_CONFIG 0x0000e78e
4765 #define A5XX_HLSQ_DS_CONFIG_ENABLED 0x00000001
4766 #define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4767 #define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)4768 static inline uint32_t A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4769 {
4770 return ((val) << A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK;
4771 }
4772 #define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4773 #define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8
A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(uint32_t val)4774 static inline uint32_t A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4775 {
4776 return ((val) << A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK;
4777 }
4778
4779 #define REG_A5XX_HLSQ_GS_CONFIG 0x0000e78f
4780 #define A5XX_HLSQ_GS_CONFIG_ENABLED 0x00000001
4781 #define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4782 #define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)4783 static inline uint32_t A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4784 {
4785 return ((val) << A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK;
4786 }
4787 #define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4788 #define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8
A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(uint32_t val)4789 static inline uint32_t A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4790 {
4791 return ((val) << A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK;
4792 }
4793
4794 #define REG_A5XX_HLSQ_CS_CONFIG 0x0000e790
4795 #define A5XX_HLSQ_CS_CONFIG_ENABLED 0x00000001
4796 #define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4797 #define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)4798 static inline uint32_t A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4799 {
4800 return ((val) << A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK;
4801 }
4802 #define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4803 #define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8
A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET(uint32_t val)4804 static inline uint32_t A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4805 {
4806 return ((val) << A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK;
4807 }
4808
4809 #define REG_A5XX_HLSQ_VS_CNTL 0x0000e791
4810 #define A5XX_HLSQ_VS_CNTL_SSBO_ENABLE 0x00000001
4811 #define A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK 0xfffffffe
4812 #define A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT 1
A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val)4813 static inline uint32_t A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val)
4814 {
4815 return ((val) << A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK;
4816 }
4817
4818 #define REG_A5XX_HLSQ_FS_CNTL 0x0000e792
4819 #define A5XX_HLSQ_FS_CNTL_SSBO_ENABLE 0x00000001
4820 #define A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK 0xfffffffe
4821 #define A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT 1
A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val)4822 static inline uint32_t A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val)
4823 {
4824 return ((val) << A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK;
4825 }
4826
4827 #define REG_A5XX_HLSQ_HS_CNTL 0x0000e793
4828 #define A5XX_HLSQ_HS_CNTL_SSBO_ENABLE 0x00000001
4829 #define A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK 0xfffffffe
4830 #define A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT 1
A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val)4831 static inline uint32_t A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val)
4832 {
4833 return ((val) << A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK;
4834 }
4835
4836 #define REG_A5XX_HLSQ_DS_CNTL 0x0000e794
4837 #define A5XX_HLSQ_DS_CNTL_SSBO_ENABLE 0x00000001
4838 #define A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK 0xfffffffe
4839 #define A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT 1
A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val)4840 static inline uint32_t A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val)
4841 {
4842 return ((val) << A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK;
4843 }
4844
4845 #define REG_A5XX_HLSQ_GS_CNTL 0x0000e795
4846 #define A5XX_HLSQ_GS_CNTL_SSBO_ENABLE 0x00000001
4847 #define A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK 0xfffffffe
4848 #define A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT 1
A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val)4849 static inline uint32_t A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val)
4850 {
4851 return ((val) << A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK;
4852 }
4853
4854 #define REG_A5XX_HLSQ_CS_CNTL 0x0000e796
4855 #define A5XX_HLSQ_CS_CNTL_SSBO_ENABLE 0x00000001
4856 #define A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK 0xfffffffe
4857 #define A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT 1
A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val)4858 static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val)
4859 {
4860 return ((val) << A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK;
4861 }
4862
4863 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_X 0x0000e7b9
4864
4865 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000e7ba
4866
4867 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000e7bb
4868
4869 #define REG_A5XX_HLSQ_CS_NDRANGE_0 0x0000e7b0
4870 #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003
4871 #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0
A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)4872 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
4873 {
4874 return ((val) << A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK;
4875 }
4876 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
4877 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2
A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)4878 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
4879 {
4880 return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK;
4881 }
4882 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
4883 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12
A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)4884 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
4885 {
4886 return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK;
4887 }
4888 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
4889 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22
A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)4890 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
4891 {
4892 return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK;
4893 }
4894
4895 #define REG_A5XX_HLSQ_CS_NDRANGE_1 0x0000e7b1
4896 #define A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff
4897 #define A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0
A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)4898 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)
4899 {
4900 return ((val) << A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK;
4901 }
4902
4903 #define REG_A5XX_HLSQ_CS_NDRANGE_2 0x0000e7b2
4904 #define A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff
4905 #define A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0
A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)4906 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)
4907 {
4908 return ((val) << A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK;
4909 }
4910
4911 #define REG_A5XX_HLSQ_CS_NDRANGE_3 0x0000e7b3
4912 #define A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff
4913 #define A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0
A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)4914 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)
4915 {
4916 return ((val) << A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK;
4917 }
4918
4919 #define REG_A5XX_HLSQ_CS_NDRANGE_4 0x0000e7b4
4920 #define A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff
4921 #define A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0
A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)4922 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)
4923 {
4924 return ((val) << A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK;
4925 }
4926
4927 #define REG_A5XX_HLSQ_CS_NDRANGE_5 0x0000e7b5
4928 #define A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff
4929 #define A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0
A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)4930 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)
4931 {
4932 return ((val) << A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK;
4933 }
4934
4935 #define REG_A5XX_HLSQ_CS_NDRANGE_6 0x0000e7b6
4936 #define A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff
4937 #define A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0
A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)4938 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)
4939 {
4940 return ((val) << A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK;
4941 }
4942
4943 #define REG_A5XX_HLSQ_CS_CNTL_0 0x0000e7b7
4944 #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff
4945 #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0
A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)4946 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
4947 {
4948 return ((val) << A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
4949 }
4950 #define A5XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00
4951 #define A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8
A5XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val)4952 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val)
4953 {
4954 return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK0__MASK;
4955 }
4956 #define A5XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000
4957 #define A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16
A5XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val)4958 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val)
4959 {
4960 return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK1__MASK;
4961 }
4962 #define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
4963 #define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24
A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)4964 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
4965 {
4966 return ((val) << A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
4967 }
4968
4969 #define REG_A5XX_HLSQ_CS_CNTL_1 0x0000e7b8
4970
4971 #define REG_A5XX_UNKNOWN_E7C0 0x0000e7c0
4972
4973 #define REG_A5XX_HLSQ_VS_CONSTLEN 0x0000e7c3
4974
4975 #define REG_A5XX_HLSQ_VS_INSTRLEN 0x0000e7c4
4976
4977 #define REG_A5XX_UNKNOWN_E7C5 0x0000e7c5
4978
4979 #define REG_A5XX_HLSQ_HS_CONSTLEN 0x0000e7c8
4980
4981 #define REG_A5XX_HLSQ_HS_INSTRLEN 0x0000e7c9
4982
4983 #define REG_A5XX_UNKNOWN_E7CA 0x0000e7ca
4984
4985 #define REG_A5XX_HLSQ_DS_CONSTLEN 0x0000e7cd
4986
4987 #define REG_A5XX_HLSQ_DS_INSTRLEN 0x0000e7ce
4988
4989 #define REG_A5XX_UNKNOWN_E7CF 0x0000e7cf
4990
4991 #define REG_A5XX_HLSQ_GS_CONSTLEN 0x0000e7d2
4992
4993 #define REG_A5XX_HLSQ_GS_INSTRLEN 0x0000e7d3
4994
4995 #define REG_A5XX_UNKNOWN_E7D4 0x0000e7d4
4996
4997 #define REG_A5XX_HLSQ_FS_CONSTLEN 0x0000e7d7
4998
4999 #define REG_A5XX_HLSQ_FS_INSTRLEN 0x0000e7d8
5000
5001 #define REG_A5XX_UNKNOWN_E7D9 0x0000e7d9
5002
5003 #define REG_A5XX_HLSQ_CS_CONSTLEN 0x0000e7dc
5004
5005 #define REG_A5XX_HLSQ_CS_INSTRLEN 0x0000e7dd
5006
5007 #define REG_A5XX_RB_2D_BLIT_CNTL 0x00002100
5008
5009 #define REG_A5XX_RB_2D_SRC_SOLID_DW0 0x00002101
5010
5011 #define REG_A5XX_RB_2D_SRC_SOLID_DW1 0x00002102
5012
5013 #define REG_A5XX_RB_2D_SRC_SOLID_DW2 0x00002103
5014
5015 #define REG_A5XX_RB_2D_SRC_SOLID_DW3 0x00002104
5016
5017 #define REG_A5XX_RB_2D_SRC_INFO 0x00002107
5018 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
5019 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)5020 static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
5021 {
5022 return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK;
5023 }
5024 #define A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK 0x00000300
5025 #define A5XX_RB_2D_SRC_INFO_TILE_MODE__SHIFT 8
A5XX_RB_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val)5026 static inline uint32_t A5XX_RB_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val)
5027 {
5028 return ((val) << A5XX_RB_2D_SRC_INFO_TILE_MODE__SHIFT) & A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK;
5029 }
5030 #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
5031 #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)5032 static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
5033 {
5034 return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK;
5035 }
5036 #define A5XX_RB_2D_SRC_INFO_FLAGS 0x00001000
5037
5038 #define REG_A5XX_RB_2D_SRC_LO 0x00002108
5039
5040 #define REG_A5XX_RB_2D_SRC_HI 0x00002109
5041
5042 #define REG_A5XX_RB_2D_SRC_SIZE 0x0000210a
5043 #define A5XX_RB_2D_SRC_SIZE_PITCH__MASK 0x0000ffff
5044 #define A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT 0
A5XX_RB_2D_SRC_SIZE_PITCH(uint32_t val)5045 static inline uint32_t A5XX_RB_2D_SRC_SIZE_PITCH(uint32_t val)
5046 {
5047 return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_PITCH__MASK;
5048 }
5049 #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK 0xffff0000
5050 #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT 16
A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(uint32_t val)5051 static inline uint32_t A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(uint32_t val)
5052 {
5053 return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK;
5054 }
5055
5056 #define REG_A5XX_RB_2D_DST_INFO 0x00002110
5057 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
5058 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)5059 static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
5060 {
5061 return ((val) << A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
5062 }
5063 #define A5XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300
5064 #define A5XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8
A5XX_RB_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val)5065 static inline uint32_t A5XX_RB_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val)
5066 {
5067 return ((val) << A5XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A5XX_RB_2D_DST_INFO_TILE_MODE__MASK;
5068 }
5069 #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
5070 #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10
A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)5071 static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
5072 {
5073 return ((val) << A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
5074 }
5075 #define A5XX_RB_2D_DST_INFO_FLAGS 0x00001000
5076
5077 #define REG_A5XX_RB_2D_DST_LO 0x00002111
5078
5079 #define REG_A5XX_RB_2D_DST_HI 0x00002112
5080
5081 #define REG_A5XX_RB_2D_DST_SIZE 0x00002113
5082 #define A5XX_RB_2D_DST_SIZE_PITCH__MASK 0x0000ffff
5083 #define A5XX_RB_2D_DST_SIZE_PITCH__SHIFT 0
A5XX_RB_2D_DST_SIZE_PITCH(uint32_t val)5084 static inline uint32_t A5XX_RB_2D_DST_SIZE_PITCH(uint32_t val)
5085 {
5086 return ((val >> 6) << A5XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_PITCH__MASK;
5087 }
5088 #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK 0xffff0000
5089 #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT 16
A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val)5090 static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val)
5091 {
5092 return ((val >> 6) << A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK;
5093 }
5094
5095 #define REG_A5XX_RB_2D_SRC_FLAGS_LO 0x00002140
5096
5097 #define REG_A5XX_RB_2D_SRC_FLAGS_HI 0x00002141
5098
5099 #define REG_A5XX_RB_2D_SRC_FLAGS_PITCH 0x00002142
5100 #define A5XX_RB_2D_SRC_FLAGS_PITCH__MASK 0xffffffff
5101 #define A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT 0
A5XX_RB_2D_SRC_FLAGS_PITCH(uint32_t val)5102 static inline uint32_t A5XX_RB_2D_SRC_FLAGS_PITCH(uint32_t val)
5103 {
5104 return ((val >> 6) << A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_SRC_FLAGS_PITCH__MASK;
5105 }
5106
5107 #define REG_A5XX_RB_2D_DST_FLAGS_LO 0x00002143
5108
5109 #define REG_A5XX_RB_2D_DST_FLAGS_HI 0x00002144
5110
5111 #define REG_A5XX_RB_2D_DST_FLAGS_PITCH 0x00002145
5112 #define A5XX_RB_2D_DST_FLAGS_PITCH__MASK 0xffffffff
5113 #define A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0
A5XX_RB_2D_DST_FLAGS_PITCH(uint32_t val)5114 static inline uint32_t A5XX_RB_2D_DST_FLAGS_PITCH(uint32_t val)
5115 {
5116 return ((val >> 6) << A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_DST_FLAGS_PITCH__MASK;
5117 }
5118
5119 #define REG_A5XX_GRAS_2D_BLIT_CNTL 0x00002180
5120
5121 #define REG_A5XX_GRAS_2D_SRC_INFO 0x00002181
5122 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
5123 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)5124 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
5125 {
5126 return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK;
5127 }
5128 #define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300
5129 #define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__SHIFT 8
A5XX_GRAS_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val)5130 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val)
5131 {
5132 return ((val) << A5XX_GRAS_2D_SRC_INFO_TILE_MODE__SHIFT) & A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK;
5133 }
5134 #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
5135 #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)5136 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
5137 {
5138 return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK;
5139 }
5140 #define A5XX_GRAS_2D_SRC_INFO_FLAGS 0x00001000
5141
5142 #define REG_A5XX_GRAS_2D_DST_INFO 0x00002182
5143 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
5144 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)5145 static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
5146 {
5147 return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK;
5148 }
5149 #define A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK 0x00000300
5150 #define A5XX_GRAS_2D_DST_INFO_TILE_MODE__SHIFT 8
A5XX_GRAS_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val)5151 static inline uint32_t A5XX_GRAS_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val)
5152 {
5153 return ((val) << A5XX_GRAS_2D_DST_INFO_TILE_MODE__SHIFT) & A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK;
5154 }
5155 #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
5156 #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT 10
A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)5157 static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
5158 {
5159 return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK;
5160 }
5161 #define A5XX_GRAS_2D_DST_INFO_FLAGS 0x00001000
5162
5163 #define REG_A5XX_UNKNOWN_2100 0x00002100
5164
5165 #define REG_A5XX_UNKNOWN_2180 0x00002180
5166
5167 #define REG_A5XX_UNKNOWN_2184 0x00002184
5168
5169 #define REG_A5XX_TEX_SAMP_0 0x00000000
5170 #define A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
5171 #define A5XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
5172 #define A5XX_TEX_SAMP_0_XY_MAG__SHIFT 1
A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val)5173 static inline uint32_t A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val)
5174 {
5175 return ((val) << A5XX_TEX_SAMP_0_XY_MAG__SHIFT) & A5XX_TEX_SAMP_0_XY_MAG__MASK;
5176 }
5177 #define A5XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
5178 #define A5XX_TEX_SAMP_0_XY_MIN__SHIFT 3
A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val)5179 static inline uint32_t A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val)
5180 {
5181 return ((val) << A5XX_TEX_SAMP_0_XY_MIN__SHIFT) & A5XX_TEX_SAMP_0_XY_MIN__MASK;
5182 }
5183 #define A5XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
5184 #define A5XX_TEX_SAMP_0_WRAP_S__SHIFT 5
A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val)5185 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val)
5186 {
5187 return ((val) << A5XX_TEX_SAMP_0_WRAP_S__SHIFT) & A5XX_TEX_SAMP_0_WRAP_S__MASK;
5188 }
5189 #define A5XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
5190 #define A5XX_TEX_SAMP_0_WRAP_T__SHIFT 8
A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val)5191 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val)
5192 {
5193 return ((val) << A5XX_TEX_SAMP_0_WRAP_T__SHIFT) & A5XX_TEX_SAMP_0_WRAP_T__MASK;
5194 }
5195 #define A5XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
5196 #define A5XX_TEX_SAMP_0_WRAP_R__SHIFT 11
A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val)5197 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val)
5198 {
5199 return ((val) << A5XX_TEX_SAMP_0_WRAP_R__SHIFT) & A5XX_TEX_SAMP_0_WRAP_R__MASK;
5200 }
5201 #define A5XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
5202 #define A5XX_TEX_SAMP_0_ANISO__SHIFT 14
A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val)5203 static inline uint32_t A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val)
5204 {
5205 return ((val) << A5XX_TEX_SAMP_0_ANISO__SHIFT) & A5XX_TEX_SAMP_0_ANISO__MASK;
5206 }
5207 #define A5XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
5208 #define A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
A5XX_TEX_SAMP_0_LOD_BIAS(float val)5209 static inline uint32_t A5XX_TEX_SAMP_0_LOD_BIAS(float val)
5210 {
5211 return ((((int32_t)(val * 256.0))) << A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A5XX_TEX_SAMP_0_LOD_BIAS__MASK;
5212 }
5213
5214 #define REG_A5XX_TEX_SAMP_1 0x00000001
5215 #define A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
5216 #define A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)5217 static inline uint32_t A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
5218 {
5219 return ((val) << A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
5220 }
5221 #define A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
5222 #define A5XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
5223 #define A5XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
5224 #define A5XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
5225 #define A5XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
A5XX_TEX_SAMP_1_MAX_LOD(float val)5226 static inline uint32_t A5XX_TEX_SAMP_1_MAX_LOD(float val)
5227 {
5228 return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A5XX_TEX_SAMP_1_MAX_LOD__MASK;
5229 }
5230 #define A5XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
5231 #define A5XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
A5XX_TEX_SAMP_1_MIN_LOD(float val)5232 static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val)
5233 {
5234 return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A5XX_TEX_SAMP_1_MIN_LOD__MASK;
5235 }
5236
5237 #define REG_A5XX_TEX_SAMP_2 0x00000002
5238 #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xffffff80
5239 #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 7
A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)5240 static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
5241 {
5242 return ((val) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
5243 }
5244
5245 #define REG_A5XX_TEX_SAMP_3 0x00000003
5246
5247 #define REG_A5XX_TEX_CONST_0 0x00000000
5248 #define A5XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003
5249 #define A5XX_TEX_CONST_0_TILE_MODE__SHIFT 0
A5XX_TEX_CONST_0_TILE_MODE(enum a5xx_tile_mode val)5250 static inline uint32_t A5XX_TEX_CONST_0_TILE_MODE(enum a5xx_tile_mode val)
5251 {
5252 return ((val) << A5XX_TEX_CONST_0_TILE_MODE__SHIFT) & A5XX_TEX_CONST_0_TILE_MODE__MASK;
5253 }
5254 #define A5XX_TEX_CONST_0_SRGB 0x00000004
5255 #define A5XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
5256 #define A5XX_TEX_CONST_0_SWIZ_X__SHIFT 4
A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val)5257 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val)
5258 {
5259 return ((val) << A5XX_TEX_CONST_0_SWIZ_X__SHIFT) & A5XX_TEX_CONST_0_SWIZ_X__MASK;
5260 }
5261 #define A5XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
5262 #define A5XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val)5263 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val)
5264 {
5265 return ((val) << A5XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Y__MASK;
5266 }
5267 #define A5XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
5268 #define A5XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val)5269 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val)
5270 {
5271 return ((val) << A5XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Z__MASK;
5272 }
5273 #define A5XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
5274 #define A5XX_TEX_CONST_0_SWIZ_W__SHIFT 13
A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val)5275 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val)
5276 {
5277 return ((val) << A5XX_TEX_CONST_0_SWIZ_W__SHIFT) & A5XX_TEX_CONST_0_SWIZ_W__MASK;
5278 }
5279 #define A5XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
5280 #define A5XX_TEX_CONST_0_MIPLVLS__SHIFT 16
A5XX_TEX_CONST_0_MIPLVLS(uint32_t val)5281 static inline uint32_t A5XX_TEX_CONST_0_MIPLVLS(uint32_t val)
5282 {
5283 return ((val) << A5XX_TEX_CONST_0_MIPLVLS__SHIFT) & A5XX_TEX_CONST_0_MIPLVLS__MASK;
5284 }
5285 #define A5XX_TEX_CONST_0_SAMPLES__MASK 0x00300000
5286 #define A5XX_TEX_CONST_0_SAMPLES__SHIFT 20
A5XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)5287 static inline uint32_t A5XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)
5288 {
5289 return ((val) << A5XX_TEX_CONST_0_SAMPLES__SHIFT) & A5XX_TEX_CONST_0_SAMPLES__MASK;
5290 }
5291 #define A5XX_TEX_CONST_0_FMT__MASK 0x3fc00000
5292 #define A5XX_TEX_CONST_0_FMT__SHIFT 22
A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val)5293 static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val)
5294 {
5295 return ((val) << A5XX_TEX_CONST_0_FMT__SHIFT) & A5XX_TEX_CONST_0_FMT__MASK;
5296 }
5297 #define A5XX_TEX_CONST_0_SWAP__MASK 0xc0000000
5298 #define A5XX_TEX_CONST_0_SWAP__SHIFT 30
A5XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)5299 static inline uint32_t A5XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)
5300 {
5301 return ((val) << A5XX_TEX_CONST_0_SWAP__SHIFT) & A5XX_TEX_CONST_0_SWAP__MASK;
5302 }
5303
5304 #define REG_A5XX_TEX_CONST_1 0x00000001
5305 #define A5XX_TEX_CONST_1_WIDTH__MASK 0x00007fff
5306 #define A5XX_TEX_CONST_1_WIDTH__SHIFT 0
A5XX_TEX_CONST_1_WIDTH(uint32_t val)5307 static inline uint32_t A5XX_TEX_CONST_1_WIDTH(uint32_t val)
5308 {
5309 return ((val) << A5XX_TEX_CONST_1_WIDTH__SHIFT) & A5XX_TEX_CONST_1_WIDTH__MASK;
5310 }
5311 #define A5XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000
5312 #define A5XX_TEX_CONST_1_HEIGHT__SHIFT 15
A5XX_TEX_CONST_1_HEIGHT(uint32_t val)5313 static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val)
5314 {
5315 return ((val) << A5XX_TEX_CONST_1_HEIGHT__SHIFT) & A5XX_TEX_CONST_1_HEIGHT__MASK;
5316 }
5317
5318 #define REG_A5XX_TEX_CONST_2 0x00000002
5319 #define A5XX_TEX_CONST_2_UNK4 0x00000010
5320 #define A5XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f
5321 #define A5XX_TEX_CONST_2_PITCHALIGN__SHIFT 0
A5XX_TEX_CONST_2_PITCHALIGN(uint32_t val)5322 static inline uint32_t A5XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
5323 {
5324 return ((val) << A5XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A5XX_TEX_CONST_2_PITCHALIGN__MASK;
5325 }
5326 #define A5XX_TEX_CONST_2_PITCH__MASK 0x1fffff80
5327 #define A5XX_TEX_CONST_2_PITCH__SHIFT 7
A5XX_TEX_CONST_2_PITCH(uint32_t val)5328 static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val)
5329 {
5330 return ((val) << A5XX_TEX_CONST_2_PITCH__SHIFT) & A5XX_TEX_CONST_2_PITCH__MASK;
5331 }
5332 #define A5XX_TEX_CONST_2_TYPE__MASK 0x60000000
5333 #define A5XX_TEX_CONST_2_TYPE__SHIFT 29
A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val)5334 static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val)
5335 {
5336 return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK;
5337 }
5338 #define A5XX_TEX_CONST_2_UNK31 0x80000000
5339
5340 #define REG_A5XX_TEX_CONST_3 0x00000003
5341 #define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
5342 #define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0
A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)5343 static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
5344 {
5345 return ((val >> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK;
5346 }
5347 #define A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000
5348 #define A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23
A5XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)5349 static inline uint32_t A5XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)
5350 {
5351 return ((val >> 12) << A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK;
5352 }
5353 #define A5XX_TEX_CONST_3_TILE_ALL 0x08000000
5354 #define A5XX_TEX_CONST_3_FLAG 0x10000000
5355
5356 #define REG_A5XX_TEX_CONST_4 0x00000004
5357 #define A5XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0
5358 #define A5XX_TEX_CONST_4_BASE_LO__SHIFT 5
A5XX_TEX_CONST_4_BASE_LO(uint32_t val)5359 static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val)
5360 {
5361 return ((val >> 5) << A5XX_TEX_CONST_4_BASE_LO__SHIFT) & A5XX_TEX_CONST_4_BASE_LO__MASK;
5362 }
5363
5364 #define REG_A5XX_TEX_CONST_5 0x00000005
5365 #define A5XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff
5366 #define A5XX_TEX_CONST_5_BASE_HI__SHIFT 0
A5XX_TEX_CONST_5_BASE_HI(uint32_t val)5367 static inline uint32_t A5XX_TEX_CONST_5_BASE_HI(uint32_t val)
5368 {
5369 return ((val) << A5XX_TEX_CONST_5_BASE_HI__SHIFT) & A5XX_TEX_CONST_5_BASE_HI__MASK;
5370 }
5371 #define A5XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000
5372 #define A5XX_TEX_CONST_5_DEPTH__SHIFT 17
A5XX_TEX_CONST_5_DEPTH(uint32_t val)5373 static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val)
5374 {
5375 return ((val) << A5XX_TEX_CONST_5_DEPTH__SHIFT) & A5XX_TEX_CONST_5_DEPTH__MASK;
5376 }
5377
5378 #define REG_A5XX_TEX_CONST_6 0x00000006
5379
5380 #define REG_A5XX_TEX_CONST_7 0x00000007
5381
5382 #define REG_A5XX_TEX_CONST_8 0x00000008
5383
5384 #define REG_A5XX_TEX_CONST_9 0x00000009
5385
5386 #define REG_A5XX_TEX_CONST_10 0x0000000a
5387
5388 #define REG_A5XX_TEX_CONST_11 0x0000000b
5389
5390 #define REG_A5XX_SSBO_0_0 0x00000000
5391 #define A5XX_SSBO_0_0_BASE_LO__MASK 0xffffffe0
5392 #define A5XX_SSBO_0_0_BASE_LO__SHIFT 5
A5XX_SSBO_0_0_BASE_LO(uint32_t val)5393 static inline uint32_t A5XX_SSBO_0_0_BASE_LO(uint32_t val)
5394 {
5395 return ((val >> 5) << A5XX_SSBO_0_0_BASE_LO__SHIFT) & A5XX_SSBO_0_0_BASE_LO__MASK;
5396 }
5397
5398 #define REG_A5XX_SSBO_0_1 0x00000001
5399 #define A5XX_SSBO_0_1_PITCH__MASK 0x003fffff
5400 #define A5XX_SSBO_0_1_PITCH__SHIFT 0
A5XX_SSBO_0_1_PITCH(uint32_t val)5401 static inline uint32_t A5XX_SSBO_0_1_PITCH(uint32_t val)
5402 {
5403 return ((val) << A5XX_SSBO_0_1_PITCH__SHIFT) & A5XX_SSBO_0_1_PITCH__MASK;
5404 }
5405
5406 #define REG_A5XX_SSBO_0_2 0x00000002
5407 #define A5XX_SSBO_0_2_ARRAY_PITCH__MASK 0x03fff000
5408 #define A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT 12
A5XX_SSBO_0_2_ARRAY_PITCH(uint32_t val)5409 static inline uint32_t A5XX_SSBO_0_2_ARRAY_PITCH(uint32_t val)
5410 {
5411 return ((val >> 12) << A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A5XX_SSBO_0_2_ARRAY_PITCH__MASK;
5412 }
5413
5414 #define REG_A5XX_SSBO_0_3 0x00000003
5415 #define A5XX_SSBO_0_3_CPP__MASK 0x0000003f
5416 #define A5XX_SSBO_0_3_CPP__SHIFT 0
A5XX_SSBO_0_3_CPP(uint32_t val)5417 static inline uint32_t A5XX_SSBO_0_3_CPP(uint32_t val)
5418 {
5419 return ((val) << A5XX_SSBO_0_3_CPP__SHIFT) & A5XX_SSBO_0_3_CPP__MASK;
5420 }
5421
5422 #define REG_A5XX_SSBO_1_0 0x00000000
5423 #define A5XX_SSBO_1_0_FMT__MASK 0x0000ff00
5424 #define A5XX_SSBO_1_0_FMT__SHIFT 8
A5XX_SSBO_1_0_FMT(enum a5xx_tex_fmt val)5425 static inline uint32_t A5XX_SSBO_1_0_FMT(enum a5xx_tex_fmt val)
5426 {
5427 return ((val) << A5XX_SSBO_1_0_FMT__SHIFT) & A5XX_SSBO_1_0_FMT__MASK;
5428 }
5429 #define A5XX_SSBO_1_0_WIDTH__MASK 0xffff0000
5430 #define A5XX_SSBO_1_0_WIDTH__SHIFT 16
A5XX_SSBO_1_0_WIDTH(uint32_t val)5431 static inline uint32_t A5XX_SSBO_1_0_WIDTH(uint32_t val)
5432 {
5433 return ((val) << A5XX_SSBO_1_0_WIDTH__SHIFT) & A5XX_SSBO_1_0_WIDTH__MASK;
5434 }
5435
5436 #define REG_A5XX_SSBO_1_1 0x00000001
5437 #define A5XX_SSBO_1_1_HEIGHT__MASK 0x0000ffff
5438 #define A5XX_SSBO_1_1_HEIGHT__SHIFT 0
A5XX_SSBO_1_1_HEIGHT(uint32_t val)5439 static inline uint32_t A5XX_SSBO_1_1_HEIGHT(uint32_t val)
5440 {
5441 return ((val) << A5XX_SSBO_1_1_HEIGHT__SHIFT) & A5XX_SSBO_1_1_HEIGHT__MASK;
5442 }
5443 #define A5XX_SSBO_1_1_DEPTH__MASK 0xffff0000
5444 #define A5XX_SSBO_1_1_DEPTH__SHIFT 16
A5XX_SSBO_1_1_DEPTH(uint32_t val)5445 static inline uint32_t A5XX_SSBO_1_1_DEPTH(uint32_t val)
5446 {
5447 return ((val) << A5XX_SSBO_1_1_DEPTH__SHIFT) & A5XX_SSBO_1_1_DEPTH__MASK;
5448 }
5449
5450 #define REG_A5XX_SSBO_2_0 0x00000000
5451 #define A5XX_SSBO_2_0_BASE_LO__MASK 0xffffffff
5452 #define A5XX_SSBO_2_0_BASE_LO__SHIFT 0
A5XX_SSBO_2_0_BASE_LO(uint32_t val)5453 static inline uint32_t A5XX_SSBO_2_0_BASE_LO(uint32_t val)
5454 {
5455 return ((val) << A5XX_SSBO_2_0_BASE_LO__SHIFT) & A5XX_SSBO_2_0_BASE_LO__MASK;
5456 }
5457
5458 #define REG_A5XX_SSBO_2_1 0x00000001
5459 #define A5XX_SSBO_2_1_BASE_HI__MASK 0xffffffff
5460 #define A5XX_SSBO_2_1_BASE_HI__SHIFT 0
A5XX_SSBO_2_1_BASE_HI(uint32_t val)5461 static inline uint32_t A5XX_SSBO_2_1_BASE_HI(uint32_t val)
5462 {
5463 return ((val) << A5XX_SSBO_2_1_BASE_HI__SHIFT) & A5XX_SSBO_2_1_BASE_HI__MASK;
5464 }
5465
5466 #define REG_A5XX_UBO_0 0x00000000
5467 #define A5XX_UBO_0_BASE_LO__MASK 0xffffffff
5468 #define A5XX_UBO_0_BASE_LO__SHIFT 0
A5XX_UBO_0_BASE_LO(uint32_t val)5469 static inline uint32_t A5XX_UBO_0_BASE_LO(uint32_t val)
5470 {
5471 return ((val) << A5XX_UBO_0_BASE_LO__SHIFT) & A5XX_UBO_0_BASE_LO__MASK;
5472 }
5473
5474 #define REG_A5XX_UBO_1 0x00000001
5475 #define A5XX_UBO_1_BASE_HI__MASK 0x0001ffff
5476 #define A5XX_UBO_1_BASE_HI__SHIFT 0
A5XX_UBO_1_BASE_HI(uint32_t val)5477 static inline uint32_t A5XX_UBO_1_BASE_HI(uint32_t val)
5478 {
5479 return ((val) << A5XX_UBO_1_BASE_HI__SHIFT) & A5XX_UBO_1_BASE_HI__MASK;
5480 }
5481
5482
5483 #endif /* A5XX_XML */
5484