1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Distributed Switch Architecture VSC9953 driver
3 * Copyright (C) 2020, Maxim Kochetkov <fido_max@inbox.ru>
4 */
5 #include <linux/types.h>
6 #include <soc/mscc/ocelot_vcap.h>
7 #include <soc/mscc/ocelot_sys.h>
8 #include <soc/mscc/ocelot.h>
9 #include <linux/of_platform.h>
10 #include <linux/pcs-lynx.h>
11 #include <linux/dsa/ocelot.h>
12 #include <linux/iopoll.h>
13 #include <linux/of_mdio.h>
14 #include "felix.h"
15
16 #define MSCC_MIIM_CMD_OPR_WRITE BIT(1)
17 #define MSCC_MIIM_CMD_OPR_READ BIT(2)
18 #define MSCC_MIIM_CMD_WRDATA_SHIFT 4
19 #define MSCC_MIIM_CMD_REGAD_SHIFT 20
20 #define MSCC_MIIM_CMD_PHYAD_SHIFT 25
21 #define MSCC_MIIM_CMD_VLD BIT(31)
22
23 static const u32 vsc9953_ana_regmap[] = {
24 REG(ANA_ADVLEARN, 0x00b500),
25 REG(ANA_VLANMASK, 0x00b504),
26 REG_RESERVED(ANA_PORT_B_DOMAIN),
27 REG(ANA_ANAGEFIL, 0x00b50c),
28 REG(ANA_ANEVENTS, 0x00b510),
29 REG(ANA_STORMLIMIT_BURST, 0x00b514),
30 REG(ANA_STORMLIMIT_CFG, 0x00b518),
31 REG(ANA_ISOLATED_PORTS, 0x00b528),
32 REG(ANA_COMMUNITY_PORTS, 0x00b52c),
33 REG(ANA_AUTOAGE, 0x00b530),
34 REG(ANA_MACTOPTIONS, 0x00b534),
35 REG(ANA_LEARNDISC, 0x00b538),
36 REG(ANA_AGENCTRL, 0x00b53c),
37 REG(ANA_MIRRORPORTS, 0x00b540),
38 REG(ANA_EMIRRORPORTS, 0x00b544),
39 REG(ANA_FLOODING, 0x00b548),
40 REG(ANA_FLOODING_IPMC, 0x00b54c),
41 REG(ANA_SFLOW_CFG, 0x00b550),
42 REG(ANA_PORT_MODE, 0x00b57c),
43 REG_RESERVED(ANA_CUT_THRU_CFG),
44 REG(ANA_PGID_PGID, 0x00b600),
45 REG(ANA_TABLES_ANMOVED, 0x00b4ac),
46 REG(ANA_TABLES_MACHDATA, 0x00b4b0),
47 REG(ANA_TABLES_MACLDATA, 0x00b4b4),
48 REG_RESERVED(ANA_TABLES_STREAMDATA),
49 REG(ANA_TABLES_MACACCESS, 0x00b4b8),
50 REG(ANA_TABLES_MACTINDX, 0x00b4bc),
51 REG(ANA_TABLES_VLANACCESS, 0x00b4c0),
52 REG(ANA_TABLES_VLANTIDX, 0x00b4c4),
53 REG_RESERVED(ANA_TABLES_ISDXACCESS),
54 REG_RESERVED(ANA_TABLES_ISDXTIDX),
55 REG(ANA_TABLES_ENTRYLIM, 0x00b480),
56 REG_RESERVED(ANA_TABLES_PTP_ID_HIGH),
57 REG_RESERVED(ANA_TABLES_PTP_ID_LOW),
58 REG_RESERVED(ANA_TABLES_STREAMACCESS),
59 REG_RESERVED(ANA_TABLES_STREAMTIDX),
60 REG_RESERVED(ANA_TABLES_SEQ_HISTORY),
61 REG_RESERVED(ANA_TABLES_SEQ_MASK),
62 REG_RESERVED(ANA_TABLES_SFID_MASK),
63 REG_RESERVED(ANA_TABLES_SFIDACCESS),
64 REG_RESERVED(ANA_TABLES_SFIDTIDX),
65 REG_RESERVED(ANA_MSTI_STATE),
66 REG_RESERVED(ANA_OAM_UPM_LM_CNT),
67 REG_RESERVED(ANA_SG_ACCESS_CTRL),
68 REG_RESERVED(ANA_SG_CONFIG_REG_1),
69 REG_RESERVED(ANA_SG_CONFIG_REG_2),
70 REG_RESERVED(ANA_SG_CONFIG_REG_3),
71 REG_RESERVED(ANA_SG_CONFIG_REG_4),
72 REG_RESERVED(ANA_SG_CONFIG_REG_5),
73 REG_RESERVED(ANA_SG_GCL_GS_CONFIG),
74 REG_RESERVED(ANA_SG_GCL_TI_CONFIG),
75 REG_RESERVED(ANA_SG_STATUS_REG_1),
76 REG_RESERVED(ANA_SG_STATUS_REG_2),
77 REG_RESERVED(ANA_SG_STATUS_REG_3),
78 REG(ANA_PORT_VLAN_CFG, 0x000000),
79 REG(ANA_PORT_DROP_CFG, 0x000004),
80 REG(ANA_PORT_QOS_CFG, 0x000008),
81 REG(ANA_PORT_VCAP_CFG, 0x00000c),
82 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x000010),
83 REG(ANA_PORT_VCAP_S2_CFG, 0x00001c),
84 REG(ANA_PORT_PCP_DEI_MAP, 0x000020),
85 REG(ANA_PORT_CPU_FWD_CFG, 0x000060),
86 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x000064),
87 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x000068),
88 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00006c),
89 REG(ANA_PORT_PORT_CFG, 0x000070),
90 REG(ANA_PORT_POL_CFG, 0x000074),
91 REG_RESERVED(ANA_PORT_PTP_CFG),
92 REG_RESERVED(ANA_PORT_PTP_DLY1_CFG),
93 REG_RESERVED(ANA_PORT_PTP_DLY2_CFG),
94 REG_RESERVED(ANA_PORT_SFID_CFG),
95 REG(ANA_PFC_PFC_CFG, 0x00c000),
96 REG_RESERVED(ANA_PFC_PFC_TIMER),
97 REG_RESERVED(ANA_IPT_OAM_MEP_CFG),
98 REG_RESERVED(ANA_IPT_IPT),
99 REG_RESERVED(ANA_PPT_PPT),
100 REG_RESERVED(ANA_FID_MAP_FID_MAP),
101 REG(ANA_AGGR_CFG, 0x00c600),
102 REG(ANA_CPUQ_CFG, 0x00c604),
103 REG_RESERVED(ANA_CPUQ_CFG2),
104 REG(ANA_CPUQ_8021_CFG, 0x00c60c),
105 REG(ANA_DSCP_CFG, 0x00c64c),
106 REG(ANA_DSCP_REWR_CFG, 0x00c74c),
107 REG(ANA_VCAP_RNG_TYPE_CFG, 0x00c78c),
108 REG(ANA_VCAP_RNG_VAL_CFG, 0x00c7ac),
109 REG_RESERVED(ANA_VRAP_CFG),
110 REG_RESERVED(ANA_VRAP_HDR_DATA),
111 REG_RESERVED(ANA_VRAP_HDR_MASK),
112 REG(ANA_DISCARD_CFG, 0x00c7d8),
113 REG(ANA_FID_CFG, 0x00c7dc),
114 REG(ANA_POL_PIR_CFG, 0x00a000),
115 REG(ANA_POL_CIR_CFG, 0x00a004),
116 REG(ANA_POL_MODE_CFG, 0x00a008),
117 REG(ANA_POL_PIR_STATE, 0x00a00c),
118 REG(ANA_POL_CIR_STATE, 0x00a010),
119 REG_RESERVED(ANA_POL_STATE),
120 REG(ANA_POL_FLOWC, 0x00c280),
121 REG(ANA_POL_HYST, 0x00c2ec),
122 REG_RESERVED(ANA_POL_MISC_CFG),
123 };
124
125 static const u32 vsc9953_qs_regmap[] = {
126 REG(QS_XTR_GRP_CFG, 0x000000),
127 REG(QS_XTR_RD, 0x000008),
128 REG(QS_XTR_FRM_PRUNING, 0x000010),
129 REG(QS_XTR_FLUSH, 0x000018),
130 REG(QS_XTR_DATA_PRESENT, 0x00001c),
131 REG(QS_XTR_CFG, 0x000020),
132 REG(QS_INJ_GRP_CFG, 0x000024),
133 REG(QS_INJ_WR, 0x00002c),
134 REG(QS_INJ_CTRL, 0x000034),
135 REG(QS_INJ_STATUS, 0x00003c),
136 REG(QS_INJ_ERR, 0x000040),
137 REG_RESERVED(QS_INH_DBG),
138 };
139
140 static const u32 vsc9953_vcap_regmap[] = {
141 /* VCAP_CORE_CFG */
142 REG(VCAP_CORE_UPDATE_CTRL, 0x000000),
143 REG(VCAP_CORE_MV_CFG, 0x000004),
144 /* VCAP_CORE_CACHE */
145 REG(VCAP_CACHE_ENTRY_DAT, 0x000008),
146 REG(VCAP_CACHE_MASK_DAT, 0x000108),
147 REG(VCAP_CACHE_ACTION_DAT, 0x000208),
148 REG(VCAP_CACHE_CNT_DAT, 0x000308),
149 REG(VCAP_CACHE_TG_DAT, 0x000388),
150 /* VCAP_CONST */
151 REG(VCAP_CONST_VCAP_VER, 0x000398),
152 REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c),
153 REG(VCAP_CONST_ENTRY_CNT, 0x0003a0),
154 REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4),
155 REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8),
156 REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac),
157 REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0),
158 REG(VCAP_CONST_CNT_WIDTH, 0x0003b4),
159 REG_RESERVED(VCAP_CONST_CORE_CNT),
160 REG_RESERVED(VCAP_CONST_IF_CNT),
161 };
162
163 static const u32 vsc9953_qsys_regmap[] = {
164 REG(QSYS_PORT_MODE, 0x003600),
165 REG(QSYS_SWITCH_PORT_MODE, 0x003630),
166 REG(QSYS_STAT_CNT_CFG, 0x00365c),
167 REG(QSYS_EEE_CFG, 0x003660),
168 REG(QSYS_EEE_THRES, 0x003688),
169 REG(QSYS_IGR_NO_SHARING, 0x00368c),
170 REG(QSYS_EGR_NO_SHARING, 0x003690),
171 REG(QSYS_SW_STATUS, 0x003694),
172 REG(QSYS_EXT_CPU_CFG, 0x0036c0),
173 REG_RESERVED(QSYS_PAD_CFG),
174 REG(QSYS_CPU_GROUP_MAP, 0x0036c8),
175 REG_RESERVED(QSYS_QMAP),
176 REG_RESERVED(QSYS_ISDX_SGRP),
177 REG_RESERVED(QSYS_TIMED_FRAME_ENTRY),
178 REG_RESERVED(QSYS_TFRM_MISC),
179 REG_RESERVED(QSYS_TFRM_PORT_DLY),
180 REG_RESERVED(QSYS_TFRM_TIMER_CFG_1),
181 REG_RESERVED(QSYS_TFRM_TIMER_CFG_2),
182 REG_RESERVED(QSYS_TFRM_TIMER_CFG_3),
183 REG_RESERVED(QSYS_TFRM_TIMER_CFG_4),
184 REG_RESERVED(QSYS_TFRM_TIMER_CFG_5),
185 REG_RESERVED(QSYS_TFRM_TIMER_CFG_6),
186 REG_RESERVED(QSYS_TFRM_TIMER_CFG_7),
187 REG_RESERVED(QSYS_TFRM_TIMER_CFG_8),
188 REG(QSYS_RED_PROFILE, 0x003724),
189 REG(QSYS_RES_QOS_MODE, 0x003764),
190 REG(QSYS_RES_CFG, 0x004000),
191 REG(QSYS_RES_STAT, 0x004004),
192 REG(QSYS_EGR_DROP_MODE, 0x003768),
193 REG(QSYS_EQ_CTRL, 0x00376c),
194 REG_RESERVED(QSYS_EVENTS_CORE),
195 REG_RESERVED(QSYS_QMAXSDU_CFG_0),
196 REG_RESERVED(QSYS_QMAXSDU_CFG_1),
197 REG_RESERVED(QSYS_QMAXSDU_CFG_2),
198 REG_RESERVED(QSYS_QMAXSDU_CFG_3),
199 REG_RESERVED(QSYS_QMAXSDU_CFG_4),
200 REG_RESERVED(QSYS_QMAXSDU_CFG_5),
201 REG_RESERVED(QSYS_QMAXSDU_CFG_6),
202 REG_RESERVED(QSYS_QMAXSDU_CFG_7),
203 REG_RESERVED(QSYS_PREEMPTION_CFG),
204 REG(QSYS_CIR_CFG, 0x000000),
205 REG_RESERVED(QSYS_EIR_CFG),
206 REG(QSYS_SE_CFG, 0x000008),
207 REG(QSYS_SE_DWRR_CFG, 0x00000c),
208 REG_RESERVED(QSYS_SE_CONNECT),
209 REG_RESERVED(QSYS_SE_DLB_SENSE),
210 REG(QSYS_CIR_STATE, 0x000044),
211 REG_RESERVED(QSYS_EIR_STATE),
212 REG_RESERVED(QSYS_SE_STATE),
213 REG(QSYS_HSCH_MISC_CFG, 0x003774),
214 REG_RESERVED(QSYS_TAG_CONFIG),
215 REG_RESERVED(QSYS_TAS_PARAM_CFG_CTRL),
216 REG_RESERVED(QSYS_PORT_MAX_SDU),
217 REG_RESERVED(QSYS_PARAM_CFG_REG_1),
218 REG_RESERVED(QSYS_PARAM_CFG_REG_2),
219 REG_RESERVED(QSYS_PARAM_CFG_REG_3),
220 REG_RESERVED(QSYS_PARAM_CFG_REG_4),
221 REG_RESERVED(QSYS_PARAM_CFG_REG_5),
222 REG_RESERVED(QSYS_GCL_CFG_REG_1),
223 REG_RESERVED(QSYS_GCL_CFG_REG_2),
224 REG_RESERVED(QSYS_PARAM_STATUS_REG_1),
225 REG_RESERVED(QSYS_PARAM_STATUS_REG_2),
226 REG_RESERVED(QSYS_PARAM_STATUS_REG_3),
227 REG_RESERVED(QSYS_PARAM_STATUS_REG_4),
228 REG_RESERVED(QSYS_PARAM_STATUS_REG_5),
229 REG_RESERVED(QSYS_PARAM_STATUS_REG_6),
230 REG_RESERVED(QSYS_PARAM_STATUS_REG_7),
231 REG_RESERVED(QSYS_PARAM_STATUS_REG_8),
232 REG_RESERVED(QSYS_PARAM_STATUS_REG_9),
233 REG_RESERVED(QSYS_GCL_STATUS_REG_1),
234 REG_RESERVED(QSYS_GCL_STATUS_REG_2),
235 };
236
237 static const u32 vsc9953_rew_regmap[] = {
238 REG(REW_PORT_VLAN_CFG, 0x000000),
239 REG(REW_TAG_CFG, 0x000004),
240 REG(REW_PORT_CFG, 0x000008),
241 REG(REW_DSCP_CFG, 0x00000c),
242 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010),
243 REG_RESERVED(REW_PTP_CFG),
244 REG_RESERVED(REW_PTP_DLY1_CFG),
245 REG_RESERVED(REW_RED_TAG_CFG),
246 REG(REW_DSCP_REMAP_DP1_CFG, 0x000610),
247 REG(REW_DSCP_REMAP_CFG, 0x000710),
248 REG_RESERVED(REW_STAT_CFG),
249 REG_RESERVED(REW_REW_STICKY),
250 REG_RESERVED(REW_PPT),
251 };
252
253 static const u32 vsc9953_sys_regmap[] = {
254 REG(SYS_COUNT_RX_OCTETS, 0x000000),
255 REG(SYS_COUNT_RX_MULTICAST, 0x000008),
256 REG(SYS_COUNT_RX_SHORTS, 0x000010),
257 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014),
258 REG(SYS_COUNT_RX_JABBERS, 0x000018),
259 REG(SYS_COUNT_RX_64, 0x000024),
260 REG(SYS_COUNT_RX_65_127, 0x000028),
261 REG(SYS_COUNT_RX_128_255, 0x00002c),
262 REG(SYS_COUNT_RX_256_1023, 0x000030),
263 REG(SYS_COUNT_RX_1024_1526, 0x000034),
264 REG(SYS_COUNT_RX_1527_MAX, 0x000038),
265 REG(SYS_COUNT_RX_LONGS, 0x000048),
266 REG(SYS_COUNT_TX_OCTETS, 0x000100),
267 REG(SYS_COUNT_TX_COLLISION, 0x000110),
268 REG(SYS_COUNT_TX_DROPS, 0x000114),
269 REG(SYS_COUNT_TX_64, 0x00011c),
270 REG(SYS_COUNT_TX_65_127, 0x000120),
271 REG(SYS_COUNT_TX_128_511, 0x000124),
272 REG(SYS_COUNT_TX_512_1023, 0x000128),
273 REG(SYS_COUNT_TX_1024_1526, 0x00012c),
274 REG(SYS_COUNT_TX_1527_MAX, 0x000130),
275 REG(SYS_COUNT_TX_AGING, 0x000178),
276 REG(SYS_RESET_CFG, 0x000318),
277 REG_RESERVED(SYS_SR_ETYPE_CFG),
278 REG(SYS_VLAN_ETYPE_CFG, 0x000320),
279 REG(SYS_PORT_MODE, 0x000324),
280 REG(SYS_FRONT_PORT_MODE, 0x000354),
281 REG(SYS_FRM_AGING, 0x00037c),
282 REG(SYS_STAT_CFG, 0x000380),
283 REG_RESERVED(SYS_SW_STATUS),
284 REG_RESERVED(SYS_MISC_CFG),
285 REG_RESERVED(SYS_REW_MAC_HIGH_CFG),
286 REG_RESERVED(SYS_REW_MAC_LOW_CFG),
287 REG_RESERVED(SYS_TIMESTAMP_OFFSET),
288 REG(SYS_PAUSE_CFG, 0x00044c),
289 REG(SYS_PAUSE_TOT_CFG, 0x000478),
290 REG(SYS_ATOP, 0x00047c),
291 REG(SYS_ATOP_TOT_CFG, 0x0004a8),
292 REG(SYS_MAC_FC_CFG, 0x0004ac),
293 REG(SYS_MMGT, 0x0004d4),
294 REG_RESERVED(SYS_MMGT_FAST),
295 REG_RESERVED(SYS_EVENTS_DIF),
296 REG_RESERVED(SYS_EVENTS_CORE),
297 REG_RESERVED(SYS_CNT),
298 REG_RESERVED(SYS_PTP_STATUS),
299 REG_RESERVED(SYS_PTP_TXSTAMP),
300 REG_RESERVED(SYS_PTP_NXT),
301 REG_RESERVED(SYS_PTP_CFG),
302 REG_RESERVED(SYS_RAM_INIT),
303 REG_RESERVED(SYS_CM_ADDR),
304 REG_RESERVED(SYS_CM_DATA_WR),
305 REG_RESERVED(SYS_CM_DATA_RD),
306 REG_RESERVED(SYS_CM_OP),
307 REG_RESERVED(SYS_CM_DATA),
308 };
309
310 static const u32 vsc9953_gcb_regmap[] = {
311 REG(GCB_SOFT_RST, 0x000008),
312 REG(GCB_MIIM_MII_STATUS, 0x0000ac),
313 REG(GCB_MIIM_MII_CMD, 0x0000b4),
314 REG(GCB_MIIM_MII_DATA, 0x0000b8),
315 };
316
317 static const u32 vsc9953_dev_gmii_regmap[] = {
318 REG(DEV_CLOCK_CFG, 0x0),
319 REG(DEV_PORT_MISC, 0x4),
320 REG_RESERVED(DEV_EVENTS),
321 REG(DEV_EEE_CFG, 0xc),
322 REG_RESERVED(DEV_RX_PATH_DELAY),
323 REG_RESERVED(DEV_TX_PATH_DELAY),
324 REG_RESERVED(DEV_PTP_PREDICT_CFG),
325 REG(DEV_MAC_ENA_CFG, 0x10),
326 REG(DEV_MAC_MODE_CFG, 0x14),
327 REG(DEV_MAC_MAXLEN_CFG, 0x18),
328 REG(DEV_MAC_TAGS_CFG, 0x1c),
329 REG(DEV_MAC_ADV_CHK_CFG, 0x20),
330 REG(DEV_MAC_IFG_CFG, 0x24),
331 REG(DEV_MAC_HDX_CFG, 0x28),
332 REG_RESERVED(DEV_MAC_DBG_CFG),
333 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x30),
334 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x34),
335 REG(DEV_MAC_STICKY, 0x38),
336 REG_RESERVED(PCS1G_CFG),
337 REG_RESERVED(PCS1G_MODE_CFG),
338 REG_RESERVED(PCS1G_SD_CFG),
339 REG_RESERVED(PCS1G_ANEG_CFG),
340 REG_RESERVED(PCS1G_ANEG_NP_CFG),
341 REG_RESERVED(PCS1G_LB_CFG),
342 REG_RESERVED(PCS1G_DBG_CFG),
343 REG_RESERVED(PCS1G_CDET_CFG),
344 REG_RESERVED(PCS1G_ANEG_STATUS),
345 REG_RESERVED(PCS1G_ANEG_NP_STATUS),
346 REG_RESERVED(PCS1G_LINK_STATUS),
347 REG_RESERVED(PCS1G_LINK_DOWN_CNT),
348 REG_RESERVED(PCS1G_STICKY),
349 REG_RESERVED(PCS1G_DEBUG_STATUS),
350 REG_RESERVED(PCS1G_LPI_CFG),
351 REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT),
352 REG_RESERVED(PCS1G_LPI_STATUS),
353 REG_RESERVED(PCS1G_TSTPAT_MODE_CFG),
354 REG_RESERVED(PCS1G_TSTPAT_STATUS),
355 REG_RESERVED(DEV_PCS_FX100_CFG),
356 REG_RESERVED(DEV_PCS_FX100_STATUS),
357 };
358
359 static const u32 *vsc9953_regmap[TARGET_MAX] = {
360 [ANA] = vsc9953_ana_regmap,
361 [QS] = vsc9953_qs_regmap,
362 [QSYS] = vsc9953_qsys_regmap,
363 [REW] = vsc9953_rew_regmap,
364 [SYS] = vsc9953_sys_regmap,
365 [S0] = vsc9953_vcap_regmap,
366 [S1] = vsc9953_vcap_regmap,
367 [S2] = vsc9953_vcap_regmap,
368 [GCB] = vsc9953_gcb_regmap,
369 [DEV_GMII] = vsc9953_dev_gmii_regmap,
370 };
371
372 /* Addresses are relative to the device's base address */
373 static const struct resource vsc9953_target_io_res[TARGET_MAX] = {
374 [ANA] = {
375 .start = 0x0280000,
376 .end = 0x028ffff,
377 .name = "ana",
378 },
379 [QS] = {
380 .start = 0x0080000,
381 .end = 0x00800ff,
382 .name = "qs",
383 },
384 [QSYS] = {
385 .start = 0x0200000,
386 .end = 0x021ffff,
387 .name = "qsys",
388 },
389 [REW] = {
390 .start = 0x0030000,
391 .end = 0x003ffff,
392 .name = "rew",
393 },
394 [SYS] = {
395 .start = 0x0010000,
396 .end = 0x001ffff,
397 .name = "sys",
398 },
399 [S0] = {
400 .start = 0x0040000,
401 .end = 0x00403ff,
402 .name = "s0",
403 },
404 [S1] = {
405 .start = 0x0050000,
406 .end = 0x00503ff,
407 .name = "s1",
408 },
409 [S2] = {
410 .start = 0x0060000,
411 .end = 0x00603ff,
412 .name = "s2",
413 },
414 [PTP] = {
415 .start = 0x0090000,
416 .end = 0x00900cb,
417 .name = "ptp",
418 },
419 [GCB] = {
420 .start = 0x0070000,
421 .end = 0x00701ff,
422 .name = "devcpu_gcb",
423 },
424 };
425
426 static const struct resource vsc9953_port_io_res[] = {
427 {
428 .start = 0x0100000,
429 .end = 0x010ffff,
430 .name = "port0",
431 },
432 {
433 .start = 0x0110000,
434 .end = 0x011ffff,
435 .name = "port1",
436 },
437 {
438 .start = 0x0120000,
439 .end = 0x012ffff,
440 .name = "port2",
441 },
442 {
443 .start = 0x0130000,
444 .end = 0x013ffff,
445 .name = "port3",
446 },
447 {
448 .start = 0x0140000,
449 .end = 0x014ffff,
450 .name = "port4",
451 },
452 {
453 .start = 0x0150000,
454 .end = 0x015ffff,
455 .name = "port5",
456 },
457 {
458 .start = 0x0160000,
459 .end = 0x016ffff,
460 .name = "port6",
461 },
462 {
463 .start = 0x0170000,
464 .end = 0x017ffff,
465 .name = "port7",
466 },
467 {
468 .start = 0x0180000,
469 .end = 0x018ffff,
470 .name = "port8",
471 },
472 {
473 .start = 0x0190000,
474 .end = 0x019ffff,
475 .name = "port9",
476 },
477 };
478
479 static const struct reg_field vsc9953_regfields[REGFIELD_MAX] = {
480 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 10, 10),
481 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 9),
482 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24),
483 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22),
484 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21),
485 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20),
486 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19),
487 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18),
488 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17),
489 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16),
490 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15),
491 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13),
492 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12),
493 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11),
494 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10),
495 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9),
496 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8),
497 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7),
498 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6),
499 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5),
500 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4),
501 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3),
502 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2),
503 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1),
504 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0),
505 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16),
506 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12),
507 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10),
508 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 7, 7),
509 [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 6, 6),
510 [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 5, 5),
511 [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0),
512 [GCB_MIIM_MII_STATUS_PENDING] = REG_FIELD(GCB_MIIM_MII_STATUS, 2, 2),
513 [GCB_MIIM_MII_STATUS_BUSY] = REG_FIELD(GCB_MIIM_MII_STATUS, 3, 3),
514 /* Replicated per number of ports (11), register size 4 per port */
515 [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 13, 13, 11, 4),
516 [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 11, 4),
517 [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 11, 4),
518 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 11, 4),
519 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 11, 4),
520 [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 4, 5, 11, 4),
521 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 2, 3, 11, 4),
522 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 11, 4),
523 [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 11, 20, 11, 4),
524 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 10, 11, 4),
525 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 11, 4),
526 };
527
528 static const struct ocelot_stat_layout vsc9953_stats_layout[] = {
529 { .offset = 0x00, .name = "rx_octets", },
530 { .offset = 0x01, .name = "rx_unicast", },
531 { .offset = 0x02, .name = "rx_multicast", },
532 { .offset = 0x03, .name = "rx_broadcast", },
533 { .offset = 0x04, .name = "rx_shorts", },
534 { .offset = 0x05, .name = "rx_fragments", },
535 { .offset = 0x06, .name = "rx_jabbers", },
536 { .offset = 0x07, .name = "rx_crc_align_errs", },
537 { .offset = 0x08, .name = "rx_sym_errs", },
538 { .offset = 0x09, .name = "rx_frames_below_65_octets", },
539 { .offset = 0x0A, .name = "rx_frames_65_to_127_octets", },
540 { .offset = 0x0B, .name = "rx_frames_128_to_255_octets", },
541 { .offset = 0x0C, .name = "rx_frames_256_to_511_octets", },
542 { .offset = 0x0D, .name = "rx_frames_512_to_1023_octets", },
543 { .offset = 0x0E, .name = "rx_frames_1024_to_1526_octets", },
544 { .offset = 0x0F, .name = "rx_frames_over_1526_octets", },
545 { .offset = 0x10, .name = "rx_pause", },
546 { .offset = 0x11, .name = "rx_control", },
547 { .offset = 0x12, .name = "rx_longs", },
548 { .offset = 0x13, .name = "rx_classified_drops", },
549 { .offset = 0x14, .name = "rx_red_prio_0", },
550 { .offset = 0x15, .name = "rx_red_prio_1", },
551 { .offset = 0x16, .name = "rx_red_prio_2", },
552 { .offset = 0x17, .name = "rx_red_prio_3", },
553 { .offset = 0x18, .name = "rx_red_prio_4", },
554 { .offset = 0x19, .name = "rx_red_prio_5", },
555 { .offset = 0x1A, .name = "rx_red_prio_6", },
556 { .offset = 0x1B, .name = "rx_red_prio_7", },
557 { .offset = 0x1C, .name = "rx_yellow_prio_0", },
558 { .offset = 0x1D, .name = "rx_yellow_prio_1", },
559 { .offset = 0x1E, .name = "rx_yellow_prio_2", },
560 { .offset = 0x1F, .name = "rx_yellow_prio_3", },
561 { .offset = 0x20, .name = "rx_yellow_prio_4", },
562 { .offset = 0x21, .name = "rx_yellow_prio_5", },
563 { .offset = 0x22, .name = "rx_yellow_prio_6", },
564 { .offset = 0x23, .name = "rx_yellow_prio_7", },
565 { .offset = 0x24, .name = "rx_green_prio_0", },
566 { .offset = 0x25, .name = "rx_green_prio_1", },
567 { .offset = 0x26, .name = "rx_green_prio_2", },
568 { .offset = 0x27, .name = "rx_green_prio_3", },
569 { .offset = 0x28, .name = "rx_green_prio_4", },
570 { .offset = 0x29, .name = "rx_green_prio_5", },
571 { .offset = 0x2A, .name = "rx_green_prio_6", },
572 { .offset = 0x2B, .name = "rx_green_prio_7", },
573 { .offset = 0x40, .name = "tx_octets", },
574 { .offset = 0x41, .name = "tx_unicast", },
575 { .offset = 0x42, .name = "tx_multicast", },
576 { .offset = 0x43, .name = "tx_broadcast", },
577 { .offset = 0x44, .name = "tx_collision", },
578 { .offset = 0x45, .name = "tx_drops", },
579 { .offset = 0x46, .name = "tx_pause", },
580 { .offset = 0x47, .name = "tx_frames_below_65_octets", },
581 { .offset = 0x48, .name = "tx_frames_65_to_127_octets", },
582 { .offset = 0x49, .name = "tx_frames_128_255_octets", },
583 { .offset = 0x4A, .name = "tx_frames_256_511_octets", },
584 { .offset = 0x4B, .name = "tx_frames_512_1023_octets", },
585 { .offset = 0x4C, .name = "tx_frames_1024_1526_octets", },
586 { .offset = 0x4D, .name = "tx_frames_over_1526_octets", },
587 { .offset = 0x4E, .name = "tx_yellow_prio_0", },
588 { .offset = 0x4F, .name = "tx_yellow_prio_1", },
589 { .offset = 0x50, .name = "tx_yellow_prio_2", },
590 { .offset = 0x51, .name = "tx_yellow_prio_3", },
591 { .offset = 0x52, .name = "tx_yellow_prio_4", },
592 { .offset = 0x53, .name = "tx_yellow_prio_5", },
593 { .offset = 0x54, .name = "tx_yellow_prio_6", },
594 { .offset = 0x55, .name = "tx_yellow_prio_7", },
595 { .offset = 0x56, .name = "tx_green_prio_0", },
596 { .offset = 0x57, .name = "tx_green_prio_1", },
597 { .offset = 0x58, .name = "tx_green_prio_2", },
598 { .offset = 0x59, .name = "tx_green_prio_3", },
599 { .offset = 0x5A, .name = "tx_green_prio_4", },
600 { .offset = 0x5B, .name = "tx_green_prio_5", },
601 { .offset = 0x5C, .name = "tx_green_prio_6", },
602 { .offset = 0x5D, .name = "tx_green_prio_7", },
603 { .offset = 0x5E, .name = "tx_aged", },
604 { .offset = 0x80, .name = "drop_local", },
605 { .offset = 0x81, .name = "drop_tail", },
606 { .offset = 0x82, .name = "drop_yellow_prio_0", },
607 { .offset = 0x83, .name = "drop_yellow_prio_1", },
608 { .offset = 0x84, .name = "drop_yellow_prio_2", },
609 { .offset = 0x85, .name = "drop_yellow_prio_3", },
610 { .offset = 0x86, .name = "drop_yellow_prio_4", },
611 { .offset = 0x87, .name = "drop_yellow_prio_5", },
612 { .offset = 0x88, .name = "drop_yellow_prio_6", },
613 { .offset = 0x89, .name = "drop_yellow_prio_7", },
614 { .offset = 0x8A, .name = "drop_green_prio_0", },
615 { .offset = 0x8B, .name = "drop_green_prio_1", },
616 { .offset = 0x8C, .name = "drop_green_prio_2", },
617 { .offset = 0x8D, .name = "drop_green_prio_3", },
618 { .offset = 0x8E, .name = "drop_green_prio_4", },
619 { .offset = 0x8F, .name = "drop_green_prio_5", },
620 { .offset = 0x90, .name = "drop_green_prio_6", },
621 { .offset = 0x91, .name = "drop_green_prio_7", },
622 };
623
624 static const struct vcap_field vsc9953_vcap_es0_keys[] = {
625 [VCAP_ES0_EGR_PORT] = { 0, 4},
626 [VCAP_ES0_IGR_PORT] = { 4, 4},
627 [VCAP_ES0_RSV] = { 8, 2},
628 [VCAP_ES0_L2_MC] = { 10, 1},
629 [VCAP_ES0_L2_BC] = { 11, 1},
630 [VCAP_ES0_VID] = { 12, 12},
631 [VCAP_ES0_DP] = { 24, 1},
632 [VCAP_ES0_PCP] = { 25, 3},
633 };
634
635 static const struct vcap_field vsc9953_vcap_es0_actions[] = {
636 [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2},
637 [VCAP_ES0_ACT_PUSH_INNER_TAG] = { 2, 1},
638 [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { 3, 2},
639 [VCAP_ES0_ACT_TAG_A_VID_SEL] = { 5, 1},
640 [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { 6, 2},
641 [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { 8, 2},
642 [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { 10, 2},
643 [VCAP_ES0_ACT_TAG_B_VID_SEL] = { 12, 1},
644 [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { 13, 2},
645 [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { 15, 2},
646 [VCAP_ES0_ACT_VID_A_VAL] = { 17, 12},
647 [VCAP_ES0_ACT_PCP_A_VAL] = { 29, 3},
648 [VCAP_ES0_ACT_DEI_A_VAL] = { 32, 1},
649 [VCAP_ES0_ACT_VID_B_VAL] = { 33, 12},
650 [VCAP_ES0_ACT_PCP_B_VAL] = { 45, 3},
651 [VCAP_ES0_ACT_DEI_B_VAL] = { 48, 1},
652 [VCAP_ES0_ACT_RSV] = { 49, 24},
653 [VCAP_ES0_ACT_HIT_STICKY] = { 73, 1},
654 };
655
656 static const struct vcap_field vsc9953_vcap_is1_keys[] = {
657 [VCAP_IS1_HK_TYPE] = { 0, 1},
658 [VCAP_IS1_HK_LOOKUP] = { 1, 2},
659 [VCAP_IS1_HK_IGR_PORT_MASK] = { 3, 11},
660 [VCAP_IS1_HK_RSV] = { 14, 10},
661 /* VCAP_IS1_HK_OAM_Y1731 not supported */
662 [VCAP_IS1_HK_L2_MC] = { 24, 1},
663 [VCAP_IS1_HK_L2_BC] = { 25, 1},
664 [VCAP_IS1_HK_IP_MC] = { 26, 1},
665 [VCAP_IS1_HK_VLAN_TAGGED] = { 27, 1},
666 [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { 28, 1},
667 [VCAP_IS1_HK_TPID] = { 29, 1},
668 [VCAP_IS1_HK_VID] = { 30, 12},
669 [VCAP_IS1_HK_DEI] = { 42, 1},
670 [VCAP_IS1_HK_PCP] = { 43, 3},
671 /* Specific Fields for IS1 Half Key S1_NORMAL */
672 [VCAP_IS1_HK_L2_SMAC] = { 46, 48},
673 [VCAP_IS1_HK_ETYPE_LEN] = { 94, 1},
674 [VCAP_IS1_HK_ETYPE] = { 95, 16},
675 [VCAP_IS1_HK_IP_SNAP] = {111, 1},
676 [VCAP_IS1_HK_IP4] = {112, 1},
677 /* Layer-3 Information */
678 [VCAP_IS1_HK_L3_FRAGMENT] = {113, 1},
679 [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = {114, 1},
680 [VCAP_IS1_HK_L3_OPTIONS] = {115, 1},
681 [VCAP_IS1_HK_L3_DSCP] = {116, 6},
682 [VCAP_IS1_HK_L3_IP4_SIP] = {122, 32},
683 /* Layer-4 Information */
684 [VCAP_IS1_HK_TCP_UDP] = {154, 1},
685 [VCAP_IS1_HK_TCP] = {155, 1},
686 [VCAP_IS1_HK_L4_SPORT] = {156, 16},
687 [VCAP_IS1_HK_L4_RNG] = {172, 8},
688 /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */
689 [VCAP_IS1_HK_IP4_INNER_TPID] = { 46, 1},
690 [VCAP_IS1_HK_IP4_INNER_VID] = { 47, 12},
691 [VCAP_IS1_HK_IP4_INNER_DEI] = { 59, 1},
692 [VCAP_IS1_HK_IP4_INNER_PCP] = { 60, 3},
693 [VCAP_IS1_HK_IP4_IP4] = { 63, 1},
694 [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { 64, 1},
695 [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { 65, 1},
696 [VCAP_IS1_HK_IP4_L3_OPTIONS] = { 66, 1},
697 [VCAP_IS1_HK_IP4_L3_DSCP] = { 67, 6},
698 [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { 73, 32},
699 [VCAP_IS1_HK_IP4_L3_IP4_SIP] = {105, 32},
700 [VCAP_IS1_HK_IP4_L3_PROTO] = {137, 8},
701 [VCAP_IS1_HK_IP4_TCP_UDP] = {145, 1},
702 [VCAP_IS1_HK_IP4_TCP] = {146, 1},
703 [VCAP_IS1_HK_IP4_L4_RNG] = {147, 8},
704 [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = {155, 32},
705 };
706
707 static const struct vcap_field vsc9953_vcap_is1_actions[] = {
708 [VCAP_IS1_ACT_DSCP_ENA] = { 0, 1},
709 [VCAP_IS1_ACT_DSCP_VAL] = { 1, 6},
710 [VCAP_IS1_ACT_QOS_ENA] = { 7, 1},
711 [VCAP_IS1_ACT_QOS_VAL] = { 8, 3},
712 [VCAP_IS1_ACT_DP_ENA] = { 11, 1},
713 [VCAP_IS1_ACT_DP_VAL] = { 12, 1},
714 [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { 13, 8},
715 [VCAP_IS1_ACT_PAG_VAL] = { 21, 8},
716 [VCAP_IS1_ACT_RSV] = { 29, 11},
717 [VCAP_IS1_ACT_VID_REPLACE_ENA] = { 40, 1},
718 [VCAP_IS1_ACT_VID_ADD_VAL] = { 41, 12},
719 [VCAP_IS1_ACT_FID_SEL] = { 53, 2},
720 [VCAP_IS1_ACT_FID_VAL] = { 55, 13},
721 [VCAP_IS1_ACT_PCP_DEI_ENA] = { 68, 1},
722 [VCAP_IS1_ACT_PCP_VAL] = { 69, 3},
723 [VCAP_IS1_ACT_DEI_VAL] = { 72, 1},
724 [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { 73, 1},
725 [VCAP_IS1_ACT_VLAN_POP_CNT] = { 74, 2},
726 [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { 76, 4},
727 [VCAP_IS1_ACT_HIT_STICKY] = { 80, 1},
728 };
729
730 static struct vcap_field vsc9953_vcap_is2_keys[] = {
731 /* Common: 41 bits */
732 [VCAP_IS2_TYPE] = { 0, 4},
733 [VCAP_IS2_HK_FIRST] = { 4, 1},
734 [VCAP_IS2_HK_PAG] = { 5, 8},
735 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 11},
736 [VCAP_IS2_HK_RSV2] = { 24, 1},
737 [VCAP_IS2_HK_HOST_MATCH] = { 25, 1},
738 [VCAP_IS2_HK_L2_MC] = { 26, 1},
739 [VCAP_IS2_HK_L2_BC] = { 27, 1},
740 [VCAP_IS2_HK_VLAN_TAGGED] = { 28, 1},
741 [VCAP_IS2_HK_VID] = { 29, 12},
742 [VCAP_IS2_HK_DEI] = { 41, 1},
743 [VCAP_IS2_HK_PCP] = { 42, 3},
744 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */
745 [VCAP_IS2_HK_L2_DMAC] = { 45, 48},
746 [VCAP_IS2_HK_L2_SMAC] = { 93, 48},
747 /* MAC_ETYPE (TYPE=000) */
748 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {141, 16},
749 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {157, 16},
750 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {173, 8},
751 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {181, 3},
752 /* MAC_LLC (TYPE=001) */
753 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {141, 40},
754 /* MAC_SNAP (TYPE=010) */
755 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {141, 40},
756 /* MAC_ARP (TYPE=011) */
757 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 45, 48},
758 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 93, 1},
759 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 94, 1},
760 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 95, 1},
761 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 96, 1},
762 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 97, 1},
763 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 98, 1},
764 [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 99, 2},
765 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = {101, 32},
766 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {133, 32},
767 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {165, 1},
768 /* IP4_TCP_UDP / IP4_OTHER common */
769 [VCAP_IS2_HK_IP4] = { 45, 1},
770 [VCAP_IS2_HK_L3_FRAGMENT] = { 46, 1},
771 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 47, 1},
772 [VCAP_IS2_HK_L3_OPTIONS] = { 48, 1},
773 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 49, 1},
774 [VCAP_IS2_HK_L3_TOS] = { 50, 8},
775 [VCAP_IS2_HK_L3_IP4_DIP] = { 58, 32},
776 [VCAP_IS2_HK_L3_IP4_SIP] = { 90, 32},
777 [VCAP_IS2_HK_DIP_EQ_SIP] = {122, 1},
778 /* IP4_TCP_UDP (TYPE=100) */
779 [VCAP_IS2_HK_TCP] = {123, 1},
780 [VCAP_IS2_HK_L4_DPORT] = {124, 16},
781 [VCAP_IS2_HK_L4_SPORT] = {140, 16},
782 [VCAP_IS2_HK_L4_RNG] = {156, 8},
783 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {164, 1},
784 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {165, 1},
785 [VCAP_IS2_HK_L4_FIN] = {166, 1},
786 [VCAP_IS2_HK_L4_SYN] = {167, 1},
787 [VCAP_IS2_HK_L4_RST] = {168, 1},
788 [VCAP_IS2_HK_L4_PSH] = {169, 1},
789 [VCAP_IS2_HK_L4_ACK] = {170, 1},
790 [VCAP_IS2_HK_L4_URG] = {171, 1},
791 /* IP4_OTHER (TYPE=101) */
792 [VCAP_IS2_HK_IP4_L3_PROTO] = {123, 8},
793 [VCAP_IS2_HK_L3_PAYLOAD] = {131, 56},
794 /* IP6_STD (TYPE=110) */
795 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 45, 1},
796 [VCAP_IS2_HK_L3_IP6_SIP] = { 46, 128},
797 [VCAP_IS2_HK_IP6_L3_PROTO] = {174, 8},
798 };
799
800 static struct vcap_field vsc9953_vcap_is2_actions[] = {
801 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1},
802 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1},
803 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3},
804 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2},
805 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1},
806 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1},
807 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1},
808 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 8},
809 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 21, 1},
810 [VCAP_IS2_ACT_PORT_MASK] = { 22, 10},
811 [VCAP_IS2_ACT_ACL_ID] = { 44, 6},
812 [VCAP_IS2_ACT_HIT_CNT] = { 50, 32},
813 };
814
815 static struct vcap_props vsc9953_vcap_props[] = {
816 [VCAP_ES0] = {
817 .action_type_width = 0,
818 .action_table = {
819 [ES0_ACTION_TYPE_NORMAL] = {
820 .width = 73, /* HIT_STICKY not included */
821 .count = 1,
822 },
823 },
824 .target = S0,
825 .keys = vsc9953_vcap_es0_keys,
826 .actions = vsc9953_vcap_es0_actions,
827 },
828 [VCAP_IS1] = {
829 .action_type_width = 0,
830 .action_table = {
831 [IS1_ACTION_TYPE_NORMAL] = {
832 .width = 80, /* HIT_STICKY not included */
833 .count = 4,
834 },
835 },
836 .target = S1,
837 .keys = vsc9953_vcap_is1_keys,
838 .actions = vsc9953_vcap_is1_actions,
839 },
840 [VCAP_IS2] = {
841 .action_type_width = 1,
842 .action_table = {
843 [IS2_ACTION_TYPE_NORMAL] = {
844 .width = 50, /* HIT_CNT not included */
845 .count = 2
846 },
847 [IS2_ACTION_TYPE_SMAC_SIP] = {
848 .width = 6,
849 .count = 4
850 },
851 },
852 .target = S2,
853 .keys = vsc9953_vcap_is2_keys,
854 .actions = vsc9953_vcap_is2_actions,
855 },
856 };
857
858 #define VSC9953_INIT_TIMEOUT 50000
859 #define VSC9953_GCB_RST_SLEEP 100
860 #define VSC9953_SYS_RAMINIT_SLEEP 80
861 #define VCS9953_MII_TIMEOUT 10000
862
vsc9953_gcb_soft_rst_status(struct ocelot * ocelot)863 static int vsc9953_gcb_soft_rst_status(struct ocelot *ocelot)
864 {
865 int val;
866
867 ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val);
868
869 return val;
870 }
871
vsc9953_sys_ram_init_status(struct ocelot * ocelot)872 static int vsc9953_sys_ram_init_status(struct ocelot *ocelot)
873 {
874 int val;
875
876 ocelot_field_read(ocelot, SYS_RESET_CFG_MEM_INIT, &val);
877
878 return val;
879 }
880
vsc9953_gcb_miim_pending_status(struct ocelot * ocelot)881 static int vsc9953_gcb_miim_pending_status(struct ocelot *ocelot)
882 {
883 int val;
884
885 ocelot_field_read(ocelot, GCB_MIIM_MII_STATUS_PENDING, &val);
886
887 return val;
888 }
889
vsc9953_gcb_miim_busy_status(struct ocelot * ocelot)890 static int vsc9953_gcb_miim_busy_status(struct ocelot *ocelot)
891 {
892 int val;
893
894 ocelot_field_read(ocelot, GCB_MIIM_MII_STATUS_BUSY, &val);
895
896 return val;
897 }
898
vsc9953_mdio_write(struct mii_bus * bus,int phy_id,int regnum,u16 value)899 static int vsc9953_mdio_write(struct mii_bus *bus, int phy_id, int regnum,
900 u16 value)
901 {
902 struct ocelot *ocelot = bus->priv;
903 int err, cmd, val;
904
905 /* Wait while MIIM controller becomes idle */
906 err = readx_poll_timeout(vsc9953_gcb_miim_pending_status, ocelot,
907 val, !val, 10, VCS9953_MII_TIMEOUT);
908 if (err) {
909 dev_err(ocelot->dev, "MDIO write: pending timeout\n");
910 goto out;
911 }
912
913 cmd = MSCC_MIIM_CMD_VLD | (phy_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
914 (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) |
915 (value << MSCC_MIIM_CMD_WRDATA_SHIFT) |
916 MSCC_MIIM_CMD_OPR_WRITE;
917
918 ocelot_write(ocelot, cmd, GCB_MIIM_MII_CMD);
919
920 out:
921 return err;
922 }
923
vsc9953_mdio_read(struct mii_bus * bus,int phy_id,int regnum)924 static int vsc9953_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
925 {
926 struct ocelot *ocelot = bus->priv;
927 int err, cmd, val;
928
929 /* Wait until MIIM controller becomes idle */
930 err = readx_poll_timeout(vsc9953_gcb_miim_pending_status, ocelot,
931 val, !val, 10, VCS9953_MII_TIMEOUT);
932 if (err) {
933 dev_err(ocelot->dev, "MDIO read: pending timeout\n");
934 goto out;
935 }
936
937 /* Write the MIIM COMMAND register */
938 cmd = MSCC_MIIM_CMD_VLD | (phy_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
939 (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) | MSCC_MIIM_CMD_OPR_READ;
940
941 ocelot_write(ocelot, cmd, GCB_MIIM_MII_CMD);
942
943 /* Wait while read operation via the MIIM controller is in progress */
944 err = readx_poll_timeout(vsc9953_gcb_miim_busy_status, ocelot,
945 val, !val, 10, VCS9953_MII_TIMEOUT);
946 if (err) {
947 dev_err(ocelot->dev, "MDIO read: busy timeout\n");
948 goto out;
949 }
950
951 val = ocelot_read(ocelot, GCB_MIIM_MII_DATA);
952
953 err = val & 0xFFFF;
954 out:
955 return err;
956 }
957
958 /* CORE_ENA is in SYS:SYSTEM:RESET_CFG
959 * MEM_INIT is in SYS:SYSTEM:RESET_CFG
960 * MEM_ENA is in SYS:SYSTEM:RESET_CFG
961 */
vsc9953_reset(struct ocelot * ocelot)962 static int vsc9953_reset(struct ocelot *ocelot)
963 {
964 int val, err;
965
966 /* soft-reset the switch core */
967 ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1);
968
969 err = readx_poll_timeout(vsc9953_gcb_soft_rst_status, ocelot, val, !val,
970 VSC9953_GCB_RST_SLEEP, VSC9953_INIT_TIMEOUT);
971 if (err) {
972 dev_err(ocelot->dev, "timeout: switch core reset\n");
973 return err;
974 }
975
976 /* initialize switch mem ~40us */
977 ocelot_field_write(ocelot, SYS_RESET_CFG_MEM_ENA, 1);
978 ocelot_field_write(ocelot, SYS_RESET_CFG_MEM_INIT, 1);
979
980 err = readx_poll_timeout(vsc9953_sys_ram_init_status, ocelot, val, !val,
981 VSC9953_SYS_RAMINIT_SLEEP,
982 VSC9953_INIT_TIMEOUT);
983 if (err) {
984 dev_err(ocelot->dev, "timeout: switch sram init\n");
985 return err;
986 }
987
988 /* enable switch core */
989 ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1);
990
991 return 0;
992 }
993
vsc9953_phylink_validate(struct ocelot * ocelot,int port,unsigned long * supported,struct phylink_link_state * state)994 static void vsc9953_phylink_validate(struct ocelot *ocelot, int port,
995 unsigned long *supported,
996 struct phylink_link_state *state)
997 {
998 struct ocelot_port *ocelot_port = ocelot->ports[port];
999 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1000
1001 if (state->interface != PHY_INTERFACE_MODE_NA &&
1002 state->interface != ocelot_port->phy_mode) {
1003 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1004 return;
1005 }
1006
1007 phylink_set_port_modes(mask);
1008 phylink_set(mask, Autoneg);
1009 phylink_set(mask, Pause);
1010 phylink_set(mask, Asym_Pause);
1011 phylink_set(mask, 10baseT_Full);
1012 phylink_set(mask, 10baseT_Half);
1013 phylink_set(mask, 100baseT_Full);
1014 phylink_set(mask, 100baseT_Half);
1015 phylink_set(mask, 1000baseT_Full);
1016
1017 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
1018 phylink_set(mask, 2500baseT_Full);
1019 phylink_set(mask, 2500baseX_Full);
1020 }
1021
1022 bitmap_and(supported, supported, mask,
1023 __ETHTOOL_LINK_MODE_MASK_NBITS);
1024 bitmap_and(state->advertising, state->advertising, mask,
1025 __ETHTOOL_LINK_MODE_MASK_NBITS);
1026 }
1027
vsc9953_prevalidate_phy_mode(struct ocelot * ocelot,int port,phy_interface_t phy_mode)1028 static int vsc9953_prevalidate_phy_mode(struct ocelot *ocelot, int port,
1029 phy_interface_t phy_mode)
1030 {
1031 switch (phy_mode) {
1032 case PHY_INTERFACE_MODE_INTERNAL:
1033 if (port != 8 && port != 9)
1034 return -ENOTSUPP;
1035 return 0;
1036 case PHY_INTERFACE_MODE_SGMII:
1037 case PHY_INTERFACE_MODE_QSGMII:
1038 /* Not supported on internal to-CPU ports */
1039 if (port == 8 || port == 9)
1040 return -ENOTSUPP;
1041 return 0;
1042 default:
1043 return -ENOTSUPP;
1044 }
1045 }
1046
1047 /* Watermark encode
1048 * Bit 9: Unit; 0:1, 1:16
1049 * Bit 8-0: Value to be multiplied with unit
1050 */
vsc9953_wm_enc(u16 value)1051 static u16 vsc9953_wm_enc(u16 value)
1052 {
1053 WARN_ON(value >= 16 * BIT(9));
1054
1055 if (value >= BIT(9))
1056 return BIT(9) | (value / 16);
1057
1058 return value;
1059 }
1060
vsc9953_wm_dec(u16 wm)1061 static u16 vsc9953_wm_dec(u16 wm)
1062 {
1063 WARN_ON(wm & ~GENMASK(9, 0));
1064
1065 if (wm & BIT(9))
1066 return (wm & GENMASK(8, 0)) * 16;
1067
1068 return wm;
1069 }
1070
vsc9953_wm_stat(u32 val,u32 * inuse,u32 * maxuse)1071 static void vsc9953_wm_stat(u32 val, u32 *inuse, u32 *maxuse)
1072 {
1073 *inuse = (val & GENMASK(25, 13)) >> 13;
1074 *maxuse = val & GENMASK(12, 0);
1075 }
1076
1077 static const struct ocelot_ops vsc9953_ops = {
1078 .reset = vsc9953_reset,
1079 .wm_enc = vsc9953_wm_enc,
1080 .wm_dec = vsc9953_wm_dec,
1081 .wm_stat = vsc9953_wm_stat,
1082 .port_to_netdev = felix_port_to_netdev,
1083 .netdev_to_port = felix_netdev_to_port,
1084 };
1085
vsc9953_mdio_bus_alloc(struct ocelot * ocelot)1086 static int vsc9953_mdio_bus_alloc(struct ocelot *ocelot)
1087 {
1088 struct felix *felix = ocelot_to_felix(ocelot);
1089 struct device *dev = ocelot->dev;
1090 struct mii_bus *bus;
1091 int port;
1092 int rc;
1093
1094 felix->pcs = devm_kcalloc(dev, felix->info->num_ports,
1095 sizeof(struct phy_device *),
1096 GFP_KERNEL);
1097 if (!felix->pcs) {
1098 dev_err(dev, "failed to allocate array for PCS PHYs\n");
1099 return -ENOMEM;
1100 }
1101
1102 bus = devm_mdiobus_alloc(dev);
1103 if (!bus)
1104 return -ENOMEM;
1105
1106 bus->name = "VSC9953 internal MDIO bus";
1107 bus->read = vsc9953_mdio_read;
1108 bus->write = vsc9953_mdio_write;
1109 bus->parent = dev;
1110 bus->priv = ocelot;
1111 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
1112
1113 /* Needed in order to initialize the bus mutex lock */
1114 rc = devm_of_mdiobus_register(dev, bus, NULL);
1115 if (rc < 0) {
1116 dev_err(dev, "failed to register MDIO bus\n");
1117 return rc;
1118 }
1119
1120 felix->imdio = bus;
1121
1122 for (port = 0; port < felix->info->num_ports; port++) {
1123 struct ocelot_port *ocelot_port = ocelot->ports[port];
1124 int addr = port + 4;
1125 struct mdio_device *pcs;
1126 struct lynx_pcs *lynx;
1127
1128 if (dsa_is_unused_port(felix->ds, port))
1129 continue;
1130
1131 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL)
1132 continue;
1133
1134 pcs = mdio_device_create(felix->imdio, addr);
1135 if (IS_ERR(pcs))
1136 continue;
1137
1138 lynx = lynx_pcs_create(pcs);
1139 if (!lynx) {
1140 mdio_device_free(pcs);
1141 continue;
1142 }
1143
1144 felix->pcs[port] = lynx;
1145
1146 dev_info(dev, "Found PCS at internal MDIO address %d\n", addr);
1147 }
1148
1149 return 0;
1150 }
1151
vsc9953_mdio_bus_free(struct ocelot * ocelot)1152 static void vsc9953_mdio_bus_free(struct ocelot *ocelot)
1153 {
1154 struct felix *felix = ocelot_to_felix(ocelot);
1155 int port;
1156
1157 for (port = 0; port < ocelot->num_phys_ports; port++) {
1158 struct lynx_pcs *pcs = felix->pcs[port];
1159
1160 if (!pcs)
1161 continue;
1162
1163 mdio_device_free(pcs->mdio);
1164 lynx_pcs_destroy(pcs);
1165 }
1166
1167 /* mdiobus_unregister and mdiobus_free handled by devres */
1168 }
1169
1170 static const struct felix_info seville_info_vsc9953 = {
1171 .target_io_res = vsc9953_target_io_res,
1172 .port_io_res = vsc9953_port_io_res,
1173 .regfields = vsc9953_regfields,
1174 .map = vsc9953_regmap,
1175 .ops = &vsc9953_ops,
1176 .stats_layout = vsc9953_stats_layout,
1177 .num_stats = ARRAY_SIZE(vsc9953_stats_layout),
1178 .vcap = vsc9953_vcap_props,
1179 .num_mact_rows = 2048,
1180 .num_ports = 10,
1181 .num_tx_queues = OCELOT_NUM_TC,
1182 .mdio_bus_alloc = vsc9953_mdio_bus_alloc,
1183 .mdio_bus_free = vsc9953_mdio_bus_free,
1184 .phylink_validate = vsc9953_phylink_validate,
1185 .prevalidate_phy_mode = vsc9953_prevalidate_phy_mode,
1186 };
1187
seville_probe(struct platform_device * pdev)1188 static int seville_probe(struct platform_device *pdev)
1189 {
1190 struct dsa_switch *ds;
1191 struct ocelot *ocelot;
1192 struct resource *res;
1193 struct felix *felix;
1194 int err;
1195
1196 felix = kzalloc(sizeof(struct felix), GFP_KERNEL);
1197 if (!felix) {
1198 err = -ENOMEM;
1199 dev_err(&pdev->dev, "Failed to allocate driver memory\n");
1200 goto err_alloc_felix;
1201 }
1202
1203 platform_set_drvdata(pdev, felix);
1204
1205 ocelot = &felix->ocelot;
1206 ocelot->dev = &pdev->dev;
1207 ocelot->num_flooding_pgids = 1;
1208 felix->info = &seville_info_vsc9953;
1209
1210 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1211 if (!res) {
1212 err = -EINVAL;
1213 dev_err(&pdev->dev, "Invalid resource\n");
1214 goto err_alloc_felix;
1215 }
1216 felix->switch_base = res->start;
1217
1218 ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL);
1219 if (!ds) {
1220 err = -ENOMEM;
1221 dev_err(&pdev->dev, "Failed to allocate DSA switch\n");
1222 goto err_alloc_ds;
1223 }
1224
1225 ds->dev = &pdev->dev;
1226 ds->num_ports = felix->info->num_ports;
1227 ds->ops = &felix_switch_ops;
1228 ds->priv = ocelot;
1229 felix->ds = ds;
1230 felix->tag_proto = DSA_TAG_PROTO_SEVILLE;
1231
1232 err = dsa_register_switch(ds);
1233 if (err) {
1234 dev_err(&pdev->dev, "Failed to register DSA switch: %d\n", err);
1235 goto err_register_ds;
1236 }
1237
1238 return 0;
1239
1240 err_register_ds:
1241 kfree(ds);
1242 err_alloc_ds:
1243 err_alloc_felix:
1244 kfree(felix);
1245 return err;
1246 }
1247
seville_remove(struct platform_device * pdev)1248 static int seville_remove(struct platform_device *pdev)
1249 {
1250 struct felix *felix = platform_get_drvdata(pdev);
1251
1252 if (!felix)
1253 return 0;
1254
1255 dsa_unregister_switch(felix->ds);
1256
1257 kfree(felix->ds);
1258 kfree(felix);
1259
1260 platform_set_drvdata(pdev, NULL);
1261
1262 return 0;
1263 }
1264
seville_shutdown(struct platform_device * pdev)1265 static void seville_shutdown(struct platform_device *pdev)
1266 {
1267 struct felix *felix = platform_get_drvdata(pdev);
1268
1269 if (!felix)
1270 return;
1271
1272 dsa_switch_shutdown(felix->ds);
1273
1274 platform_set_drvdata(pdev, NULL);
1275 }
1276
1277 static const struct of_device_id seville_of_match[] = {
1278 { .compatible = "mscc,vsc9953-switch" },
1279 { },
1280 };
1281 MODULE_DEVICE_TABLE(of, seville_of_match);
1282
1283 static struct platform_driver seville_vsc9953_driver = {
1284 .probe = seville_probe,
1285 .remove = seville_remove,
1286 .shutdown = seville_shutdown,
1287 .driver = {
1288 .name = "mscc_seville",
1289 .of_match_table = of_match_ptr(seville_of_match),
1290 },
1291 };
1292 module_platform_driver(seville_vsc9953_driver);
1293
1294 MODULE_DESCRIPTION("Seville Switch driver");
1295 MODULE_LICENSE("GPL v2");
1296