1 /*
2 * QorIQ 10G MDIO Controller
3 *
4 * Copyright 2012 Freescale Semiconductor, Inc.
5 * Copyright 2021 NXP
6 *
7 * Authors: Andy Fleming <afleming@freescale.com>
8 * Timur Tabi <timur@freescale.com>
9 *
10 * This file is licensed under the terms of the GNU General Public License
11 * version 2. This program is licensed "as is" without any warranty of any
12 * kind, whether express or implied.
13 */
14
15 #include <linux/acpi.h>
16 #include <linux/acpi_mdio.h>
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/mdio.h>
20 #include <linux/module.h>
21 #include <linux/of_address.h>
22 #include <linux/of_mdio.h>
23 #include <linux/of_platform.h>
24 #include <linux/phy.h>
25 #include <linux/slab.h>
26
27 /* Number of microseconds to wait for a register to respond */
28 #define TIMEOUT 1000
29
30 struct tgec_mdio_controller {
31 __be32 reserved[12];
32 __be32 mdio_stat; /* MDIO configuration and status */
33 __be32 mdio_ctl; /* MDIO control */
34 __be32 mdio_data; /* MDIO data */
35 __be32 mdio_addr; /* MDIO address */
36 } __packed;
37
38 #define MDIO_STAT_ENC BIT(6)
39 #define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8)
40 #define MDIO_STAT_BSY BIT(0)
41 #define MDIO_STAT_RD_ER BIT(1)
42 #define MDIO_CTL_DEV_ADDR(x) (x & 0x1f)
43 #define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5)
44 #define MDIO_CTL_PRE_DIS BIT(10)
45 #define MDIO_CTL_SCAN_EN BIT(11)
46 #define MDIO_CTL_POST_INC BIT(14)
47 #define MDIO_CTL_READ BIT(15)
48
49 #define MDIO_DATA(x) (x & 0xffff)
50 #define MDIO_DATA_BSY BIT(31)
51
52 struct mdio_fsl_priv {
53 struct tgec_mdio_controller __iomem *mdio_base;
54 bool is_little_endian;
55 bool has_a009885;
56 bool has_a011043;
57 };
58
xgmac_read32(void __iomem * regs,bool is_little_endian)59 static u32 xgmac_read32(void __iomem *regs,
60 bool is_little_endian)
61 {
62 if (is_little_endian)
63 return ioread32(regs);
64 else
65 return ioread32be(regs);
66 }
67
xgmac_write32(u32 value,void __iomem * regs,bool is_little_endian)68 static void xgmac_write32(u32 value,
69 void __iomem *regs,
70 bool is_little_endian)
71 {
72 if (is_little_endian)
73 iowrite32(value, regs);
74 else
75 iowrite32be(value, regs);
76 }
77
78 /*
79 * Wait until the MDIO bus is free
80 */
xgmac_wait_until_free(struct device * dev,struct tgec_mdio_controller __iomem * regs,bool is_little_endian)81 static int xgmac_wait_until_free(struct device *dev,
82 struct tgec_mdio_controller __iomem *regs,
83 bool is_little_endian)
84 {
85 unsigned int timeout;
86
87 /* Wait till the bus is free */
88 timeout = TIMEOUT;
89 while ((xgmac_read32(®s->mdio_stat, is_little_endian) &
90 MDIO_STAT_BSY) && timeout) {
91 cpu_relax();
92 timeout--;
93 }
94
95 if (!timeout) {
96 dev_err(dev, "timeout waiting for bus to be free\n");
97 return -ETIMEDOUT;
98 }
99
100 return 0;
101 }
102
103 /*
104 * Wait till the MDIO read or write operation is complete
105 */
xgmac_wait_until_done(struct device * dev,struct tgec_mdio_controller __iomem * regs,bool is_little_endian)106 static int xgmac_wait_until_done(struct device *dev,
107 struct tgec_mdio_controller __iomem *regs,
108 bool is_little_endian)
109 {
110 unsigned int timeout;
111
112 /* Wait till the MDIO write is complete */
113 timeout = TIMEOUT;
114 while ((xgmac_read32(®s->mdio_stat, is_little_endian) &
115 MDIO_STAT_BSY) && timeout) {
116 cpu_relax();
117 timeout--;
118 }
119
120 if (!timeout) {
121 dev_err(dev, "timeout waiting for operation to complete\n");
122 return -ETIMEDOUT;
123 }
124
125 return 0;
126 }
127
128 /*
129 * Write value to the PHY for this device to the register at regnum,waiting
130 * until the write is done before it returns. All PHY configuration has to be
131 * done through the TSEC1 MIIM regs.
132 */
xgmac_mdio_write(struct mii_bus * bus,int phy_id,int regnum,u16 value)133 static int xgmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value)
134 {
135 struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
136 struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
137 uint16_t dev_addr;
138 u32 mdio_ctl, mdio_stat;
139 int ret;
140 bool endian = priv->is_little_endian;
141
142 mdio_stat = xgmac_read32(®s->mdio_stat, endian);
143 if (regnum & MII_ADDR_C45) {
144 /* Clause 45 (ie 10G) */
145 dev_addr = (regnum >> 16) & 0x1f;
146 mdio_stat |= MDIO_STAT_ENC;
147 } else {
148 /* Clause 22 (ie 1G) */
149 dev_addr = regnum & 0x1f;
150 mdio_stat &= ~MDIO_STAT_ENC;
151 }
152
153 xgmac_write32(mdio_stat, ®s->mdio_stat, endian);
154
155 ret = xgmac_wait_until_free(&bus->dev, regs, endian);
156 if (ret)
157 return ret;
158
159 /* Set the port and dev addr */
160 mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
161 xgmac_write32(mdio_ctl, ®s->mdio_ctl, endian);
162
163 /* Set the register address */
164 if (regnum & MII_ADDR_C45) {
165 xgmac_write32(regnum & 0xffff, ®s->mdio_addr, endian);
166
167 ret = xgmac_wait_until_free(&bus->dev, regs, endian);
168 if (ret)
169 return ret;
170 }
171
172 /* Write the value to the register */
173 xgmac_write32(MDIO_DATA(value), ®s->mdio_data, endian);
174
175 ret = xgmac_wait_until_done(&bus->dev, regs, endian);
176 if (ret)
177 return ret;
178
179 return 0;
180 }
181
182 /*
183 * Reads from register regnum in the PHY for device dev, returning the value.
184 * Clears miimcom first. All PHY configuration has to be done through the
185 * TSEC1 MIIM regs.
186 */
xgmac_mdio_read(struct mii_bus * bus,int phy_id,int regnum)187 static int xgmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
188 {
189 struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
190 struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
191 unsigned long flags;
192 uint16_t dev_addr;
193 uint32_t mdio_stat;
194 uint32_t mdio_ctl;
195 int ret;
196 bool endian = priv->is_little_endian;
197
198 mdio_stat = xgmac_read32(®s->mdio_stat, endian);
199 if (regnum & MII_ADDR_C45) {
200 dev_addr = (regnum >> 16) & 0x1f;
201 mdio_stat |= MDIO_STAT_ENC;
202 } else {
203 dev_addr = regnum & 0x1f;
204 mdio_stat &= ~MDIO_STAT_ENC;
205 }
206
207 xgmac_write32(mdio_stat, ®s->mdio_stat, endian);
208
209 ret = xgmac_wait_until_free(&bus->dev, regs, endian);
210 if (ret)
211 return ret;
212
213 /* Set the Port and Device Addrs */
214 mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
215 xgmac_write32(mdio_ctl, ®s->mdio_ctl, endian);
216
217 /* Set the register address */
218 if (regnum & MII_ADDR_C45) {
219 xgmac_write32(regnum & 0xffff, ®s->mdio_addr, endian);
220
221 ret = xgmac_wait_until_free(&bus->dev, regs, endian);
222 if (ret)
223 return ret;
224 }
225
226 if (priv->has_a009885)
227 /* Once the operation completes, i.e. MDIO_STAT_BSY clears, we
228 * must read back the data register within 16 MDC cycles.
229 */
230 local_irq_save(flags);
231
232 /* Initiate the read */
233 xgmac_write32(mdio_ctl | MDIO_CTL_READ, ®s->mdio_ctl, endian);
234
235 ret = xgmac_wait_until_done(&bus->dev, regs, endian);
236 if (ret)
237 goto irq_restore;
238
239 /* Return all Fs if nothing was there */
240 if ((xgmac_read32(®s->mdio_stat, endian) & MDIO_STAT_RD_ER) &&
241 !priv->has_a011043) {
242 dev_dbg(&bus->dev,
243 "Error while reading PHY%d reg at %d.%hhu\n",
244 phy_id, dev_addr, regnum);
245 ret = 0xffff;
246 } else {
247 ret = xgmac_read32(®s->mdio_data, endian) & 0xffff;
248 dev_dbg(&bus->dev, "read %04x\n", ret);
249 }
250
251 irq_restore:
252 if (priv->has_a009885)
253 local_irq_restore(flags);
254
255 return ret;
256 }
257
xgmac_mdio_probe(struct platform_device * pdev)258 static int xgmac_mdio_probe(struct platform_device *pdev)
259 {
260 struct fwnode_handle *fwnode;
261 struct mdio_fsl_priv *priv;
262 struct resource *res;
263 struct mii_bus *bus;
264 int ret;
265
266 /* In DPAA-1, MDIO is one of the many FMan sub-devices. The FMan
267 * defines a register space that spans a large area, covering all the
268 * subdevice areas. Therefore, MDIO cannot claim exclusive access to
269 * this register area.
270 */
271 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
272 if (!res) {
273 dev_err(&pdev->dev, "could not obtain address\n");
274 return -EINVAL;
275 }
276
277 bus = mdiobus_alloc_size(sizeof(struct mdio_fsl_priv));
278 if (!bus)
279 return -ENOMEM;
280
281 bus->name = "Freescale XGMAC MDIO Bus";
282 bus->read = xgmac_mdio_read;
283 bus->write = xgmac_mdio_write;
284 bus->parent = &pdev->dev;
285 bus->probe_capabilities = MDIOBUS_C22_C45;
286 snprintf(bus->id, MII_BUS_ID_SIZE, "%pa", &res->start);
287
288 /* Set the PHY base address */
289 priv = bus->priv;
290 priv->mdio_base = ioremap(res->start, resource_size(res));
291 if (!priv->mdio_base) {
292 ret = -ENOMEM;
293 goto err_ioremap;
294 }
295
296 /* For both ACPI and DT cases, endianness of MDIO controller
297 * needs to be specified using "little-endian" property.
298 */
299 priv->is_little_endian = device_property_read_bool(&pdev->dev,
300 "little-endian");
301
302 priv->has_a009885 = device_property_read_bool(&pdev->dev,
303 "fsl,erratum-a009885");
304 priv->has_a011043 = device_property_read_bool(&pdev->dev,
305 "fsl,erratum-a011043");
306
307 fwnode = pdev->dev.fwnode;
308 if (is_of_node(fwnode))
309 ret = of_mdiobus_register(bus, to_of_node(fwnode));
310 else if (is_acpi_node(fwnode))
311 ret = acpi_mdiobus_register(bus, fwnode);
312 else
313 ret = -EINVAL;
314 if (ret) {
315 dev_err(&pdev->dev, "cannot register MDIO bus\n");
316 goto err_registration;
317 }
318
319 platform_set_drvdata(pdev, bus);
320
321 return 0;
322
323 err_registration:
324 iounmap(priv->mdio_base);
325
326 err_ioremap:
327 mdiobus_free(bus);
328
329 return ret;
330 }
331
xgmac_mdio_remove(struct platform_device * pdev)332 static int xgmac_mdio_remove(struct platform_device *pdev)
333 {
334 struct mii_bus *bus = platform_get_drvdata(pdev);
335 struct mdio_fsl_priv *priv = bus->priv;
336
337 mdiobus_unregister(bus);
338 iounmap(priv->mdio_base);
339 mdiobus_free(bus);
340
341 return 0;
342 }
343
344 static const struct of_device_id xgmac_mdio_match[] = {
345 {
346 .compatible = "fsl,fman-xmdio",
347 },
348 {
349 .compatible = "fsl,fman-memac-mdio",
350 },
351 {},
352 };
353 MODULE_DEVICE_TABLE(of, xgmac_mdio_match);
354
355 static const struct acpi_device_id xgmac_acpi_match[] = {
356 { "NXP0006" },
357 { }
358 };
359 MODULE_DEVICE_TABLE(acpi, xgmac_acpi_match);
360
361 static struct platform_driver xgmac_mdio_driver = {
362 .driver = {
363 .name = "fsl-fman_xmdio",
364 .of_match_table = xgmac_mdio_match,
365 .acpi_match_table = xgmac_acpi_match,
366 },
367 .probe = xgmac_mdio_probe,
368 .remove = xgmac_mdio_remove,
369 };
370
371 module_platform_driver(xgmac_mdio_driver);
372
373 MODULE_DESCRIPTION("Freescale QorIQ 10G MDIO Controller");
374 MODULE_LICENSE("GPL v2");
375