1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * dim2.c - MediaLB DIM2 Hardware Dependent Module
4 *
5 * Copyright (C) 2015-2016, Microchip Technology Germany II GmbH & Co. KG
6 */
7
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10 #include <linux/module.h>
11 #include <linux/of_platform.h>
12 #include <linux/printk.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/interrupt.h>
17 #include <linux/slab.h>
18 #include <linux/io.h>
19 #include <linux/clk.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/sched.h>
22 #include <linux/kthread.h>
23 #include <linux/most.h>
24 #include "hal.h"
25 #include "errors.h"
26 #include "sysfs.h"
27
28 #define DMA_CHANNELS (32 - 1) /* channel 0 is a system channel */
29
30 #define MAX_BUFFERS_PACKET 32
31 #define MAX_BUFFERS_STREAMING 32
32 #define MAX_BUF_SIZE_PACKET 2048
33 #define MAX_BUF_SIZE_STREAMING (8 * 1024)
34
35 /*
36 * The parameter representing the number of frames per sub-buffer for
37 * synchronous channels. Valid values: [0 .. 6].
38 *
39 * The values 0, 1, 2, 3, 4, 5, 6 represent corresponding number of frames per
40 * sub-buffer 1, 2, 4, 8, 16, 32, 64.
41 */
42 static u8 fcnt = 4; /* (1 << fcnt) frames per subbuffer */
43 module_param(fcnt, byte, 0000);
44 MODULE_PARM_DESC(fcnt, "Num of frames per sub-buffer for sync channels as a power of 2");
45
46 static DEFINE_SPINLOCK(dim_lock);
47
48 static void dim2_tasklet_fn(unsigned long data);
49 static DECLARE_TASKLET_OLD(dim2_tasklet, dim2_tasklet_fn);
50
51 /**
52 * struct hdm_channel - private structure to keep channel specific data
53 * @name: channel name
54 * @is_initialized: identifier to know whether the channel is initialized
55 * @ch: HAL specific channel data
56 * @reset_dbr_size: reset DBR data buffer size
57 * @pending_list: list to keep MBO's before starting transfer
58 * @started_list: list to keep MBO's after starting transfer
59 * @direction: channel direction (TX or RX)
60 * @data_type: channel data type
61 */
62 struct hdm_channel {
63 char name[sizeof "caNNN"];
64 bool is_initialized;
65 struct dim_channel ch;
66 u16 *reset_dbr_size;
67 struct list_head pending_list; /* before dim_enqueue_buffer() */
68 struct list_head started_list; /* after dim_enqueue_buffer() */
69 enum most_channel_direction direction;
70 enum most_channel_data_type data_type;
71 };
72
73 /*
74 * struct dim2_hdm - private structure to keep interface specific data
75 * @hch: an array of channel specific data
76 * @most_iface: most interface structure
77 * @capabilities: an array of channel capability data
78 * @io_base: I/O register base address
79 * @netinfo_task: thread to deliver network status
80 * @netinfo_waitq: waitq for the thread to sleep
81 * @deliver_netinfo: to identify whether network status received
82 * @mac_addrs: INIC mac address
83 * @link_state: network link state
84 * @atx_idx: index of async tx channel
85 */
86 struct dim2_hdm {
87 struct device dev;
88 struct hdm_channel hch[DMA_CHANNELS];
89 struct most_channel_capability capabilities[DMA_CHANNELS];
90 struct most_interface most_iface;
91 char name[16 + sizeof "dim2-"];
92 void __iomem *io_base;
93 u8 clk_speed;
94 struct clk *clk;
95 struct clk *clk_pll;
96 struct task_struct *netinfo_task;
97 wait_queue_head_t netinfo_waitq;
98 int deliver_netinfo;
99 unsigned char mac_addrs[6];
100 unsigned char link_state;
101 int atx_idx;
102 struct medialb_bus bus;
103 void (*on_netinfo)(struct most_interface *most_iface,
104 unsigned char link_state, unsigned char *addrs);
105 void (*disable_platform)(struct platform_device *pdev);
106 };
107
108 struct dim2_platform_data {
109 int (*enable)(struct platform_device *pdev);
110 void (*disable)(struct platform_device *pdev);
111 };
112
113 #define iface_to_hdm(iface) container_of(iface, struct dim2_hdm, most_iface)
114
115 /* Macro to identify a network status message */
116 #define PACKET_IS_NET_INFO(p) \
117 (((p)[1] == 0x18) && ((p)[2] == 0x05) && ((p)[3] == 0x0C) && \
118 ((p)[13] == 0x3C) && ((p)[14] == 0x00) && ((p)[15] == 0x0A))
119
state_show(struct device * dev,struct device_attribute * attr,char * buf)120 static ssize_t state_show(struct device *dev, struct device_attribute *attr,
121 char *buf)
122 {
123 bool state;
124 unsigned long flags;
125
126 spin_lock_irqsave(&dim_lock, flags);
127 state = dim_get_lock_state();
128 spin_unlock_irqrestore(&dim_lock, flags);
129
130 return sysfs_emit(buf, "%s\n", state ? "locked" : "");
131 }
132
133 static DEVICE_ATTR_RO(state);
134
135 static struct attribute *dim2_attrs[] = {
136 &dev_attr_state.attr,
137 NULL,
138 };
139
140 ATTRIBUTE_GROUPS(dim2);
141
142 /**
143 * dimcb_on_error - callback from HAL to report miscommunication between
144 * HDM and HAL
145 * @error_id: Error ID
146 * @error_message: Error message. Some text in a free format
147 */
dimcb_on_error(u8 error_id,const char * error_message)148 void dimcb_on_error(u8 error_id, const char *error_message)
149 {
150 pr_err("%s: error_id - %d, error_message - %s\n", __func__, error_id,
151 error_message);
152 }
153
154 /**
155 * try_start_dim_transfer - try to transfer a buffer on a channel
156 * @hdm_ch: channel specific data
157 *
158 * Transfer a buffer from pending_list if the channel is ready
159 */
try_start_dim_transfer(struct hdm_channel * hdm_ch)160 static int try_start_dim_transfer(struct hdm_channel *hdm_ch)
161 {
162 u16 buf_size;
163 struct list_head *head = &hdm_ch->pending_list;
164 struct mbo *mbo;
165 unsigned long flags;
166 struct dim_ch_state_t st;
167
168 BUG_ON(!hdm_ch);
169 BUG_ON(!hdm_ch->is_initialized);
170
171 spin_lock_irqsave(&dim_lock, flags);
172 if (list_empty(head)) {
173 spin_unlock_irqrestore(&dim_lock, flags);
174 return -EAGAIN;
175 }
176
177 if (!dim_get_channel_state(&hdm_ch->ch, &st)->ready) {
178 spin_unlock_irqrestore(&dim_lock, flags);
179 return -EAGAIN;
180 }
181
182 mbo = list_first_entry(head, struct mbo, list);
183 buf_size = mbo->buffer_length;
184
185 if (dim_dbr_space(&hdm_ch->ch) < buf_size) {
186 spin_unlock_irqrestore(&dim_lock, flags);
187 return -EAGAIN;
188 }
189
190 BUG_ON(mbo->bus_address == 0);
191 if (!dim_enqueue_buffer(&hdm_ch->ch, mbo->bus_address, buf_size)) {
192 list_del(head->next);
193 spin_unlock_irqrestore(&dim_lock, flags);
194 mbo->processed_length = 0;
195 mbo->status = MBO_E_INVAL;
196 mbo->complete(mbo);
197 return -EFAULT;
198 }
199
200 list_move_tail(head->next, &hdm_ch->started_list);
201 spin_unlock_irqrestore(&dim_lock, flags);
202
203 return 0;
204 }
205
206 /**
207 * deliver_netinfo_thread - thread to deliver network status to mostcore
208 * @data: private data
209 *
210 * Wait for network status and deliver it to mostcore once it is received
211 */
deliver_netinfo_thread(void * data)212 static int deliver_netinfo_thread(void *data)
213 {
214 struct dim2_hdm *dev = data;
215
216 while (!kthread_should_stop()) {
217 wait_event_interruptible(dev->netinfo_waitq,
218 dev->deliver_netinfo ||
219 kthread_should_stop());
220
221 if (dev->deliver_netinfo) {
222 dev->deliver_netinfo--;
223 if (dev->on_netinfo) {
224 dev->on_netinfo(&dev->most_iface,
225 dev->link_state,
226 dev->mac_addrs);
227 }
228 }
229 }
230
231 return 0;
232 }
233
234 /**
235 * retrieve_netinfo - retrieve network status from received buffer
236 * @dev: private data
237 * @mbo: received MBO
238 *
239 * Parse the message in buffer and get node address, link state, MAC address.
240 * Wake up a thread to deliver this status to mostcore
241 */
retrieve_netinfo(struct dim2_hdm * dev,struct mbo * mbo)242 static void retrieve_netinfo(struct dim2_hdm *dev, struct mbo *mbo)
243 {
244 u8 *data = mbo->virt_address;
245
246 pr_info("Node Address: 0x%03x\n", (u16)data[16] << 8 | data[17]);
247 dev->link_state = data[18];
248 pr_info("NIState: %d\n", dev->link_state);
249 memcpy(dev->mac_addrs, data + 19, 6);
250 dev->deliver_netinfo++;
251 wake_up_interruptible(&dev->netinfo_waitq);
252 }
253
254 /**
255 * service_done_flag - handle completed buffers
256 * @dev: private data
257 * @ch_idx: channel index
258 *
259 * Return back the completed buffers to mostcore, using completion callback
260 */
service_done_flag(struct dim2_hdm * dev,int ch_idx)261 static void service_done_flag(struct dim2_hdm *dev, int ch_idx)
262 {
263 struct hdm_channel *hdm_ch = dev->hch + ch_idx;
264 struct dim_ch_state_t st;
265 struct list_head *head;
266 struct mbo *mbo;
267 int done_buffers;
268 unsigned long flags;
269 u8 *data;
270
271 BUG_ON(!hdm_ch);
272 BUG_ON(!hdm_ch->is_initialized);
273
274 spin_lock_irqsave(&dim_lock, flags);
275
276 done_buffers = dim_get_channel_state(&hdm_ch->ch, &st)->done_buffers;
277 if (!done_buffers) {
278 spin_unlock_irqrestore(&dim_lock, flags);
279 return;
280 }
281
282 if (!dim_detach_buffers(&hdm_ch->ch, done_buffers)) {
283 spin_unlock_irqrestore(&dim_lock, flags);
284 return;
285 }
286 spin_unlock_irqrestore(&dim_lock, flags);
287
288 head = &hdm_ch->started_list;
289
290 while (done_buffers) {
291 spin_lock_irqsave(&dim_lock, flags);
292 if (list_empty(head)) {
293 spin_unlock_irqrestore(&dim_lock, flags);
294 pr_crit("hard error: started_mbo list is empty whereas DIM2 has sent buffers\n");
295 break;
296 }
297
298 mbo = list_first_entry(head, struct mbo, list);
299 list_del(head->next);
300 spin_unlock_irqrestore(&dim_lock, flags);
301
302 data = mbo->virt_address;
303
304 if (hdm_ch->data_type == MOST_CH_ASYNC &&
305 hdm_ch->direction == MOST_CH_RX &&
306 PACKET_IS_NET_INFO(data)) {
307 retrieve_netinfo(dev, mbo);
308
309 spin_lock_irqsave(&dim_lock, flags);
310 list_add_tail(&mbo->list, &hdm_ch->pending_list);
311 spin_unlock_irqrestore(&dim_lock, flags);
312 } else {
313 if (hdm_ch->data_type == MOST_CH_CONTROL ||
314 hdm_ch->data_type == MOST_CH_ASYNC) {
315 u32 const data_size =
316 (u32)data[0] * 256 + data[1] + 2;
317
318 mbo->processed_length =
319 min_t(u32, data_size,
320 mbo->buffer_length);
321 } else {
322 mbo->processed_length = mbo->buffer_length;
323 }
324 mbo->status = MBO_SUCCESS;
325 mbo->complete(mbo);
326 }
327
328 done_buffers--;
329 }
330 }
331
get_active_channels(struct dim2_hdm * dev,struct dim_channel ** buffer)332 static struct dim_channel **get_active_channels(struct dim2_hdm *dev,
333 struct dim_channel **buffer)
334 {
335 int idx = 0;
336 int ch_idx;
337
338 for (ch_idx = 0; ch_idx < DMA_CHANNELS; ch_idx++) {
339 if (dev->hch[ch_idx].is_initialized)
340 buffer[idx++] = &dev->hch[ch_idx].ch;
341 }
342 buffer[idx++] = NULL;
343
344 return buffer;
345 }
346
dim2_mlb_isr(int irq,void * _dev)347 static irqreturn_t dim2_mlb_isr(int irq, void *_dev)
348 {
349 struct dim2_hdm *dev = _dev;
350 unsigned long flags;
351
352 spin_lock_irqsave(&dim_lock, flags);
353 dim_service_mlb_int_irq();
354 spin_unlock_irqrestore(&dim_lock, flags);
355
356 if (dev->atx_idx >= 0 && dev->hch[dev->atx_idx].is_initialized)
357 while (!try_start_dim_transfer(dev->hch + dev->atx_idx))
358 continue;
359
360 return IRQ_HANDLED;
361 }
362
363 /**
364 * dim2_tasklet_fn - tasklet function
365 * @data: private data
366 *
367 * Service each initialized channel, if needed
368 */
dim2_tasklet_fn(unsigned long data)369 static void dim2_tasklet_fn(unsigned long data)
370 {
371 struct dim2_hdm *dev = (struct dim2_hdm *)data;
372 unsigned long flags;
373 int ch_idx;
374
375 for (ch_idx = 0; ch_idx < DMA_CHANNELS; ch_idx++) {
376 if (!dev->hch[ch_idx].is_initialized)
377 continue;
378
379 spin_lock_irqsave(&dim_lock, flags);
380 dim_service_channel(&dev->hch[ch_idx].ch);
381 spin_unlock_irqrestore(&dim_lock, flags);
382
383 service_done_flag(dev, ch_idx);
384 while (!try_start_dim_transfer(dev->hch + ch_idx))
385 continue;
386 }
387 }
388
389 /**
390 * dim2_ahb_isr - interrupt service routine
391 * @irq: irq number
392 * @_dev: private data
393 *
394 * Acknowledge the interrupt and schedule a tasklet to service channels.
395 * Return IRQ_HANDLED.
396 */
dim2_ahb_isr(int irq,void * _dev)397 static irqreturn_t dim2_ahb_isr(int irq, void *_dev)
398 {
399 struct dim2_hdm *dev = _dev;
400 struct dim_channel *buffer[DMA_CHANNELS + 1];
401 unsigned long flags;
402
403 spin_lock_irqsave(&dim_lock, flags);
404 dim_service_ahb_int_irq(get_active_channels(dev, buffer));
405 spin_unlock_irqrestore(&dim_lock, flags);
406
407 dim2_tasklet.data = (unsigned long)dev;
408 tasklet_schedule(&dim2_tasklet);
409 return IRQ_HANDLED;
410 }
411
412 /**
413 * complete_all_mbos - complete MBO's in a list
414 * @head: list head
415 *
416 * Delete all the entries in list and return back MBO's to mostcore using
417 * completion call back.
418 */
complete_all_mbos(struct list_head * head)419 static void complete_all_mbos(struct list_head *head)
420 {
421 unsigned long flags;
422 struct mbo *mbo;
423
424 for (;;) {
425 spin_lock_irqsave(&dim_lock, flags);
426 if (list_empty(head)) {
427 spin_unlock_irqrestore(&dim_lock, flags);
428 break;
429 }
430
431 mbo = list_first_entry(head, struct mbo, list);
432 list_del(head->next);
433 spin_unlock_irqrestore(&dim_lock, flags);
434
435 mbo->processed_length = 0;
436 mbo->status = MBO_E_CLOSE;
437 mbo->complete(mbo);
438 }
439 }
440
441 /**
442 * configure_channel - initialize a channel
443 * @most_iface: interface the channel belongs to
444 * @ch_idx: channel index to be configured
445 * @ccfg: structure that holds the configuration information
446 *
447 * Receives configuration information from mostcore and initialize
448 * the corresponding channel. Return 0 on success, negative on failure.
449 */
configure_channel(struct most_interface * most_iface,int ch_idx,struct most_channel_config * ccfg)450 static int configure_channel(struct most_interface *most_iface, int ch_idx,
451 struct most_channel_config *ccfg)
452 {
453 struct dim2_hdm *dev = iface_to_hdm(most_iface);
454 bool const is_tx = ccfg->direction == MOST_CH_TX;
455 u16 const sub_size = ccfg->subbuffer_size;
456 u16 const buf_size = ccfg->buffer_size;
457 u16 new_size;
458 unsigned long flags;
459 u8 hal_ret;
460 int const ch_addr = ch_idx * 2 + 2;
461 struct hdm_channel *const hdm_ch = dev->hch + ch_idx;
462
463 BUG_ON(ch_idx < 0 || ch_idx >= DMA_CHANNELS);
464
465 if (hdm_ch->is_initialized)
466 return -EPERM;
467
468 /* do not reset if the property was set by user, see poison_channel */
469 hdm_ch->reset_dbr_size = ccfg->dbr_size ? NULL : &ccfg->dbr_size;
470
471 /* zero value is default dbr_size, see dim2 hal */
472 hdm_ch->ch.dbr_size = ccfg->dbr_size;
473
474 switch (ccfg->data_type) {
475 case MOST_CH_CONTROL:
476 new_size = dim_norm_ctrl_async_buffer_size(buf_size);
477 if (new_size == 0) {
478 pr_err("%s: too small buffer size\n", hdm_ch->name);
479 return -EINVAL;
480 }
481 ccfg->buffer_size = new_size;
482 if (new_size != buf_size)
483 pr_warn("%s: fixed buffer size (%d -> %d)\n",
484 hdm_ch->name, buf_size, new_size);
485 spin_lock_irqsave(&dim_lock, flags);
486 hal_ret = dim_init_control(&hdm_ch->ch, is_tx, ch_addr,
487 is_tx ? new_size * 2 : new_size);
488 break;
489 case MOST_CH_ASYNC:
490 new_size = dim_norm_ctrl_async_buffer_size(buf_size);
491 if (new_size == 0) {
492 pr_err("%s: too small buffer size\n", hdm_ch->name);
493 return -EINVAL;
494 }
495 ccfg->buffer_size = new_size;
496 if (new_size != buf_size)
497 pr_warn("%s: fixed buffer size (%d -> %d)\n",
498 hdm_ch->name, buf_size, new_size);
499 spin_lock_irqsave(&dim_lock, flags);
500 hal_ret = dim_init_async(&hdm_ch->ch, is_tx, ch_addr,
501 is_tx ? new_size * 2 : new_size);
502 break;
503 case MOST_CH_ISOC:
504 new_size = dim_norm_isoc_buffer_size(buf_size, sub_size);
505 if (new_size == 0) {
506 pr_err("%s: invalid sub-buffer size or too small buffer size\n",
507 hdm_ch->name);
508 return -EINVAL;
509 }
510 ccfg->buffer_size = new_size;
511 if (new_size != buf_size)
512 pr_warn("%s: fixed buffer size (%d -> %d)\n",
513 hdm_ch->name, buf_size, new_size);
514 spin_lock_irqsave(&dim_lock, flags);
515 hal_ret = dim_init_isoc(&hdm_ch->ch, is_tx, ch_addr, sub_size);
516 break;
517 case MOST_CH_SYNC:
518 new_size = dim_norm_sync_buffer_size(buf_size, sub_size);
519 if (new_size == 0) {
520 pr_err("%s: invalid sub-buffer size or too small buffer size\n",
521 hdm_ch->name);
522 return -EINVAL;
523 }
524 ccfg->buffer_size = new_size;
525 if (new_size != buf_size)
526 pr_warn("%s: fixed buffer size (%d -> %d)\n",
527 hdm_ch->name, buf_size, new_size);
528 spin_lock_irqsave(&dim_lock, flags);
529 hal_ret = dim_init_sync(&hdm_ch->ch, is_tx, ch_addr, sub_size);
530 break;
531 default:
532 pr_err("%s: configure failed, bad channel type: %d\n",
533 hdm_ch->name, ccfg->data_type);
534 return -EINVAL;
535 }
536
537 if (hal_ret != DIM_NO_ERROR) {
538 spin_unlock_irqrestore(&dim_lock, flags);
539 pr_err("%s: configure failed (%d), type: %d, is_tx: %d\n",
540 hdm_ch->name, hal_ret, ccfg->data_type, (int)is_tx);
541 return -ENODEV;
542 }
543
544 hdm_ch->data_type = ccfg->data_type;
545 hdm_ch->direction = ccfg->direction;
546 hdm_ch->is_initialized = true;
547
548 if (hdm_ch->data_type == MOST_CH_ASYNC &&
549 hdm_ch->direction == MOST_CH_TX &&
550 dev->atx_idx < 0)
551 dev->atx_idx = ch_idx;
552
553 spin_unlock_irqrestore(&dim_lock, flags);
554 ccfg->dbr_size = hdm_ch->ch.dbr_size;
555
556 return 0;
557 }
558
559 /**
560 * enqueue - enqueue a buffer for data transfer
561 * @most_iface: intended interface
562 * @ch_idx: ID of the channel the buffer is intended for
563 * @mbo: pointer to the buffer object
564 *
565 * Push the buffer into pending_list and try to transfer one buffer from
566 * pending_list. Return 0 on success, negative on failure.
567 */
enqueue(struct most_interface * most_iface,int ch_idx,struct mbo * mbo)568 static int enqueue(struct most_interface *most_iface, int ch_idx,
569 struct mbo *mbo)
570 {
571 struct dim2_hdm *dev = iface_to_hdm(most_iface);
572 struct hdm_channel *hdm_ch = dev->hch + ch_idx;
573 unsigned long flags;
574
575 BUG_ON(ch_idx < 0 || ch_idx >= DMA_CHANNELS);
576
577 if (!hdm_ch->is_initialized)
578 return -EPERM;
579
580 if (mbo->bus_address == 0)
581 return -EFAULT;
582
583 spin_lock_irqsave(&dim_lock, flags);
584 list_add_tail(&mbo->list, &hdm_ch->pending_list);
585 spin_unlock_irqrestore(&dim_lock, flags);
586
587 (void)try_start_dim_transfer(hdm_ch);
588
589 return 0;
590 }
591
592 /**
593 * request_netinfo - triggers retrieving of network info
594 * @most_iface: pointer to the interface
595 * @ch_idx: corresponding channel ID
596 * @on_netinfo: call-back used to deliver network status to mostcore
597 *
598 * Send a command to INIC which triggers retrieving of network info by means of
599 * "Message exchange over MDP/MEP". Return 0 on success, negative on failure.
600 */
request_netinfo(struct most_interface * most_iface,int ch_idx,void (* on_netinfo)(struct most_interface *,unsigned char,unsigned char *))601 static void request_netinfo(struct most_interface *most_iface, int ch_idx,
602 void (*on_netinfo)(struct most_interface *,
603 unsigned char, unsigned char *))
604 {
605 struct dim2_hdm *dev = iface_to_hdm(most_iface);
606 struct mbo *mbo;
607 u8 *data;
608
609 dev->on_netinfo = on_netinfo;
610 if (!on_netinfo)
611 return;
612
613 if (dev->atx_idx < 0) {
614 pr_err("Async Tx Not initialized\n");
615 return;
616 }
617
618 mbo = most_get_mbo(&dev->most_iface, dev->atx_idx, NULL);
619 if (!mbo)
620 return;
621
622 mbo->buffer_length = 5;
623
624 data = mbo->virt_address;
625
626 data[0] = 0x00; /* PML High byte */
627 data[1] = 0x03; /* PML Low byte */
628 data[2] = 0x02; /* PMHL */
629 data[3] = 0x08; /* FPH */
630 data[4] = 0x40; /* FMF (FIFO cmd msg - Triggers NAOverMDP) */
631
632 most_submit_mbo(mbo);
633 }
634
635 /**
636 * poison_channel - poison buffers of a channel
637 * @most_iface: pointer to the interface the channel to be poisoned belongs to
638 * @ch_idx: corresponding channel ID
639 *
640 * Destroy a channel and complete all the buffers in both started_list &
641 * pending_list. Return 0 on success, negative on failure.
642 */
poison_channel(struct most_interface * most_iface,int ch_idx)643 static int poison_channel(struct most_interface *most_iface, int ch_idx)
644 {
645 struct dim2_hdm *dev = iface_to_hdm(most_iface);
646 struct hdm_channel *hdm_ch = dev->hch + ch_idx;
647 unsigned long flags;
648 u8 hal_ret;
649 int ret = 0;
650
651 BUG_ON(ch_idx < 0 || ch_idx >= DMA_CHANNELS);
652
653 if (!hdm_ch->is_initialized)
654 return -EPERM;
655
656 tasklet_disable(&dim2_tasklet);
657 spin_lock_irqsave(&dim_lock, flags);
658 hal_ret = dim_destroy_channel(&hdm_ch->ch);
659 hdm_ch->is_initialized = false;
660 if (ch_idx == dev->atx_idx)
661 dev->atx_idx = -1;
662 spin_unlock_irqrestore(&dim_lock, flags);
663 tasklet_enable(&dim2_tasklet);
664 if (hal_ret != DIM_NO_ERROR) {
665 pr_err("HAL Failed to close channel %s\n", hdm_ch->name);
666 ret = -EFAULT;
667 }
668
669 complete_all_mbos(&hdm_ch->started_list);
670 complete_all_mbos(&hdm_ch->pending_list);
671 if (hdm_ch->reset_dbr_size)
672 *hdm_ch->reset_dbr_size = 0;
673
674 return ret;
675 }
676
dma_alloc(struct mbo * mbo,u32 size)677 static void *dma_alloc(struct mbo *mbo, u32 size)
678 {
679 struct device *dev = mbo->ifp->driver_dev;
680
681 return dma_alloc_coherent(dev, size, &mbo->bus_address, GFP_KERNEL);
682 }
683
dma_free(struct mbo * mbo,u32 size)684 static void dma_free(struct mbo *mbo, u32 size)
685 {
686 struct device *dev = mbo->ifp->driver_dev;
687
688 dma_free_coherent(dev, size, mbo->virt_address, mbo->bus_address);
689 }
690
691 static const struct of_device_id dim2_of_match[];
692
693 static struct {
694 const char *clock_speed;
695 u8 clk_speed;
696 } clk_mt[] = {
697 { "256fs", CLK_256FS },
698 { "512fs", CLK_512FS },
699 { "1024fs", CLK_1024FS },
700 { "2048fs", CLK_2048FS },
701 { "3072fs", CLK_3072FS },
702 { "4096fs", CLK_4096FS },
703 { "6144fs", CLK_6144FS },
704 { "8192fs", CLK_8192FS },
705 };
706
707 /**
708 * get_dim2_clk_speed - converts string to DIM2 clock speed value
709 *
710 * @clock_speed: string in the format "{NUMBER}fs"
711 * @val: pointer to get one of the CLK_{NUMBER}FS values
712 *
713 * By success stores one of the CLK_{NUMBER}FS in the *val and returns 0,
714 * otherwise returns -EINVAL.
715 */
get_dim2_clk_speed(const char * clock_speed,u8 * val)716 static int get_dim2_clk_speed(const char *clock_speed, u8 *val)
717 {
718 int i;
719
720 for (i = 0; i < ARRAY_SIZE(clk_mt); i++) {
721 if (!strcmp(clock_speed, clk_mt[i].clock_speed)) {
722 *val = clk_mt[i].clk_speed;
723 return 0;
724 }
725 }
726 return -EINVAL;
727 }
728
dim2_release(struct device * d)729 static void dim2_release(struct device *d)
730 {
731 struct dim2_hdm *dev = container_of(d, struct dim2_hdm, dev);
732 unsigned long flags;
733
734 kthread_stop(dev->netinfo_task);
735
736 spin_lock_irqsave(&dim_lock, flags);
737 dim_shutdown();
738 spin_unlock_irqrestore(&dim_lock, flags);
739
740 if (dev->disable_platform)
741 dev->disable_platform(to_platform_device(d->parent));
742
743 kfree(dev);
744 }
745
746 /*
747 * dim2_probe - dim2 probe handler
748 * @pdev: platform device structure
749 *
750 * Register the dim2 interface with mostcore and initialize it.
751 * Return 0 on success, negative on failure.
752 */
dim2_probe(struct platform_device * pdev)753 static int dim2_probe(struct platform_device *pdev)
754 {
755 const struct dim2_platform_data *pdata;
756 const struct of_device_id *of_id;
757 const char *clock_speed;
758 struct dim2_hdm *dev;
759 struct resource *res;
760 int ret, i;
761 u8 hal_ret;
762 int irq;
763
764 enum { MLB_INT_IDX, AHB0_INT_IDX };
765
766 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
767 if (!dev)
768 return -ENOMEM;
769
770 dev->atx_idx = -1;
771
772 platform_set_drvdata(pdev, dev);
773
774 ret = of_property_read_string(pdev->dev.of_node,
775 "microchip,clock-speed", &clock_speed);
776 if (ret) {
777 dev_err(&pdev->dev, "missing dt property clock-speed\n");
778 goto err_free_dev;
779 }
780
781 ret = get_dim2_clk_speed(clock_speed, &dev->clk_speed);
782 if (ret) {
783 dev_err(&pdev->dev, "bad dt property clock-speed\n");
784 goto err_free_dev;
785 }
786
787 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
788 dev->io_base = devm_ioremap_resource(&pdev->dev, res);
789 if (IS_ERR(dev->io_base)) {
790 ret = PTR_ERR(dev->io_base);
791 goto err_free_dev;
792 }
793
794 of_id = of_match_node(dim2_of_match, pdev->dev.of_node);
795 pdata = of_id->data;
796 ret = pdata && pdata->enable ? pdata->enable(pdev) : 0;
797 if (ret)
798 goto err_free_dev;
799
800 dev->disable_platform = pdata ? pdata->disable : NULL;
801
802 dev_info(&pdev->dev, "sync: num of frames per sub-buffer: %u\n", fcnt);
803 hal_ret = dim_startup(dev->io_base, dev->clk_speed, fcnt);
804 if (hal_ret != DIM_NO_ERROR) {
805 dev_err(&pdev->dev, "dim_startup failed: %d\n", hal_ret);
806 ret = -ENODEV;
807 goto err_disable_platform;
808 }
809
810 irq = platform_get_irq(pdev, AHB0_INT_IDX);
811 if (irq < 0) {
812 ret = irq;
813 goto err_shutdown_dim;
814 }
815
816 ret = devm_request_irq(&pdev->dev, irq, dim2_ahb_isr, 0,
817 "dim2_ahb0_int", dev);
818 if (ret) {
819 dev_err(&pdev->dev, "failed to request ahb0_int irq %d\n", irq);
820 goto err_shutdown_dim;
821 }
822
823 irq = platform_get_irq(pdev, MLB_INT_IDX);
824 if (irq < 0) {
825 ret = irq;
826 goto err_shutdown_dim;
827 }
828
829 ret = devm_request_irq(&pdev->dev, irq, dim2_mlb_isr, 0,
830 "dim2_mlb_int", dev);
831 if (ret) {
832 dev_err(&pdev->dev, "failed to request mlb_int irq %d\n", irq);
833 goto err_shutdown_dim;
834 }
835
836 init_waitqueue_head(&dev->netinfo_waitq);
837 dev->deliver_netinfo = 0;
838 dev->netinfo_task = kthread_run(&deliver_netinfo_thread, dev,
839 "dim2_netinfo");
840 if (IS_ERR(dev->netinfo_task)) {
841 ret = PTR_ERR(dev->netinfo_task);
842 goto err_shutdown_dim;
843 }
844
845 for (i = 0; i < DMA_CHANNELS; i++) {
846 struct most_channel_capability *cap = dev->capabilities + i;
847 struct hdm_channel *hdm_ch = dev->hch + i;
848
849 INIT_LIST_HEAD(&hdm_ch->pending_list);
850 INIT_LIST_HEAD(&hdm_ch->started_list);
851 hdm_ch->is_initialized = false;
852 snprintf(hdm_ch->name, sizeof(hdm_ch->name), "ca%d", i * 2 + 2);
853
854 cap->name_suffix = hdm_ch->name;
855 cap->direction = MOST_CH_RX | MOST_CH_TX;
856 cap->data_type = MOST_CH_CONTROL | MOST_CH_ASYNC |
857 MOST_CH_ISOC | MOST_CH_SYNC;
858 cap->num_buffers_packet = MAX_BUFFERS_PACKET;
859 cap->buffer_size_packet = MAX_BUF_SIZE_PACKET;
860 cap->num_buffers_streaming = MAX_BUFFERS_STREAMING;
861 cap->buffer_size_streaming = MAX_BUF_SIZE_STREAMING;
862 }
863
864 {
865 const char *fmt;
866
867 if (sizeof(res->start) == sizeof(long long))
868 fmt = "dim2-%016llx";
869 else if (sizeof(res->start) == sizeof(long))
870 fmt = "dim2-%016lx";
871 else
872 fmt = "dim2-%016x";
873
874 snprintf(dev->name, sizeof(dev->name), fmt, res->start);
875 }
876
877 dev->most_iface.interface = ITYPE_MEDIALB_DIM2;
878 dev->most_iface.description = dev->name;
879 dev->most_iface.num_channels = DMA_CHANNELS;
880 dev->most_iface.channel_vector = dev->capabilities;
881 dev->most_iface.configure = configure_channel;
882 dev->most_iface.enqueue = enqueue;
883 dev->most_iface.dma_alloc = dma_alloc;
884 dev->most_iface.dma_free = dma_free;
885 dev->most_iface.poison_channel = poison_channel;
886 dev->most_iface.request_netinfo = request_netinfo;
887 dev->most_iface.driver_dev = &pdev->dev;
888 dev->most_iface.dev = &dev->dev;
889 dev->dev.init_name = dev->name;
890 dev->dev.parent = &pdev->dev;
891 dev->dev.release = dim2_release;
892
893 return most_register_interface(&dev->most_iface);
894
895 err_shutdown_dim:
896 dim_shutdown();
897 err_disable_platform:
898 if (dev->disable_platform)
899 dev->disable_platform(pdev);
900 err_free_dev:
901 kfree(dev);
902
903 return ret;
904 }
905
906 /**
907 * dim2_remove - dim2 remove handler
908 * @pdev: platform device structure
909 *
910 * Unregister the interface from mostcore
911 */
dim2_remove(struct platform_device * pdev)912 static int dim2_remove(struct platform_device *pdev)
913 {
914 struct dim2_hdm *dev = platform_get_drvdata(pdev);
915
916 most_deregister_interface(&dev->most_iface);
917
918 return 0;
919 }
920
921 /* platform specific functions [[ */
922
fsl_mx6_enable(struct platform_device * pdev)923 static int fsl_mx6_enable(struct platform_device *pdev)
924 {
925 struct dim2_hdm *dev = platform_get_drvdata(pdev);
926 int ret;
927
928 dev->clk = devm_clk_get(&pdev->dev, "mlb");
929 if (IS_ERR_OR_NULL(dev->clk)) {
930 dev_err(&pdev->dev, "unable to get mlb clock\n");
931 return -EFAULT;
932 }
933
934 ret = clk_prepare_enable(dev->clk);
935 if (ret) {
936 dev_err(&pdev->dev, "%s\n", "clk_prepare_enable failed");
937 return ret;
938 }
939
940 if (dev->clk_speed >= CLK_2048FS) {
941 /* enable pll */
942 dev->clk_pll = devm_clk_get(&pdev->dev, "pll8_mlb");
943 if (IS_ERR_OR_NULL(dev->clk_pll)) {
944 dev_err(&pdev->dev, "unable to get mlb pll clock\n");
945 clk_disable_unprepare(dev->clk);
946 return -EFAULT;
947 }
948
949 writel(0x888, dev->io_base + 0x38);
950 clk_prepare_enable(dev->clk_pll);
951 }
952
953 return 0;
954 }
955
fsl_mx6_disable(struct platform_device * pdev)956 static void fsl_mx6_disable(struct platform_device *pdev)
957 {
958 struct dim2_hdm *dev = platform_get_drvdata(pdev);
959
960 if (dev->clk_speed >= CLK_2048FS)
961 clk_disable_unprepare(dev->clk_pll);
962
963 clk_disable_unprepare(dev->clk);
964 }
965
rcar_h2_enable(struct platform_device * pdev)966 static int rcar_h2_enable(struct platform_device *pdev)
967 {
968 struct dim2_hdm *dev = platform_get_drvdata(pdev);
969 int ret;
970
971 dev->clk = devm_clk_get(&pdev->dev, NULL);
972 if (IS_ERR(dev->clk)) {
973 dev_err(&pdev->dev, "cannot get clock\n");
974 return PTR_ERR(dev->clk);
975 }
976
977 ret = clk_prepare_enable(dev->clk);
978 if (ret) {
979 dev_err(&pdev->dev, "%s\n", "clk_prepare_enable failed");
980 return ret;
981 }
982
983 if (dev->clk_speed >= CLK_2048FS) {
984 /* enable MLP pll and LVDS drivers */
985 writel(0x03, dev->io_base + 0x600);
986 /* set bias */
987 writel(0x888, dev->io_base + 0x38);
988 } else {
989 /* PLL */
990 writel(0x04, dev->io_base + 0x600);
991 }
992
993
994 /* BBCR = 0b11 */
995 writel(0x03, dev->io_base + 0x500);
996 writel(0x0002FF02, dev->io_base + 0x508);
997
998 return 0;
999 }
1000
rcar_h2_disable(struct platform_device * pdev)1001 static void rcar_h2_disable(struct platform_device *pdev)
1002 {
1003 struct dim2_hdm *dev = platform_get_drvdata(pdev);
1004
1005 clk_disable_unprepare(dev->clk);
1006
1007 /* disable PLLs and LVDS drivers */
1008 writel(0x0, dev->io_base + 0x600);
1009 }
1010
rcar_m3_enable(struct platform_device * pdev)1011 static int rcar_m3_enable(struct platform_device *pdev)
1012 {
1013 struct dim2_hdm *dev = platform_get_drvdata(pdev);
1014 u32 enable_512fs = dev->clk_speed == CLK_512FS;
1015 int ret;
1016
1017 dev->clk = devm_clk_get(&pdev->dev, NULL);
1018 if (IS_ERR(dev->clk)) {
1019 dev_err(&pdev->dev, "cannot get clock\n");
1020 return PTR_ERR(dev->clk);
1021 }
1022
1023 ret = clk_prepare_enable(dev->clk);
1024 if (ret) {
1025 dev_err(&pdev->dev, "%s\n", "clk_prepare_enable failed");
1026 return ret;
1027 }
1028
1029 /* PLL */
1030 writel(0x04, dev->io_base + 0x600);
1031
1032 writel(enable_512fs, dev->io_base + 0x604);
1033
1034 /* BBCR = 0b11 */
1035 writel(0x03, dev->io_base + 0x500);
1036 writel(0x0002FF02, dev->io_base + 0x508);
1037
1038 return 0;
1039 }
1040
rcar_m3_disable(struct platform_device * pdev)1041 static void rcar_m3_disable(struct platform_device *pdev)
1042 {
1043 struct dim2_hdm *dev = platform_get_drvdata(pdev);
1044
1045 clk_disable_unprepare(dev->clk);
1046
1047 /* disable PLLs and LVDS drivers */
1048 writel(0x0, dev->io_base + 0x600);
1049 }
1050
1051 /* ]] platform specific functions */
1052
1053 enum dim2_platforms { FSL_MX6, RCAR_H2, RCAR_M3 };
1054
1055 static struct dim2_platform_data plat_data[] = {
1056 [FSL_MX6] = { .enable = fsl_mx6_enable, .disable = fsl_mx6_disable },
1057 [RCAR_H2] = { .enable = rcar_h2_enable, .disable = rcar_h2_disable },
1058 [RCAR_M3] = { .enable = rcar_m3_enable, .disable = rcar_m3_disable },
1059 };
1060
1061 static const struct of_device_id dim2_of_match[] = {
1062 {
1063 .compatible = "fsl,imx6q-mlb150",
1064 .data = plat_data + FSL_MX6
1065 },
1066 {
1067 .compatible = "renesas,mlp",
1068 .data = plat_data + RCAR_H2
1069 },
1070 {
1071 .compatible = "rcar,medialb-dim2",
1072 .data = plat_data + RCAR_M3
1073 },
1074 {
1075 .compatible = "xlnx,axi4-os62420_3pin-1.00.a",
1076 },
1077 {
1078 .compatible = "xlnx,axi4-os62420_6pin-1.00.a",
1079 },
1080 {},
1081 };
1082
1083 MODULE_DEVICE_TABLE(of, dim2_of_match);
1084
1085 static struct platform_driver dim2_driver = {
1086 .probe = dim2_probe,
1087 .remove = dim2_remove,
1088 .driver = {
1089 .name = "hdm_dim2",
1090 .of_match_table = dim2_of_match,
1091 .dev_groups = dim2_groups,
1092 },
1093 };
1094
1095 module_platform_driver(dim2_driver);
1096
1097 MODULE_AUTHOR("Andrey Shvetsov <andrey.shvetsov@k2l.de>");
1098 MODULE_DESCRIPTION("MediaLB DIM2 Hardware Dependent Module");
1099 MODULE_LICENSE("GPL");
1100