Lines Matching refs:ctxt
78 u64 ret = READ_ONCE(hyp_vcpu->host_vcpu->arch.ctxt.regs.regs[0]); in handle_pvm_entry_psci()
154 u64 rt_val = READ_ONCE(host_vcpu->arch.ctxt.regs.regs[0]); in handle_pvm_entry_sys64()
228 u64 rd_val = READ_ONCE(host_vcpu->arch.ctxt.regs.regs[0]); in handle_pvm_entry_dabt()
239 WRITE_ONCE(hyp_vcpu->host_vcpu->arch.ctxt.regs.pstate, in handle_pvm_exit_wfx()
240 hyp_vcpu->vcpu.arch.ctxt.regs.pstate & PSR_MODE_MASK); in handle_pvm_exit_wfx()
255 WRITE_ONCE(host_vcpu->arch.ctxt.regs.pstate, in handle_pvm_exit_sys64()
256 hyp_vcpu->vcpu.arch.ctxt.regs.pstate & PSR_MODE_MASK); in handle_pvm_exit_sys64()
262 WRITE_ONCE(host_vcpu->arch.ctxt.regs.regs[0], rt_val); in handle_pvm_exit_sys64()
320 WRITE_ONCE(host_vcpu->arch.ctxt.regs.regs[i], in handle_pvm_exit_hvc64()
348 WRITE_ONCE(host_vcpu->arch.ctxt.regs.regs[0], rt_val); in handle_pvm_exit_dabt()
355 WRITE_ONCE(host_vcpu->arch.ctxt.regs.pstate, in handle_pvm_exit_dabt()
356 hyp_vcpu->vcpu.arch.ctxt.regs.pstate & PSR_MODE_MASK); in handle_pvm_exit_dabt()
495 to_vcpu->arch.ctxt.regs = from_vcpu->arch.ctxt.regs; in __copy_vcpu_state()
496 to_vcpu->arch.ctxt.spsr_abt = from_vcpu->arch.ctxt.spsr_abt; in __copy_vcpu_state()
497 to_vcpu->arch.ctxt.spsr_und = from_vcpu->arch.ctxt.spsr_und; in __copy_vcpu_state()
498 to_vcpu->arch.ctxt.spsr_irq = from_vcpu->arch.ctxt.spsr_irq; in __copy_vcpu_state()
499 to_vcpu->arch.ctxt.spsr_fiq = from_vcpu->arch.ctxt.spsr_fiq; in __copy_vcpu_state()
508 to_vcpu->arch.ctxt.sys_regs[i] = from_vcpu->arch.ctxt.sys_regs[i]; in __copy_vcpu_state()
675 __sve_save_state(vcpu_sve_pffr(vcpu), &vcpu->arch.ctxt.fp_regs.fpsr); in __hyp_sve_save_guest()
692 __fpsimd_save_state(&hyp_vcpu->vcpu.arch.ctxt.fp_regs); in fpsimd_host_restore()
810 #define get_host_hyp_vcpus(ctxt, regnr, hyp_vcpup) \ argument
812 DECLARE_REG(struct kvm_vcpu *, __vcpu, ctxt, regnr); \
816 #define get_host_hyp_vcpus_from_vgic_v3_cpu_if(ctxt, regnr, hyp_vcpup) \ argument
818 DECLARE_REG(struct vgic_v3_cpu_if *, cif, ctxt, regnr); \