84 	struct hw_perf_event *hwc = &event->hw;  in amd_uncore_read()  local
93 	prev = local64_read(&hwc->prev_count);  in amd_uncore_read()
94 	rdpmcl(hwc->event_base_rdpmc, new);  in amd_uncore_read()
95 	local64_set(&hwc->prev_count, new);  in amd_uncore_read()
103 	struct hw_perf_event *hwc = &event->hw;  in amd_uncore_start()  local
106 		wrmsrl(hwc->event_base, (u64)local64_read(&hwc->prev_count));  in amd_uncore_start()
108 	hwc->state = 0;  in amd_uncore_start()
109 	wrmsrl(hwc->config_base, (hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE));  in amd_uncore_start()
115 	struct hw_perf_event *hwc = &event->hw;  in amd_uncore_stop()  local
117 	wrmsrl(hwc->config_base, hwc->config);  in amd_uncore_stop()
118 	hwc->state |= PERF_HES_STOPPED;  in amd_uncore_stop()
120 	if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {  in amd_uncore_stop()
122 		hwc->state |= PERF_HES_UPTODATE;  in amd_uncore_stop()
130 	struct hw_perf_event *hwc = &event->hw;  in amd_uncore_add()  local
133 	if (hwc->idx != -1 && uncore->events[hwc->idx] == event)  in amd_uncore_add()
138 			hwc->idx = i;  in amd_uncore_add()
144 	hwc->idx = -1;  in amd_uncore_add()
147 			hwc->idx = i;  in amd_uncore_add()
153 	if (hwc->idx == -1)  in amd_uncore_add()
156 	hwc->config_base = uncore->msr_base + (2 * hwc->idx);  in amd_uncore_add()
157 	hwc->event_base = uncore->msr_base + 1 + (2 * hwc->idx);  in amd_uncore_add()
158 	hwc->event_base_rdpmc = uncore->rdpmc_base + hwc->idx;  in amd_uncore_add()
159 	hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;  in amd_uncore_add()
171 	struct hw_perf_event *hwc = &event->hw;  in amd_uncore_del()  local
180 	hwc->idx = -1;  in amd_uncore_del()
211 	struct hw_perf_event *hwc = &event->hw;  in amd_uncore_event_init()  local
224 	hwc->config = event->attr.config & AMD64_RAW_EVENT_MASK_NB;  in amd_uncore_event_init()
225 	hwc->idx = -1;  in amd_uncore_event_init()
235 		hwc->config |= l3_thread_slice_mask(event->attr.config);  in amd_uncore_event_init()