Lines Matching refs:a4
165 s32i a4, a2, PT_AREG4
176 movi a4, fast_unaligned_fixup
177 s32i a4, a3, EXC_TABLE_FIXUP
205 l32i a4, a3, 0 # load 2 words
209 __src_b a4, a4, a5 # a4 has the instruction
213 extui a5, a4, INSN_OP0, 4 # get insn.op0 nibble
221 _bbci.l a4, OP1_SI_BIT + INSN_OP1, .Lload
226 extui a6, a4, INSN_T, 4 # get source register
249 extui a5, a4, INSN_OP0, 4
257 extui a5, a4, INSN_OP1, 4
273 extui a4, a4, INSN_T, 4 # extract target register
275 addx8 a4, a4, a5
276 jx a4 # jump to entry for target register
321 movi a4, 0
323 s32i a4, a3, EXC_TABLE_FIXUP
331 l32i a4, a2, PT_AREG4
344 1: # a7: instruction pointer, a4: instruction, a3: value
351 extui a5, a4, INSN_OP0, 4 # extract OP0
360 extui a5, a4, INSN_OP1, 4 # extract OP1
371 movi a4, ~3
372 and a4, a4, a8 # align memory address
378 addi a4, a4, 8
385 l32e a5, a4, -8
387 l32i a5, a4, 0 # load lower address word
393 s32e a5, a4, -8
394 l32e a8, a4, -4
396 s32i a5, a4, 0 # store
397 l32i a8, a4, 4 # same for upper address word
403 s32e a6, a4, -4
405 s32i a6, a4, 4
410 rsr a4, lend # check if we reached LEND
411 bne a7, a4, 1f
412 rsr a4, lcount # and LCOUNT != 0
413 beqz a4, 1f
414 addi a4, a4, -1 # decrement LCOUNT and set
416 wsr a4, lcount
422 rsr a4, icountlevel
423 beqz a4, 1f
424 bgeui a4, LOCKLEVEL + 1, 1f
425 rsr a4, icount
426 addi a4, a4, 1
427 wsr a4, icount
429 movi a4, 0
431 s32i a4, a3, EXC_TABLE_FIXUP
439 l32i a4, a2, PT_AREG4
460 l32i a4, a2, PT_AREG4