491 	u32 ctl_reg;  member
514 	u32 ctl_reg;  member
933 	return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0;  in bcm2835_clock_is_on()
1049 	while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) {  in bcm2835_clock_wait_busy()
1066 	cprman_write(cprman, data->ctl_reg,  in bcm2835_clock_off()
1067 		     cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE);  in bcm2835_clock_off()
1081 	cprman_write(cprman, data->ctl_reg,  in bcm2835_clock_on()
1082 		     cprman_read(cprman, data->ctl_reg) |  in bcm2835_clock_on()
1120 	ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC;  in bcm2835_clock_set_rate()
1122 	cprman_write(cprman, data->ctl_reg, ctl);  in bcm2835_clock_set_rate()
1270 	cprman_write(cprman, data->ctl_reg, src);  in bcm2835_clock_set_parent()
1279 	u32 src = cprman_read(cprman, data->ctl_reg);  in bcm2835_clock_get_parent()
1302 	bcm2835_debugfs_regset(cprman, data->ctl_reg,  in bcm2835_clock_debug_init()
1480 		if (!(cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE))  in bcm2835_register_clock()
1506 				    cprman->regs + gate_data->ctl_reg,  in bcm2835_register_gate()
1945 		.ctl_reg = CM_OTPCTL,
1957 		.ctl_reg = CM_TIMERCTL,
1968 		.ctl_reg = CM_TSENSCTL,
1975 		.ctl_reg = CM_TECCTL,
1984 		.ctl_reg = CM_H264CTL,
1992 		.ctl_reg = CM_ISPCTL,
2005 		.ctl_reg = CM_SDCCTL,
2013 		.ctl_reg = CM_V3DCTL,
2027 		.ctl_reg = CM_VPUCTL,
2039 		.ctl_reg = CM_AVEOCTL,
2047 		.ctl_reg = CM_CAM0CTL,
2055 		.ctl_reg = CM_CAM1CTL,
2063 		.ctl_reg = CM_DFTCTL,
2070 		.ctl_reg = CM_DPICTL,
2080 		.ctl_reg = CM_EMMCCTL,
2090 		.ctl_reg = CM_EMMC2CTL,
2100 		.ctl_reg = CM_GP0CTL,
2109 		.ctl_reg = CM_GP1CTL,
2119 		.ctl_reg = CM_GP2CTL,
2129 		.ctl_reg = CM_HSMCTL,
2137 		.ctl_reg = CM_PCMCTL,
2147 		.ctl_reg = CM_PWMCTL,
2156 		.ctl_reg = CM_SLIMCTL,
2165 		.ctl_reg = CM_SMICTL,
2173 		.ctl_reg = CM_UARTCTL,
2184 		.ctl_reg = CM_VECCTL,
2199 		.ctl_reg = CM_DSI0ECTL,
2207 		.ctl_reg = CM_DSI1ECTL,
2215 		.ctl_reg = CM_DSI0PCTL,
2223 		.ctl_reg = CM_DSI1PCTL,
2241 		.ctl_reg = CM_PERIICTL),