88 	u32 ctl;  in ingenic_pll_recalc_rate()  local
93 	ctl = readl(cgu->base + pll_info->reg);  in ingenic_pll_recalc_rate()
95 	m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0);  in ingenic_pll_recalc_rate()
97 	n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0);  in ingenic_pll_recalc_rate()
99 	od_enc = ctl >> pll_info->od_shift;  in ingenic_pll_recalc_rate()
103 		ctl = readl(cgu->base + pll_info->bypass_reg);  in ingenic_pll_recalc_rate()
105 		bypass = !!(ctl & BIT(pll_info->bypass_bit));  in ingenic_pll_recalc_rate()
183 	u32 ctl;  in ingenic_pll_check_stable()  local
185 	return readl_poll_timeout(cgu->base + pll_info->reg, ctl,  in ingenic_pll_check_stable()
186 				  ctl & BIT(pll_info->stable_bit),  in ingenic_pll_check_stable()
201 	u32 ctl;  in ingenic_pll_set_rate()  local
210 	ctl = readl(cgu->base + pll_info->reg);  in ingenic_pll_set_rate()
212 	ctl &= ~(GENMASK(pll_info->m_bits - 1, 0) << pll_info->m_shift);  in ingenic_pll_set_rate()
213 	ctl |= (m - pll_info->m_offset) << pll_info->m_shift;  in ingenic_pll_set_rate()
215 	ctl &= ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift);  in ingenic_pll_set_rate()
216 	ctl |= (n - pll_info->n_offset) << pll_info->n_shift;  in ingenic_pll_set_rate()
218 	ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift);  in ingenic_pll_set_rate()
219 	ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift;  in ingenic_pll_set_rate()
221 	writel(ctl, cgu->base + pll_info->reg);  in ingenic_pll_set_rate()
224 	if (ctl & BIT(pll_info->enable_bit))  in ingenic_pll_set_rate()
240 	u32 ctl;  in ingenic_pll_enable()  local
244 		ctl = readl(cgu->base + pll_info->bypass_reg);  in ingenic_pll_enable()
246 		ctl &= ~BIT(pll_info->bypass_bit);  in ingenic_pll_enable()
248 		writel(ctl, cgu->base + pll_info->bypass_reg);  in ingenic_pll_enable()
251 	ctl = readl(cgu->base + pll_info->reg);  in ingenic_pll_enable()
253 	ctl |= BIT(pll_info->enable_bit);  in ingenic_pll_enable()
255 	writel(ctl, cgu->base + pll_info->reg);  in ingenic_pll_enable()
270 	u32 ctl;  in ingenic_pll_disable()  local
273 	ctl = readl(cgu->base + pll_info->reg);  in ingenic_pll_disable()
275 	ctl &= ~BIT(pll_info->enable_bit);  in ingenic_pll_disable()
277 	writel(ctl, cgu->base + pll_info->reg);  in ingenic_pll_disable()
287 	u32 ctl;  in ingenic_pll_is_enabled()  local
289 	ctl = readl(cgu->base + pll_info->reg);  in ingenic_pll_is_enabled()
291 	return !!(ctl & BIT(pll_info->enable_bit));  in ingenic_pll_is_enabled()