388 	u32 div_reg, div;  in ingenic_clk_recalc_rate()  local
394 		if (!(clk_info->div.bypass_mask & BIT(parent))) {  in ingenic_clk_recalc_rate()
395 			div_reg = readl(cgu->base + clk_info->div.reg);  in ingenic_clk_recalc_rate()
396 			div = (div_reg >> clk_info->div.shift) &  in ingenic_clk_recalc_rate()
397 			      GENMASK(clk_info->div.bits - 1, 0);  in ingenic_clk_recalc_rate()
399 			if (clk_info->div.div_table)  in ingenic_clk_recalc_rate()
400 				div = clk_info->div.div_table[div];  in ingenic_clk_recalc_rate()
402 				div = (div + 1) * clk_info->div.div;  in ingenic_clk_recalc_rate()
404 			rate /= div;  in ingenic_clk_recalc_rate()
407 		rate /= clk_info->fixdiv.div;  in ingenic_clk_recalc_rate()
415 			unsigned int div)  in ingenic_clk_calc_hw_div()  argument
419 	for (i = 0; i < (1 << clk_info->div.bits)  in ingenic_clk_calc_hw_div()
420 				&& clk_info->div.div_table[i]; i++) {  in ingenic_clk_calc_hw_div()
421 		if (clk_info->div.div_table[i] >= div &&  in ingenic_clk_calc_hw_div()
422 		    clk_info->div.div_table[i] < best) {  in ingenic_clk_calc_hw_div()
423 			best = clk_info->div.div_table[i];  in ingenic_clk_calc_hw_div()
426 			if (div == best)  in ingenic_clk_calc_hw_div()
439 	unsigned int div, hw_div;  in ingenic_clk_calc_div()  local
443 	if (clk_info->div.bypass_mask & BIT(parent))  in ingenic_clk_calc_div()
447 	div = DIV_ROUND_UP(parent_rate, req_rate);  in ingenic_clk_calc_div()
449 	if (clk_info->div.div_table) {  in ingenic_clk_calc_div()
450 		hw_div = ingenic_clk_calc_hw_div(clk_info, div);  in ingenic_clk_calc_div()
452 		return clk_info->div.div_table[hw_div];  in ingenic_clk_calc_div()
456 	div = clamp_t(unsigned int, div, clk_info->div.div,  in ingenic_clk_calc_div()
457 		      clk_info->div.div << clk_info->div.bits);  in ingenic_clk_calc_div()
464 	div = DIV_ROUND_UP(div, clk_info->div.div);  in ingenic_clk_calc_div()
465 	div *= clk_info->div.div;  in ingenic_clk_calc_div()
467 	return div;  in ingenic_clk_calc_div()
476 	unsigned int div = 1;  in ingenic_clk_round_rate()  local
479 		div = ingenic_clk_calc_div(hw, clk_info, *parent_rate, req_rate);  in ingenic_clk_round_rate()
481 		div = clk_info->fixdiv.div;  in ingenic_clk_round_rate()
485 	return DIV_ROUND_UP(*parent_rate, div);  in ingenic_clk_round_rate()
493 	return readl_poll_timeout(cgu->base + clk_info->div.reg, reg,  in ingenic_clk_check_stable()
494 				  !(reg & BIT(clk_info->div.busy_bit)),  in ingenic_clk_check_stable()
506 	unsigned int hw_div, div;  in ingenic_clk_set_rate()  local
511 		div = ingenic_clk_calc_div(hw, clk_info, parent_rate, req_rate);  in ingenic_clk_set_rate()
512 		rate = DIV_ROUND_UP(parent_rate, div);  in ingenic_clk_set_rate()
517 		if (clk_info->div.div_table)  in ingenic_clk_set_rate()
518 			hw_div = ingenic_clk_calc_hw_div(clk_info, div);  in ingenic_clk_set_rate()
520 			hw_div = ((div / clk_info->div.div) - 1);  in ingenic_clk_set_rate()
523 		reg = readl(cgu->base + clk_info->div.reg);  in ingenic_clk_set_rate()
526 		mask = GENMASK(clk_info->div.bits - 1, 0);  in ingenic_clk_set_rate()
527 		reg &= ~(mask << clk_info->div.shift);  in ingenic_clk_set_rate()
528 		reg |= hw_div << clk_info->div.shift;  in ingenic_clk_set_rate()
531 		if (clk_info->div.stop_bit != -1)  in ingenic_clk_set_rate()
532 			reg &= ~BIT(clk_info->div.stop_bit);  in ingenic_clk_set_rate()
535 		if (clk_info->div.ce_bit != -1)  in ingenic_clk_set_rate()
536 			reg |= BIT(clk_info->div.ce_bit);  in ingenic_clk_set_rate()
539 		writel(reg, cgu->base + clk_info->div.reg);  in ingenic_clk_set_rate()
542 		if (clk_info->div.busy_bit != -1)  in ingenic_clk_set_rate()