Lines Matching refs:clks
145 static struct clk *clks[clk_max]; variable
167 clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); in mx28_clocks_init()
168 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); in mx28_clocks_init()
169 clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); in mx28_clocks_init()
170 clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); in mx28_clocks_init()
171 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0); in mx28_clocks_init()
172 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1); in mx28_clocks_init()
173 clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2); in mx28_clocks_init()
174 clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3); in mx28_clocks_init()
175 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0); in mx28_clocks_init()
176 clks[ref_hsadc] = mxs_clk_ref("ref_hsadc", "pll0", FRAC1, 1); in mx28_clocks_init()
177 clks[ref_gpmi] = mxs_clk_ref("ref_gpmi", "pll0", FRAC1, 2); in mx28_clocks_init()
178 clks[saif0_sel] = mxs_clk_mux("saif0_sel", CLKSEQ, 0, 1, sel_pll0, ARRAY_SIZE(sel_pll0)); in mx28_clocks_init()
179 clks[saif1_sel] = mxs_clk_mux("saif1_sel", CLKSEQ, 1, 1, sel_pll0, ARRAY_SIZE(sel_pll0)); in mx28_clocks_init()
180 clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 2, 1, sel_gpmi, ARRAY_SIZE(sel_gpmi)); in mx28_clocks_init()
181 clks[ssp0_sel] = mxs_clk_mux("ssp0_sel", CLKSEQ, 3, 1, sel_io0, ARRAY_SIZE(sel_io0)); in mx28_clocks_init()
182 clks[ssp1_sel] = mxs_clk_mux("ssp1_sel", CLKSEQ, 4, 1, sel_io0, ARRAY_SIZE(sel_io0)); in mx28_clocks_init()
183 clks[ssp2_sel] = mxs_clk_mux("ssp2_sel", CLKSEQ, 5, 1, sel_io1, ARRAY_SIZE(sel_io1)); in mx28_clocks_init()
184 clks[ssp3_sel] = mxs_clk_mux("ssp3_sel", CLKSEQ, 6, 1, sel_io1, ARRAY_SIZE(sel_io1)); in mx28_clocks_init()
185 clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 7, 1, emi_sels, ARRAY_SIZE(emi_sels)); in mx28_clocks_init()
186 clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu)); in mx28_clocks_init()
187 clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 14, 1, sel_pix, ARRAY_SIZE(sel_pix)); in mx28_clocks_init()
188 clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 18, 1, cpu_sels, ARRAY_SIZE(cpu_sels)); in mx28_clocks_init()
189 clks[ptp_sel] = mxs_clk_mux("ptp_sel", ENET, 19, 1, ptp_sels, ARRAY_SIZE(ptp_sels)); in mx28_clocks_init()
190 clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28); in mx28_clocks_init()
191 clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29); in mx28_clocks_init()
192 clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 31); in mx28_clocks_init()
193 clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31); in mx28_clocks_init()
194 clks[ssp0_div] = mxs_clk_div("ssp0_div", "ssp0_sel", SSP0, 0, 9, 29); in mx28_clocks_init()
195 clks[ssp1_div] = mxs_clk_div("ssp1_div", "ssp1_sel", SSP1, 0, 9, 29); in mx28_clocks_init()
196 clks[ssp2_div] = mxs_clk_div("ssp2_div", "ssp2_sel", SSP2, 0, 9, 29); in mx28_clocks_init()
197 clks[ssp3_div] = mxs_clk_div("ssp3_div", "ssp3_sel", SSP3, 0, 9, 29); in mx28_clocks_init()
198 clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29); in mx28_clocks_init()
199 clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28); in mx28_clocks_init()
200 clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29); in mx28_clocks_init()
201 clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", LCDIF, 0, 13, 29); in mx28_clocks_init()
202 clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 7, 29); in mx28_clocks_init()
203 clks[ptp] = mxs_clk_div("ptp", "ptp_sel", ENET, 21, 6, 27); in mx28_clocks_init()
204 clks[saif0_div] = mxs_clk_frac("saif0_div", "saif0_sel", SAIF0, 0, 16, 29); in mx28_clocks_init()
205 clks[saif1_div] = mxs_clk_frac("saif1_div", "saif1_sel", SAIF1, 0, 16, 29); in mx28_clocks_init()
206 clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750); in mx28_clocks_init()
207 clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768); in mx28_clocks_init()
208 clks[lradc] = mxs_clk_fixed_factor("lradc", "clk32k", 1, 16); in mx28_clocks_init()
209 clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll0", 1, 4); in mx28_clocks_init()
210 clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26); in mx28_clocks_init()
211 clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29); in mx28_clocks_init()
212 clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31); in mx28_clocks_init()
213 clks[ssp0] = mxs_clk_gate("ssp0", "ssp0_div", SSP0, 31); in mx28_clocks_init()
214 clks[ssp1] = mxs_clk_gate("ssp1", "ssp1_div", SSP1, 31); in mx28_clocks_init()
215 clks[ssp2] = mxs_clk_gate("ssp2", "ssp2_div", SSP2, 31); in mx28_clocks_init()
216 clks[ssp3] = mxs_clk_gate("ssp3", "ssp3_div", SSP3, 31); in mx28_clocks_init()
217 clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31); in mx28_clocks_init()
218 clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31); in mx28_clocks_init()
219 clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31); in mx28_clocks_init()
220 clks[saif0] = mxs_clk_gate("saif0", "saif0_div", SAIF0, 31); in mx28_clocks_init()
221 clks[saif1] = mxs_clk_gate("saif1", "saif1_div", SAIF1, 31); in mx28_clocks_init()
222 clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", LCDIF, 31); in mx28_clocks_init()
223 clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31); in mx28_clocks_init()
224 clks[fec] = mxs_clk_gate("fec", "hbus", ENET, 30); in mx28_clocks_init()
225 clks[can0] = mxs_clk_gate("can0", "ref_xtal", FLEXCAN, 30); in mx28_clocks_init()
226 clks[can1] = mxs_clk_gate("can1", "ref_xtal", FLEXCAN, 28); in mx28_clocks_init()
227 clks[usb0] = mxs_clk_gate("usb0", "usb0_phy", DIGCTRL, 2); in mx28_clocks_init()
228 clks[usb1] = mxs_clk_gate("usb1", "usb1_phy", DIGCTRL, 16); in mx28_clocks_init()
229 clks[usb0_phy] = clk_register_gate(NULL, "usb0_phy", "pll0", 0, PLL0CTRL0, 18, 0, &mxs_lock); in mx28_clocks_init()
230 clks[usb1_phy] = clk_register_gate(NULL, "usb1_phy", "pll1", 0, PLL1CTRL0, 18, 0, &mxs_lock); in mx28_clocks_init()
231 clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock); in mx28_clocks_init()
233 for (i = 0; i < ARRAY_SIZE(clks); i++) in mx28_clocks_init()
234 if (IS_ERR(clks[i])) { in mx28_clocks_init()
236 i, PTR_ERR(clks[i])); in mx28_clocks_init()
240 clk_data.clks = clks; in mx28_clocks_init()
241 clk_data.clk_num = ARRAY_SIZE(clks); in mx28_clocks_init()
244 clk_register_clkdev(clks[enet_out], NULL, "enet_out"); in mx28_clocks_init()
247 clk_prepare_enable(clks[clks_init_on[i]]); in mx28_clocks_init()