Lines Matching refs:pll_params
1202 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params, in _pll_fixed_mdiv() argument
1205 u16 mdiv = parent_rate / pll_params->cf_min; in _pll_fixed_mdiv()
1207 if (pll_params->flags & TEGRA_MDIV_NEW) in _pll_fixed_mdiv()
1208 return (!pll_params->mdiv_default ? mdiv : in _pll_fixed_mdiv()
1209 min(mdiv, pll_params->mdiv_default)); in _pll_fixed_mdiv()
1211 if (pll_params->mdiv_default) in _pll_fixed_mdiv()
1212 return pll_params->mdiv_default; in _pll_fixed_mdiv()
1214 if (parent_rate > pll_params->cf_max) in _pll_fixed_mdiv()
1267 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params, in _setup_dynamic_ramp() argument
1296 val = step_a << pll_params->stepa_shift; in _setup_dynamic_ramp()
1297 val |= step_b << pll_params->stepb_shift; in _setup_dynamic_ramp()
1298 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); in _setup_dynamic_ramp()
1870 void __iomem *pmc, struct tegra_clk_pll_params *pll_params, in _tegra_init_pll() argument
1882 pll->params = pll_params; in _tegra_init_pll()
1885 if (!pll_params->div_nmp) in _tegra_init_pll()
1886 pll_params->div_nmp = &default_nmp; in _tegra_init_pll()
1922 unsigned long flags, struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pll() argument
1928 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pll()
1930 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pll()
1953 unsigned long flags, struct tegra_clk_pll_params *pll_params, in tegra_clk_register_plle() argument
1959 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_plle()
1961 if (!pll_params->div_nmp) in tegra_clk_register_plle()
1962 pll_params->div_nmp = &pll_e_nmp; in tegra_clk_register_plle()
1964 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_plle()
1978 struct tegra_clk_pll_params *pll_params, spinlock_t *lock) in tegra_clk_register_pllu() argument
1983 pll_params->flags |= TEGRA_PLLU; in tegra_clk_register_pllu()
1985 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_pllu()
2045 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllxc() argument
2060 if (!pll_params->pdiv_tohw) in tegra_clk_register_pllxc()
2065 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllxc()
2067 if (pll_params->adjust_vco) in tegra_clk_register_pllxc()
2068 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllxc()
2075 if (!pll_params->set_defaults) { in tegra_clk_register_pllxc()
2078 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate); in tegra_clk_register_pllxc()
2082 val = readl_relaxed(clk_base + pll_params->base_reg); in tegra_clk_register_pllxc()
2083 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); in tegra_clk_register_pllxc()
2086 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx)); in tegra_clk_register_pllxc()
2088 val_iddq |= BIT(pll_params->iddq_bit_idx); in tegra_clk_register_pllxc()
2090 clk_base + pll_params->iddq_reg); in tegra_clk_register_pllxc()
2094 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllxc()
2109 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllre() argument
2116 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllre()
2118 if (pll_params->adjust_vco) in tegra_clk_register_pllre()
2119 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllre()
2122 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllre()
2130 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) & in tegra_clk_register_pllre()
2131 BIT(pll_params->iddq_bit_idx)); in tegra_clk_register_pllre()
2135 m = _pll_fixed_mdiv(pll_params, parent_rate); in tegra_clk_register_pllre()
2137 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll); in tegra_clk_register_pllre()
2158 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllm() argument
2165 if (!pll_params->pdiv_tohw) in tegra_clk_register_pllm()
2177 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllm()
2179 if (pll_params->adjust_vco) in tegra_clk_register_pllm()
2180 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllm()
2183 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllm()
2184 pll_params->flags |= TEGRA_PLLM; in tegra_clk_register_pllm()
2185 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllm()
2200 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllc() argument
2204 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; in tegra_clk_register_pllc()
2221 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllc()
2223 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllc()
2224 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllc()
2237 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); in tegra_clk_register_pllc()
2238 cfg.n = cfg.m * pll_params->vco_min / parent_rate; in tegra_clk_register_pllc()
2257 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll); in tegra_clk_register_pllc()
2258 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll); in tegra_clk_register_pllc()
2259 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll); in tegra_clk_register_pllc()
2274 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_plle_tegra114() argument
2280 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_plle_tegra114()
2297 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllu_tegra114() argument
2303 pll_params->flags |= TEGRA_PLLU; in tegra_clk_register_pllu_tegra114()
2305 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_pllu_tegra114()
2331 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllss() argument
2341 if (!pll_params->div_nmp) in tegra_clk_register_pllss()
2351 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_pllss()
2361 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllss()
2365 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); in tegra_clk_register_pllss()
2366 cfg.n = cfg.m * pll_params->vco_min / parent_rate; in tegra_clk_register_pllss()
2368 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++) in tegra_clk_register_pllss()
2375 cfg.p = pll_params->pdiv_tohw[i-1].hw_val; in tegra_clk_register_pllss()
2380 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll); in tegra_clk_register_pllss()
2381 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll); in tegra_clk_register_pllss()
2382 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll); in tegra_clk_register_pllss()
2385 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); in tegra_clk_register_pllss()
2387 if (val_iddq & BIT(pll_params->iddq_bit_idx)) { in tegra_clk_register_pllss()
2393 val_iddq |= BIT(pll_params->iddq_bit_idx); in tegra_clk_register_pllss()
2394 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg); in tegra_clk_register_pllss()
2414 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllre_tegra210() argument
2420 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllre_tegra210()
2422 if (pll_params->adjust_vco) in tegra_clk_register_pllre_tegra210()
2423 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllre_tegra210()
2426 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllre_tegra210()
2577 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_plle_tegra210() argument
2583 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_plle_tegra210()
2600 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllc_tegra210() argument
2604 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; in tegra_clk_register_pllc_tegra210()
2620 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllc_tegra210()
2622 if (pll_params->adjust_vco) in tegra_clk_register_pllc_tegra210()
2623 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllc_tegra210()
2626 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllc_tegra210()
2627 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllc_tegra210()
2642 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllss_tegra210() argument
2650 if (!pll_params->div_nmp) in tegra_clk_register_pllss_tegra210()
2660 val = readl_relaxed(clk_base + pll_params->base_reg); in tegra_clk_register_pllss_tegra210()
2668 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllss_tegra210()
2670 if (pll_params->adjust_vco) in tegra_clk_register_pllss_tegra210()
2671 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllss_tegra210()
2674 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllss_tegra210()
2675 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_pllss_tegra210()
2691 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllmb() argument
2698 if (!pll_params->pdiv_tohw) in tegra_clk_register_pllmb()
2710 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllmb()
2712 if (pll_params->adjust_vco) in tegra_clk_register_pllmb()
2713 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllmb()
2716 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllmb()
2717 pll_params->flags |= TEGRA_PLLMB; in tegra_clk_register_pllmb()
2718 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllmb()