Lines Matching refs:devpriv
441 struct ni_private *devpriv = dev->private; in ni_stc_writew() local
444 if (devpriv->is_m_series) { in ni_stc_writew()
447 spin_lock_irqsave(&devpriv->window_lock, flags); in ni_stc_writew()
448 if (!devpriv->mite && reg < 8) { in ni_stc_writew()
454 spin_unlock_irqrestore(&devpriv->window_lock, flags); in ni_stc_writew()
461 struct ni_private *devpriv = dev->private; in ni_stc_writel() local
463 if (devpriv->is_m_series) { in ni_stc_writel()
473 struct ni_private *devpriv = dev->private; in ni_stc_readw() local
477 if (devpriv->is_m_series) { in ni_stc_readw()
480 spin_lock_irqsave(&devpriv->window_lock, flags); in ni_stc_readw()
481 if (!devpriv->mite && reg < 8) { in ni_stc_readw()
487 spin_unlock_irqrestore(&devpriv->window_lock, flags); in ni_stc_readw()
494 struct ni_private *devpriv = dev->private; in ni_stc_readl() local
497 if (devpriv->is_m_series) { in ni_stc_readl()
510 struct ni_private *devpriv = dev->private; in ni_set_bitfield() local
513 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags); in ni_set_bitfield()
516 devpriv->int_a_enable_reg &= ~bit_mask; in ni_set_bitfield()
517 devpriv->int_a_enable_reg |= bit_values & bit_mask; in ni_set_bitfield()
518 ni_stc_writew(dev, devpriv->int_a_enable_reg, reg); in ni_set_bitfield()
521 devpriv->int_b_enable_reg &= ~bit_mask; in ni_set_bitfield()
522 devpriv->int_b_enable_reg |= bit_values & bit_mask; in ni_set_bitfield()
523 ni_stc_writew(dev, devpriv->int_b_enable_reg, reg); in ni_set_bitfield()
526 devpriv->io_bidirection_pin_reg &= ~bit_mask; in ni_set_bitfield()
527 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask; in ni_set_bitfield()
528 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg); in ni_set_bitfield()
531 devpriv->ai_ao_select_reg &= ~bit_mask; in ni_set_bitfield()
532 devpriv->ai_ao_select_reg |= bit_values & bit_mask; in ni_set_bitfield()
533 ni_writeb(dev, devpriv->ai_ao_select_reg, reg); in ni_set_bitfield()
536 devpriv->g0_g1_select_reg &= ~bit_mask; in ni_set_bitfield()
537 devpriv->g0_g1_select_reg |= bit_values & bit_mask; in ni_set_bitfield()
538 ni_writeb(dev, devpriv->g0_g1_select_reg, reg); in ni_set_bitfield()
541 devpriv->cdio_dma_select_reg &= ~bit_mask; in ni_set_bitfield()
542 devpriv->cdio_dma_select_reg |= bit_values & bit_mask; in ni_set_bitfield()
543 ni_writeb(dev, devpriv->cdio_dma_select_reg, reg); in ni_set_bitfield()
550 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags); in ni_set_bitfield()
563 struct ni_private *devpriv = dev->private; in ni_request_ai_mite_channel() local
568 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_request_ai_mite_channel()
569 mite_chan = mite_request_channel(devpriv->mite, devpriv->ai_mite_ring); in ni_request_ai_mite_channel()
571 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_request_ai_mite_channel()
577 devpriv->ai_mite_chan = mite_chan; in ni_request_ai_mite_channel()
583 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_request_ai_mite_channel()
589 struct ni_private *devpriv = dev->private; in ni_request_ao_mite_channel() local
594 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_request_ao_mite_channel()
595 mite_chan = mite_request_channel(devpriv->mite, devpriv->ao_mite_ring); in ni_request_ao_mite_channel()
597 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_request_ao_mite_channel()
603 devpriv->ao_mite_chan = mite_chan; in ni_request_ao_mite_channel()
609 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_request_ao_mite_channel()
617 struct ni_private *devpriv = dev->private; in ni_request_gpct_mite_channel() local
618 struct ni_gpct *counter = &devpriv->counter_dev->counters[gpct_index]; in ni_request_gpct_mite_channel()
623 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_request_gpct_mite_channel()
624 mite_chan = mite_request_channel(devpriv->mite, in ni_request_gpct_mite_channel()
625 devpriv->gpct_mite_ring[gpct_index]); in ni_request_gpct_mite_channel()
627 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_request_gpct_mite_channel()
640 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_request_gpct_mite_channel()
646 struct ni_private *devpriv = dev->private; in ni_request_cdo_mite_channel() local
651 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_request_cdo_mite_channel()
652 mite_chan = mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring); in ni_request_cdo_mite_channel()
654 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_request_cdo_mite_channel()
660 devpriv->cdo_mite_chan = mite_chan; in ni_request_cdo_mite_channel()
673 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_request_cdo_mite_channel()
681 struct ni_private *devpriv = dev->private; in ni_release_ai_mite_channel() local
684 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_release_ai_mite_channel()
685 if (devpriv->ai_mite_chan) { in ni_release_ai_mite_channel()
688 mite_release_channel(devpriv->ai_mite_chan); in ni_release_ai_mite_channel()
689 devpriv->ai_mite_chan = NULL; in ni_release_ai_mite_channel()
691 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_release_ai_mite_channel()
698 struct ni_private *devpriv = dev->private; in ni_release_ao_mite_channel() local
701 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_release_ao_mite_channel()
702 if (devpriv->ao_mite_chan) { in ni_release_ao_mite_channel()
705 mite_release_channel(devpriv->ao_mite_chan); in ni_release_ao_mite_channel()
706 devpriv->ao_mite_chan = NULL; in ni_release_ao_mite_channel()
708 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_release_ao_mite_channel()
716 struct ni_private *devpriv = dev->private; in ni_release_gpct_mite_channel() local
719 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_release_gpct_mite_channel()
720 if (devpriv->counter_dev->counters[gpct_index].mite_chan) { in ni_release_gpct_mite_channel()
722 devpriv->counter_dev->counters[gpct_index].mite_chan; in ni_release_gpct_mite_channel()
726 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index], in ni_release_gpct_mite_channel()
730 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_release_gpct_mite_channel()
735 struct ni_private *devpriv = dev->private; in ni_release_cdo_mite_channel() local
738 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_release_cdo_mite_channel()
739 if (devpriv->cdo_mite_chan) { in ni_release_cdo_mite_channel()
742 mite_release_channel(devpriv->cdo_mite_chan); in ni_release_cdo_mite_channel()
743 devpriv->cdo_mite_chan = NULL; in ni_release_cdo_mite_channel()
745 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_release_cdo_mite_channel()
751 struct ni_private *devpriv = dev->private; in ni_e_series_enable_second_irq() local
755 if (devpriv->is_m_series || gpct_index > 1) in ni_e_series_enable_second_irq()
777 struct ni_private *devpriv = dev->private; in ni_clear_ai_fifo() local
781 if (devpriv->is_6143) { in ni_clear_ai_fifo()
795 if (devpriv->is_625x) { in ni_clear_ai_fifo()
817 struct ni_private *devpriv = dev->private; in ni_ao_win_outw() local
820 spin_lock_irqsave(&devpriv->window_lock, flags); in ni_ao_win_outw()
823 spin_unlock_irqrestore(&devpriv->window_lock, flags); in ni_ao_win_outw()
829 struct ni_private *devpriv = dev->private; in ni_ao_win_outl() local
832 spin_lock_irqsave(&devpriv->window_lock, flags); in ni_ao_win_outl()
835 spin_unlock_irqrestore(&devpriv->window_lock, flags); in ni_ao_win_outl()
840 struct ni_private *devpriv = dev->private; in ni_ao_win_inw() local
844 spin_lock_irqsave(&devpriv->window_lock, flags); in ni_ao_win_inw()
847 spin_unlock_irqrestore(&devpriv->window_lock, flags); in ni_ao_win_inw()
877 struct ni_private *devpriv = dev->private; in ni_sync_ai_dma() local
881 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_sync_ai_dma()
882 if (devpriv->ai_mite_chan) in ni_sync_ai_dma()
883 mite_sync_dma(devpriv->ai_mite_chan, s); in ni_sync_ai_dma()
884 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_sync_ai_dma()
889 struct ni_private *devpriv = dev->private; in ni_ai_drain_dma() local
895 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_ai_drain_dma()
896 if (devpriv->ai_mite_chan) { in ni_ai_drain_dma()
900 mite_bytes_in_transit(devpriv->ai_mite_chan) == 0) in ni_ai_drain_dma()
908 mite_bytes_in_transit(devpriv->ai_mite_chan), in ni_ai_drain_dma()
913 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_ai_drain_dma()
950 struct ni_private *devpriv = dev->private; in ni_ao_fifo_load() local
958 if (devpriv->is_6xxx) { in ni_ao_fifo_load()
961 if (!devpriv->is_6711) { in ni_ao_fifo_load()
1015 struct ni_private *devpriv = dev->private; in ni_ao_prep_fifo() local
1021 if (devpriv->is_6xxx) in ni_ao_prep_fifo()
1041 struct ni_private *devpriv = dev->private; in ni_ai_fifo_read() local
1047 if (devpriv->is_611x) { in ni_ai_fifo_read()
1062 } else if (devpriv->is_6143) { in ni_ai_fifo_read()
1084 if (n > ARRAY_SIZE(devpriv->ai_fifo_buffer)) { in ni_ai_fifo_read()
1091 devpriv->ai_fifo_buffer[i] = in ni_ai_fifo_read()
1094 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n); in ni_ai_fifo_read()
1113 struct ni_private *devpriv = dev->private; in ni_handle_fifo_dregs() local
1119 if (devpriv->is_611x) { in ni_handle_fifo_dregs()
1130 } else if (devpriv->is_6143) { in ni_handle_fifo_dregs()
1158 i < ARRAY_SIZE(devpriv->ai_fifo_buffer); i++) { in ni_handle_fifo_dregs()
1163 devpriv->ai_fifo_buffer[i] = in ni_handle_fifo_dregs()
1166 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i); in ni_handle_fifo_dregs()
1173 struct ni_private *devpriv = dev->private; in get_last_sample_611x() local
1178 if (!devpriv->is_611x) in get_last_sample_611x()
1191 struct ni_private *devpriv = dev->private; in get_last_sample_6143() local
1196 if (!devpriv->is_6143) in get_last_sample_6143()
1227 struct ni_private *devpriv = dev->private; in ni_handle_eos() local
1229 if (devpriv->aimode == AIMODE_SCAN) { in ni_handle_eos()
1246 if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS) in ni_handle_eos()
1254 struct ni_private *devpriv = dev->private; in handle_gpct_interrupt() local
1259 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index], in handle_gpct_interrupt()
1399 struct ni_private *devpriv = dev->private; in ni_ai_munge() local
1419 larray[i] += devpriv->ai_offset[chan_index]; in ni_ai_munge()
1421 array[i] += devpriv->ai_offset[chan_index]; in ni_ai_munge()
1431 struct ni_private *devpriv = dev->private; in ni_ai_setup_MITE_dma() local
1443 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_ai_setup_MITE_dma()
1444 if (!devpriv->ai_mite_chan) { in ni_ai_setup_MITE_dma()
1445 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_ai_setup_MITE_dma()
1449 if (devpriv->is_611x || devpriv->is_6143) in ni_ai_setup_MITE_dma()
1450 mite_prep_dma(devpriv->ai_mite_chan, 32, 16); in ni_ai_setup_MITE_dma()
1451 else if (devpriv->is_628x) in ni_ai_setup_MITE_dma()
1452 mite_prep_dma(devpriv->ai_mite_chan, 32, 32); in ni_ai_setup_MITE_dma()
1454 mite_prep_dma(devpriv->ai_mite_chan, 16, 16); in ni_ai_setup_MITE_dma()
1457 mite_dma_arm(devpriv->ai_mite_chan); in ni_ai_setup_MITE_dma()
1458 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_ai_setup_MITE_dma()
1465 struct ni_private *devpriv = dev->private; in ni_ao_setup_MITE_dma() local
1477 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_ao_setup_MITE_dma()
1478 if (devpriv->ao_mite_chan) { in ni_ao_setup_MITE_dma()
1479 if (devpriv->is_611x || devpriv->is_6713) { in ni_ao_setup_MITE_dma()
1480 mite_prep_dma(devpriv->ao_mite_chan, 32, 32); in ni_ao_setup_MITE_dma()
1487 mite_prep_dma(devpriv->ao_mite_chan, 16, 32); in ni_ao_setup_MITE_dma()
1489 mite_dma_arm(devpriv->ao_mite_chan); in ni_ao_setup_MITE_dma()
1493 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_ao_setup_MITE_dma()
1507 struct ni_private *devpriv = dev->private; in ni_ai_reset() local
1520 if (!devpriv->is_6143) in ni_ai_reset()
1540 if (devpriv->is_611x) { in ni_ai_reset()
1542 } else if (devpriv->is_6143) { in ni_ai_reset()
1546 if (devpriv->is_622x) in ni_ai_reset()
1610 struct ni_private *devpriv = dev->private; in ni_m_series_load_channelgain_list() local
1628 devpriv->ai_calib_source; in ni_m_series_load_channelgain_list()
1646 devpriv->ai_offset[i] = 0; in ni_m_series_load_channelgain_list()
1708 struct ni_private *devpriv = dev->private; in ni_load_channelgain_list() local
1715 if (devpriv->is_m_series) { in ni_load_channelgain_list()
1719 if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) { in ni_load_channelgain_list()
1720 if (devpriv->changain_state && in ni_load_channelgain_list()
1721 devpriv->changain_spec == list[0]) { in ni_load_channelgain_list()
1725 devpriv->changain_state = 1; in ni_load_channelgain_list()
1726 devpriv->changain_spec = list[0]; in ni_load_channelgain_list()
1728 devpriv->changain_state = 0; in ni_load_channelgain_list()
1734 if (devpriv->is_6143) { in ni_load_channelgain_list()
1736 !devpriv->ai_calib_source_enabled) { in ni_load_channelgain_list()
1738 ni_writew(dev, devpriv->ai_calib_source | in ni_load_channelgain_list()
1741 ni_writew(dev, devpriv->ai_calib_source, in ni_load_channelgain_list()
1743 devpriv->ai_calib_source_enabled = 1; in ni_load_channelgain_list()
1747 devpriv->ai_calib_source_enabled) { in ni_load_channelgain_list()
1749 ni_writew(dev, devpriv->ai_calib_source | in ni_load_channelgain_list()
1752 ni_writew(dev, devpriv->ai_calib_source, in ni_load_channelgain_list()
1754 devpriv->ai_calib_source_enabled = 0; in ni_load_channelgain_list()
1761 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE)) in ni_load_channelgain_list()
1762 chan = devpriv->ai_calib_source; in ni_load_channelgain_list()
1771 if (devpriv->is_611x) in ni_load_channelgain_list()
1772 devpriv->ai_offset[i] = offset; in ni_load_channelgain_list()
1774 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset; in ni_load_channelgain_list()
1778 if (devpriv->is_611x) in ni_load_channelgain_list()
1782 if (devpriv->is_611x) in ni_load_channelgain_list()
1784 else if (devpriv->is_6143) in ni_load_channelgain_list()
1804 if (!devpriv->is_6143) { in ni_load_channelgain_list()
1817 if (!devpriv->is_611x && !devpriv->is_6143) in ni_load_channelgain_list()
1826 struct ni_private *devpriv = dev->private; in ni_ai_insn_read() local
1836 signbits = devpriv->ai_offset[0]; in ni_ai_insn_read()
1837 if (devpriv->is_611x) { in ni_ai_insn_read()
1871 } else if (devpriv->is_6143) { in ni_ai_insn_read()
1912 if (devpriv->is_m_series) { in ni_ai_insn_read()
1929 struct ni_private *devpriv = dev->private; in ni_ns_to_timer() local
1935 divider = DIV_ROUND_CLOSEST(nanosec, devpriv->clock_ns); in ni_ns_to_timer()
1938 divider = (nanosec) / devpriv->clock_ns; in ni_ns_to_timer()
1941 divider = DIV_ROUND_UP(nanosec, devpriv->clock_ns); in ni_ns_to_timer()
1949 struct ni_private *devpriv = dev->private; in ni_timer_to_ns() local
1951 return devpriv->clock_ns * (timer + 1); in ni_timer_to_ns()
1992 struct ni_private *devpriv = dev->private; in ni_min_ai_scan_period_ns() local
1995 if (devpriv->is_611x || devpriv->is_6143) in ni_min_ai_scan_period_ns()
2006 struct ni_private *devpriv = dev->private; in ni_ai_cmdtest() local
2018 if (devpriv->is_611x || devpriv->is_6143) in ni_ai_cmdtest()
2050 &devpriv->routing_tables, 1); in ni_ai_cmdtest()
2058 devpriv->clock_ns * in ni_ai_cmdtest()
2064 &devpriv->routing_tables, 1); in ni_ai_cmdtest()
2070 if (devpriv->is_611x || devpriv->is_6143) { in ni_ai_cmdtest()
2077 devpriv->clock_ns * in ni_ai_cmdtest()
2084 &devpriv->routing_tables, 1); in ni_ai_cmdtest()
2095 if (devpriv->is_611x) in ni_ai_cmdtest()
2120 if (!devpriv->is_611x && !devpriv->is_6143) { in ni_ai_cmdtest()
2149 struct ni_private *devpriv = dev->private; in ni_ai_inttrig() local
2155 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2, in ni_ai_inttrig()
2164 struct ni_private *devpriv = dev->private; in ni_ai_cmd() local
2189 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA; in ni_ai_cmd()
2190 ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG); in ni_ai_cmd()
2204 &devpriv->routing_tables, 1)); in ni_ai_cmd()
2219 if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) { in ni_ai_cmd()
2230 devpriv->ai_cmd2 = 0; in ni_ai_cmd()
2235 if (devpriv->is_611x) { in ni_ai_cmd()
2250 devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS; in ni_ai_cmd()
2319 &devpriv->routing_tables, 1)); in ni_ai_cmd()
2351 &devpriv->routing_tables, 1)); in ni_ai_cmd()
2373 (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) { in ni_ai_cmd()
2375 devpriv->aimode = AIMODE_SCAN; in ni_ai_cmd()
2377 devpriv->aimode = AIMODE_HALF_FULL; in ni_ai_cmd()
2380 switch (devpriv->aimode) { in ni_ai_cmd()
2452 devpriv->ai_cmd2, in ni_ai_cmd()
2469 struct ni_private *devpriv = dev->private; in ni_ai_insn_config() local
2476 if (devpriv->is_m_series) { in ni_ai_insn_config()
2479 devpriv->ai_calib_source = data[1]; in ni_ai_insn_config()
2480 } else if (devpriv->is_6143) { in ni_ai_insn_config()
2485 devpriv->ai_calib_source = calib_source; in ni_ai_insn_config()
2496 devpriv->ai_calib_source = calib_source; in ni_ai_insn_config()
2497 if (devpriv->is_611x) { in ni_ai_insn_config()
2507 if (devpriv->is_611x || devpriv->is_6143) in ni_ai_insn_config()
2557 struct ni_private *devpriv = dev->private; in ni_m_series_ao_config_chanlist() local
2566 devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED; in ni_m_series_ao_config_chanlist()
2567 ni_writeb(dev, devpriv->ao_conf[i], in ni_m_series_ao_config_chanlist()
2619 devpriv->ao_conf[chan] = conf; in ni_m_series_ao_config_chanlist()
2630 struct ni_private *devpriv = dev->private; in ni_old_ao_config_chanlist() local
2661 devpriv->ao_conf[chan] = conf; in ni_old_ao_config_chanlist()
2671 struct ni_private *devpriv = dev->private; in ni_ao_config_chanlist() local
2673 if (devpriv->is_m_series) in ni_ao_config_chanlist()
2685 struct ni_private *devpriv = dev->private; in ni_ao_insn_write() local
2691 if (devpriv->is_6xxx) { in ni_ao_insn_write()
2695 } else if (devpriv->is_m_series) { in ni_ao_insn_write()
2708 if (devpriv->is_6xxx) { in ni_ao_insn_write()
2716 } else if (devpriv->is_m_series) { in ni_ao_insn_write()
2750 struct ni_private *devpriv = dev->private; in ni_ao_arm() local
2760 if (!devpriv->ao_needs_arming) { in ni_ao_arm()
2766 devpriv->ao_needs_arming = 0; in ni_ao_arm()
2773 if (devpriv->is_6xxx) in ni_ao_arm()
2789 ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE, in ni_ao_arm()
2791 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG); in ni_ao_arm()
2815 devpriv->ao_cmd1, in ni_ao_arm()
2826 struct ni_private *devpriv = dev->private; in ni_ao_insn_config() local
2836 if (devpriv->mite) in ni_ao_insn_config()
2837 data[2] += devpriv->mite->fifo_size; in ni_ao_insn_config()
2865 struct ni_private *devpriv = dev->private; in ni_ao_inttrig() local
2886 if (devpriv->ao_needs_arming) { in ni_ao_inttrig()
2893 ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2, in ni_ao_inttrig()
2945 if (devpriv->is_m_series) in ni_ao_cmd_personalize()
2956 struct ni_private *devpriv = dev->private; in ni_ao_cmd_set_trigger() local
2963 devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS; in ni_ao_cmd_set_trigger()
2964 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE; in ni_ao_cmd_set_trigger()
2966 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS; in ni_ao_cmd_set_trigger()
2967 devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE; in ni_ao_cmd_set_trigger()
2969 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG); in ni_ao_cmd_set_trigger()
2979 &devpriv->routing_tables, 1)); in ni_ao_cmd_set_trigger()
2994 devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN; in ni_ao_cmd_set_trigger()
2995 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG); in ni_ao_cmd_set_trigger()
3003 struct ni_private *devpriv = dev->private; in ni_ao_cmd_set_counters() local
3014 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG); in ni_ao_cmd_set_counters()
3018 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC; in ni_ao_cmd_set_counters()
3019 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG); in ni_ao_cmd_set_counters()
3033 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC; in ni_ao_cmd_set_counters()
3034 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG); in ni_ao_cmd_set_counters()
3048 if (devpriv->is_m_series) { in ni_ao_cmd_set_counters()
3079 struct ni_private *devpriv = dev->private; in ni_ao_cmd_set_update() local
3087 devpriv->ao_mode1 &= ~(NISTC_AO_MODE1_UI_SRC_MASK | in ni_ao_cmd_set_update()
3095 devpriv->ao_cmd2 &= ~NISTC_AO_CMD2_BC_GATE_ENA; in ni_ao_cmd_set_update()
3138 devpriv->ao_cmd2 |= NISTC_AO_CMD2_BC_GATE_ENA; in ni_ao_cmd_set_update()
3139 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC( in ni_ao_cmd_set_update()
3143 &devpriv->routing_tables)); in ni_ao_cmd_set_update()
3145 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY; in ni_ao_cmd_set_update()
3148 ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG); in ni_ao_cmd_set_update()
3149 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG); in ni_ao_cmd_set_update()
3150 devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) | in ni_ao_cmd_set_update()
3152 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG); in ni_ao_cmd_set_update()
3155 devpriv->ao_cmd1 |= NISTC_AO_CMD1_DAC1_UPDATE_MODE | in ni_ao_cmd_set_update()
3158 ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG); in ni_ao_cmd_set_update()
3166 struct ni_private *devpriv = dev->private; in ni_ao_cmd_set_channels() local
3172 if (devpriv->is_6xxx) { in ni_ao_cmd_set_channels()
3188 devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN; in ni_ao_cmd_set_channels()
3193 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN; in ni_ao_cmd_set_channels()
3195 if (devpriv->is_m_series | devpriv->is_6xxx) in ni_ao_cmd_set_channels()
3202 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG); in ni_ao_cmd_set_channels()
3211 struct ni_private *devpriv = dev->private; in ni_ao_cmd_set_stop_conditions() local
3215 devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR; in ni_ao_cmd_set_stop_conditions()
3216 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG); in ni_ao_cmd_set_stop_conditions()
3229 struct ni_private *devpriv = dev->private; in ni_ao_cmd_set_fifo_mode() local
3233 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK; in ni_ao_cmd_set_fifo_mode()
3235 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F; in ni_ao_cmd_set_fifo_mode()
3237 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF; in ni_ao_cmd_set_fifo_mode()
3240 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA; in ni_ao_cmd_set_fifo_mode()
3241 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG); in ni_ao_cmd_set_fifo_mode()
3263 struct ni_private *devpriv = dev->private; in ni_ao_cmd() local
3281 ni_cmd_set_mite_transfer(devpriv->ao_mite_ring, s, cmd, 0x00ffffff); in ni_ao_cmd()
3295 devpriv->ao_needs_arming = 1; in ni_ao_cmd()
3305 struct ni_private *devpriv = dev->private; in ni_ao_cmdtest() local
3341 &devpriv->routing_tables, 1); in ni_ao_cmdtest()
3349 devpriv->clock_ns * in ni_ao_cmdtest()
3354 &devpriv->routing_tables); in ni_ao_cmdtest()
3391 struct ni_private *devpriv = dev->private; in ni_ao_reset() local
3396 if (devpriv->is_m_series) in ni_ao_reset()
3411 devpriv->ao_cmd1 = 0; in ni_ao_reset()
3412 devpriv->ao_cmd2 = 0; in ni_ao_reset()
3413 devpriv->ao_mode1 = 0; in ni_ao_reset()
3414 devpriv->ao_mode2 = 0; in ni_ao_reset()
3415 if (devpriv->is_m_series) in ni_ao_reset()
3416 devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE; in ni_ao_reset()
3418 devpriv->ao_mode3 = 0; in ni_ao_reset()
3426 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG); in ni_ao_reset()
3438 if (devpriv->is_6xxx) { in ni_ao_reset()
3457 struct ni_private *devpriv = dev->private; in ni_dio_insn_config() local
3464 devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK; in ni_dio_insn_config()
3465 devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits); in ni_dio_insn_config()
3466 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); in ni_dio_insn_config()
3476 struct ni_private *devpriv = dev->private; in ni_dio_insn_bits() local
3480 devpriv->serial_interval_ns) in ni_dio_insn_bits()
3484 devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK; in ni_dio_insn_bits()
3485 devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state); in ni_dio_insn_bits()
3486 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG); in ni_dio_insn_bits()
3552 struct ni_private *devpriv = dev->private; in ni_cdio_cmdtest() local
3580 &devpriv->routing_tables); in ni_cdio_cmdtest()
3619 struct ni_private *devpriv = dev->private; in ni_cdo_inttrig() local
3630 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_cdo_inttrig()
3631 if (devpriv->cdo_mite_chan) { in ni_cdo_inttrig()
3632 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32); in ni_cdo_inttrig()
3633 mite_dma_arm(devpriv->cdo_mite_chan); in ni_cdo_inttrig()
3638 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_cdo_inttrig()
3667 struct ni_private *devpriv = dev->private; in ni_cdio_cmd() local
3683 &devpriv->routing_tables)); in ni_cdio_cmd()
3700 ni_cmd_set_mite_transfer(devpriv->cdo_mite_ring, s, cmd, in ni_cdio_cmd()
3727 struct ni_private *devpriv = dev->private; in handle_cdio_interrupt() local
3732 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in handle_cdio_interrupt()
3733 if (devpriv->cdo_mite_chan) in handle_cdio_interrupt()
3734 mite_ack_linkc(devpriv->cdo_mite_chan, s, true); in handle_cdio_interrupt()
3735 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in handle_cdio_interrupt()
3758 struct ni_private *devpriv = dev->private; in ni_serial_hw_readwrite8() local
3762 devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK; in ni_serial_hw_readwrite8()
3763 devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out); in ni_serial_hw_readwrite8()
3764 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG); in ni_serial_hw_readwrite8()
3772 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START; in ni_serial_hw_readwrite8()
3773 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); in ni_serial_hw_readwrite8()
3774 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START; in ni_serial_hw_readwrite8()
3780 udelay((devpriv->serial_interval_ns + 999) / 1000); in ni_serial_hw_readwrite8()
3793 udelay((devpriv->serial_interval_ns + 999) / 1000); in ni_serial_hw_readwrite8()
3799 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); in ni_serial_hw_readwrite8()
3809 struct ni_private *devpriv = dev->private; in ni_serial_sw_readwrite8() local
3813 udelay((devpriv->serial_interval_ns + 999) / 1000); in ni_serial_sw_readwrite8()
3821 devpriv->dio_output &= ~NISTC_DIO_SDOUT; in ni_serial_sw_readwrite8()
3823 devpriv->dio_output |= NISTC_DIO_SDOUT; in ni_serial_sw_readwrite8()
3824 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG); in ni_serial_sw_readwrite8()
3830 devpriv->dio_control |= NISTC_DIO_SDCLK; in ni_serial_sw_readwrite8()
3831 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); in ni_serial_sw_readwrite8()
3833 udelay((devpriv->serial_interval_ns + 999) / 2000); in ni_serial_sw_readwrite8()
3835 devpriv->dio_control &= ~NISTC_DIO_SDCLK; in ni_serial_sw_readwrite8()
3836 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); in ni_serial_sw_readwrite8()
3838 udelay((devpriv->serial_interval_ns + 999) / 2000); in ni_serial_sw_readwrite8()
3856 struct ni_private *devpriv = dev->private; in ni_serial_insn_config() local
3857 unsigned int clk_fout = devpriv->clock_and_fout; in ni_serial_insn_config()
3866 devpriv->serial_hw_mode = 1; in ni_serial_insn_config()
3867 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA; in ni_serial_insn_config()
3870 devpriv->serial_hw_mode = 0; in ni_serial_insn_config()
3871 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA | in ni_serial_insn_config()
3874 devpriv->serial_interval_ns = data[1]; in ni_serial_insn_config()
3880 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE; in ni_serial_insn_config()
3884 devpriv->serial_interval_ns = data[1]; in ni_serial_insn_config()
3886 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE; in ni_serial_insn_config()
3890 devpriv->serial_interval_ns = data[1]; in ni_serial_insn_config()
3892 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE; in ni_serial_insn_config()
3902 devpriv->serial_interval_ns = data[1]; in ni_serial_insn_config()
3904 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA | in ni_serial_insn_config()
3906 devpriv->serial_hw_mode = 0; in ni_serial_insn_config()
3908 devpriv->serial_interval_ns = data[1]; in ni_serial_insn_config()
3910 devpriv->clock_and_fout = clk_fout; in ni_serial_insn_config()
3912 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); in ni_serial_insn_config()
3913 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG); in ni_serial_insn_config()
3918 if (devpriv->serial_interval_ns == 0) in ni_serial_insn_config()
3923 if (devpriv->serial_hw_mode) { in ni_serial_insn_config()
3926 } else if (devpriv->serial_interval_ns > 0) { in ni_serial_insn_config()
4089 struct ni_private *devpriv = dev->private; in ni_freq_out_insn_read() local
4090 unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout); in ni_freq_out_insn_read()
4104 struct ni_private *devpriv = dev->private; in ni_freq_out_insn_write() local
4109 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA; in ni_freq_out_insn_write()
4110 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG); in ni_freq_out_insn_write()
4111 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK; in ni_freq_out_insn_write()
4114 devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val); in ni_freq_out_insn_write()
4116 devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA; in ni_freq_out_insn_write()
4117 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG); in ni_freq_out_insn_write()
4127 struct ni_private *devpriv = dev->private; in ni_freq_out_insn_config() local
4133 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL; in ni_freq_out_insn_config()
4136 devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL; in ni_freq_out_insn_config()
4141 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG); in ni_freq_out_insn_config()
4144 if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) { in ni_freq_out_insn_config()
4171 struct ni_private *devpriv = dev->private; in ni_get_pwm_config() local
4173 data[1] = devpriv->pwm_up_count * devpriv->clock_ns; in ni_get_pwm_config()
4174 data[2] = devpriv->pwm_down_count * devpriv->clock_ns; in ni_get_pwm_config()
4183 struct ni_private *devpriv = dev->private; in ni_m_series_pwm_config() local
4191 devpriv->clock_ns); in ni_m_series_pwm_config()
4194 up_count = data[2] / devpriv->clock_ns; in ni_m_series_pwm_config()
4198 DIV_ROUND_UP(data[2], devpriv->clock_ns); in ni_m_series_pwm_config()
4206 devpriv->clock_ns); in ni_m_series_pwm_config()
4209 down_count = data[4] / devpriv->clock_ns; in ni_m_series_pwm_config()
4213 DIV_ROUND_UP(data[4], devpriv->clock_ns); in ni_m_series_pwm_config()
4218 if (up_count * devpriv->clock_ns != data[2] || in ni_m_series_pwm_config()
4219 down_count * devpriv->clock_ns != data[4]) { in ni_m_series_pwm_config()
4220 data[2] = up_count * devpriv->clock_ns; in ni_m_series_pwm_config()
4221 data[4] = down_count * devpriv->clock_ns; in ni_m_series_pwm_config()
4227 devpriv->pwm_up_count = up_count; in ni_m_series_pwm_config()
4228 devpriv->pwm_down_count = down_count; in ni_m_series_pwm_config()
4243 struct ni_private *devpriv = dev->private; in ni_6143_pwm_config() local
4251 devpriv->clock_ns); in ni_6143_pwm_config()
4254 up_count = data[2] / devpriv->clock_ns; in ni_6143_pwm_config()
4258 DIV_ROUND_UP(data[2], devpriv->clock_ns); in ni_6143_pwm_config()
4266 devpriv->clock_ns); in ni_6143_pwm_config()
4269 down_count = data[4] / devpriv->clock_ns; in ni_6143_pwm_config()
4273 DIV_ROUND_UP(data[4], devpriv->clock_ns); in ni_6143_pwm_config()
4278 if (up_count * devpriv->clock_ns != data[2] || in ni_6143_pwm_config()
4279 down_count * devpriv->clock_ns != data[4]) { in ni_6143_pwm_config()
4280 data[2] = up_count * devpriv->clock_ns; in ni_6143_pwm_config()
4281 data[4] = down_count * devpriv->clock_ns; in ni_6143_pwm_config()
4285 devpriv->pwm_up_count = up_count; in ni_6143_pwm_config()
4287 devpriv->pwm_down_count = down_count; in ni_6143_pwm_config()
4364 struct ni_private *devpriv = dev->private; in ni_write_caldac() local
4370 if (devpriv->caldacs[addr] == val) in ni_write_caldac()
4372 devpriv->caldacs[addr] = val; in ni_write_caldac()
4421 struct ni_private *devpriv = dev->private; in ni_calib_insn_read() local
4425 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)]; in ni_calib_insn_read()
4433 struct ni_private *devpriv = dev->private; in caldac_setup() local
4458 unsigned int *maxdata_list = devpriv->caldac_maxdata_list; in caldac_setup()
4536 struct ni_private *devpriv = dev->private; in ni_m_series_eeprom_insn_read() local
4540 data[i] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)]; in ni_m_series_eeprom_insn_read()
4589 struct ni_private *devpriv = dev->private; in ni_m_series_get_pfi_routing() local
4593 devpriv->pfi_output_select_reg[array_offset]); in ni_m_series_get_pfi_routing()
4599 struct ni_private *devpriv = dev->private; in ni_m_series_set_pfi_routing() local
4601 unsigned short val = devpriv->pfi_output_select_reg[index]; in ni_m_series_set_pfi_routing()
4609 devpriv->pfi_output_select_reg[index] = val; in ni_m_series_set_pfi_routing()
4617 struct ni_private *devpriv = dev->private; in ni_get_pfi_routing() local
4623 return (devpriv->is_m_series) in ni_get_pfi_routing()
4632 struct ni_private *devpriv = dev->private; in ni_set_pfi_routing() local
4638 return (devpriv->is_m_series) in ni_set_pfi_routing()
4647 struct ni_private *devpriv = dev->private; in ni_config_pfi_filter() local
4650 if (!devpriv->is_m_series) in ni_config_pfi_filter()
4678 struct ni_private *devpriv = dev->private; in ni_get_pfi_direction() local
4684 return devpriv->io_bidirection_pin_reg & (1 << chan) ? in ni_get_pfi_direction()
4726 struct ni_private *devpriv = dev->private; in ni_pfi_insn_bits() local
4728 if (!devpriv->is_m_series) in ni_pfi_insn_bits()
4928 struct ni_private *devpriv = dev->private; in ni_mseries_set_pll_master_clock() local
4951 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK; in ni_mseries_set_pll_master_clock()
4952 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, in ni_mseries_set_pll_master_clock()
4955 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL | in ni_mseries_set_pll_master_clock()
4957 devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK; in ni_mseries_set_pll_master_clock()
4960 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR; in ni_mseries_set_pll_master_clock()
4964 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10; in ni_mseries_set_pll_master_clock()
4969 devpriv->clock_and_fout2 |= in ni_mseries_set_pll_master_clock()
4981 &devpriv->clock_ns); in ni_mseries_set_pll_master_clock()
4988 ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG); in ni_mseries_set_pll_master_clock()
4993 devpriv->clock_source = source; in ni_mseries_set_pll_master_clock()
5012 struct ni_private *devpriv = dev->private; in ni_set_master_clock() local
5015 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK; in ni_set_master_clock()
5016 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, in ni_set_master_clock()
5018 devpriv->clock_ns = TIMEBASE_1_NS; in ni_set_master_clock()
5019 if (devpriv->is_m_series) { in ni_set_master_clock()
5020 devpriv->clock_and_fout2 &= in ni_set_master_clock()
5023 ni_writew(dev, devpriv->clock_and_fout2, in ni_set_master_clock()
5027 devpriv->clock_source = source; in ni_set_master_clock()
5029 if (devpriv->is_m_series) { in ni_set_master_clock()
5034 devpriv->rtsi_trig_direction_reg |= in ni_set_master_clock()
5037 devpriv->rtsi_trig_direction_reg, in ni_set_master_clock()
5044 devpriv->clock_ns = period_ns; in ni_set_master_clock()
5045 devpriv->clock_source = source; in ni_set_master_clock()
5057 struct ni_private *devpriv = dev->private; in ni_valid_rtsi_output_source() local
5059 if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) { in ni_valid_rtsi_output_source()
5086 return (devpriv->is_m_series) ? 1 : 0; in ni_valid_rtsi_output_source()
5095 struct ni_private *devpriv = dev->private; in ni_set_rtsi_routing() local
5104 devpriv->rtsi_trig_a_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan); in ni_set_rtsi_routing()
5105 devpriv->rtsi_trig_a_output_reg |= NISTC_RTSI_TRIG(chan, src); in ni_set_rtsi_routing()
5106 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg, in ni_set_rtsi_routing()
5108 } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) { in ni_set_rtsi_routing()
5109 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan); in ni_set_rtsi_routing()
5110 devpriv->rtsi_trig_b_output_reg |= NISTC_RTSI_TRIG(chan, src); in ni_set_rtsi_routing()
5111 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg, in ni_set_rtsi_routing()
5127 struct ni_private *devpriv = dev->private; in ni_get_rtsi_routing() local
5135 devpriv->rtsi_trig_a_output_reg); in ni_get_rtsi_routing()
5136 } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) { in ni_get_rtsi_routing()
5138 devpriv->rtsi_trig_b_output_reg); in ni_get_rtsi_routing()
5150 struct ni_private *devpriv = dev->private; in ni_set_rtsi_direction() local
5151 unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series); in ni_set_rtsi_direction()
5159 devpriv->rtsi_trig_direction_reg |= in ni_set_rtsi_direction()
5160 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series); in ni_set_rtsi_direction()
5162 devpriv->rtsi_trig_direction_reg |= in ni_set_rtsi_direction()
5167 devpriv->rtsi_trig_direction_reg &= in ni_set_rtsi_direction()
5168 ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series); in ni_set_rtsi_direction()
5170 devpriv->rtsi_trig_direction_reg &= in ni_set_rtsi_direction()
5174 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, in ni_set_rtsi_direction()
5180 struct ni_private *devpriv = dev->private; in ni_get_rtsi_direction() local
5181 unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series); in ni_get_rtsi_direction()
5188 return (devpriv->rtsi_trig_direction_reg & in ni_get_rtsi_direction()
5189 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series)) in ni_get_rtsi_direction()
5192 return (devpriv->rtsi_trig_direction_reg & in ni_get_rtsi_direction()
5204 struct ni_private *devpriv = dev->private; in ni_rtsi_insn_config() local
5223 data[1] = devpriv->clock_source; in ni_rtsi_insn_config()
5224 data[2] = devpriv->clock_ns; in ni_rtsi_insn_config()
5276 struct ni_private *devpriv = dev->private; in set_rgout0_reg() local
5278 if (devpriv->is_m_series) { in set_rgout0_reg()
5279 devpriv->rtsi_trig_direction_reg &= in set_rgout0_reg()
5281 devpriv->rtsi_trig_direction_reg |= in set_rgout0_reg()
5284 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, in set_rgout0_reg()
5287 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIGB_SUB_SEL1; in set_rgout0_reg()
5288 devpriv->rtsi_trig_b_output_reg |= in set_rgout0_reg()
5291 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg, in set_rgout0_reg()
5298 struct ni_private *devpriv = dev->private; in get_rgout0_reg() local
5301 if (devpriv->is_m_series) in get_rgout0_reg()
5302 reg = (devpriv->rtsi_trig_direction_reg & in get_rgout0_reg()
5306 reg = (devpriv->rtsi_trig_b_output_reg & in get_rgout0_reg()
5314 struct ni_private *devpriv = dev->private; in get_rgout0_src() local
5317 return ni_find_route_source(reg, NI_RGOUT0, &devpriv->routing_tables); in get_rgout0_src()
5332 struct ni_private *devpriv = dev->private; in incr_rgout0_src_use() local
5334 &devpriv->routing_tables); in incr_rgout0_src_use()
5339 if (devpriv->rgout0_usage > 0 && get_rgout0_reg(dev) != reg) in incr_rgout0_src_use()
5342 ++devpriv->rgout0_usage; in incr_rgout0_src_use()
5358 struct ni_private *devpriv = dev->private; in decr_rgout0_src_use() local
5360 &devpriv->routing_tables); in decr_rgout0_src_use()
5362 if (devpriv->rgout0_usage > 0 && get_rgout0_reg(dev) == reg) { in decr_rgout0_src_use()
5363 --devpriv->rgout0_usage; in decr_rgout0_src_use()
5364 if (!devpriv->rgout0_usage) in decr_rgout0_src_use()
5379 struct ni_private *devpriv = dev->private; in set_ith_rtsi_brd_reg() local
5384 if (devpriv->is_m_series) in set_ith_rtsi_brd_reg()
5390 devpriv->rtsi_shared_mux_reg &= ~(reg_i_mask << reg_i_shift); in set_ith_rtsi_brd_reg()
5392 devpriv->rtsi_shared_mux_reg |= (reg & reg_i_mask) << reg_i_shift; in set_ith_rtsi_brd_reg()
5394 ni_stc_writew(dev, devpriv->rtsi_shared_mux_reg, NISTC_RTSI_BOARD_REG); in set_ith_rtsi_brd_reg()
5399 struct ni_private *devpriv = dev->private; in get_ith_rtsi_brd_reg() local
5404 if (devpriv->is_m_series) in get_ith_rtsi_brd_reg()
5409 return (devpriv->rtsi_shared_mux_reg >> reg_i_shift) & reg_i_mask; in get_ith_rtsi_brd_reg()
5414 struct ni_private *devpriv = dev->private; in get_rtsi_brd_src() local
5430 return ni_find_route_source(reg, brd, &devpriv->routing_tables); in get_rtsi_brd_src()
5443 struct ni_private *devpriv = dev->private; in incr_rtsi_brd_src_use() local
5452 &devpriv->routing_tables); in incr_rtsi_brd_src_use()
5457 if (!devpriv->rtsi_shared_mux_usage[i]) { in incr_rtsi_brd_src_use()
5486 ++devpriv->rtsi_shared_mux_usage[i]; in incr_rtsi_brd_src_use()
5501 struct ni_private *devpriv = dev->private; in decr_rtsi_brd_src_use() local
5503 &devpriv->routing_tables); in decr_rtsi_brd_src_use()
5506 if (devpriv->rtsi_shared_mux_usage[i] > 0 && in decr_rtsi_brd_src_use()
5508 --devpriv->rtsi_shared_mux_usage[i]; in decr_rtsi_brd_src_use()
5509 if (!devpriv->rtsi_shared_mux_usage[i]) in decr_rtsi_brd_src_use()
5519 struct ni_private *devpriv = dev->private; in ni_rtsi_init() local
5529 devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ; in ni_rtsi_init()
5549 devpriv->rtsi_shared_mux_reg = 0; in ni_rtsi_init()
5552 memset(devpriv->rtsi_shared_mux_usage, 0, in ni_rtsi_init()
5553 sizeof(devpriv->rtsi_shared_mux_usage)); in ni_rtsi_init()
5556 devpriv->rgout0_usage = 0; in ni_rtsi_init()
5564 struct ni_private *devpriv = dev->private; in ni_get_gout_routing() local
5565 unsigned int reg = devpriv->an_trig_etc_reg; in ni_get_gout_routing()
5585 struct ni_private *devpriv = dev->private; in ni_disable_gout_routing() local
5589 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_0_ENA; in ni_disable_gout_routing()
5592 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_1_ENA; in ni_disable_gout_routing()
5598 ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG); in ni_disable_gout_routing()
5606 struct ni_private *devpriv = dev->private; in ni_set_gout_routing() local
5611 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_0_SEL(-1); in ni_set_gout_routing()
5613 devpriv->an_trig_etc_reg |= NISTC_ATRIG_ETC_GPFO_0_ENA in ni_set_gout_routing()
5618 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_1_SEL; in ni_set_gout_routing()
5621 devpriv->an_trig_etc_reg |= NISTC_ATRIG_ETC_GPFO_1_ENA | src; in ni_set_gout_routing()
5627 ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG); in ni_set_gout_routing()
5641 struct ni_private *devpriv = dev->private; in get_output_select_source() local
5673 reg = ni_tio_get_routing(devpriv->counter_dev, dest); in get_output_select_source()
5681 &devpriv->routing_tables); in get_output_select_source()
5695 struct ni_private *devpriv = dev->private; in test_route() local
5697 &devpriv->routing_tables); in test_route()
5710 struct ni_private *devpriv = dev->private; in connect_route() local
5712 &devpriv->routing_tables); in connect_route()
5746 brd, dest, &devpriv->routing_tables); in connect_route()
5767 ni_tio_set_routing(devpriv->counter_dev, dest, in connect_route()
5778 struct ni_private *devpriv = dev->private; in disconnect_route() local
5780 &devpriv->routing_tables); in disconnect_route()
5804 &devpriv->routing_tables); in disconnect_route()
5828 ni_tio_unset_routing(devpriv->counter_dev, dest); in disconnect_route()
5897 struct ni_private *devpriv = dev->private; in ni_E_interrupt() local
5909 if (devpriv->mite) { in ni_E_interrupt()
5912 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too); in ni_E_interrupt()
5913 if (s_ai && devpriv->ai_mite_chan) in ni_E_interrupt()
5914 mite_ack_linkc(devpriv->ai_mite_chan, s_ai, false); in ni_E_interrupt()
5915 if (s_ao && devpriv->ao_mite_chan) in ni_E_interrupt()
5916 mite_ack_linkc(devpriv->ao_mite_chan, s_ao, false); in ni_E_interrupt()
5917 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too); in ni_E_interrupt()
5937 if (devpriv->is_m_series) in ni_E_interrupt()
5947 struct ni_private *devpriv; in ni_alloc_private() local
5949 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); in ni_alloc_private()
5950 if (!devpriv) in ni_alloc_private()
5953 spin_lock_init(&devpriv->window_lock); in ni_alloc_private()
5954 spin_lock_init(&devpriv->soft_reg_copy_lock); in ni_alloc_private()
5955 spin_lock_init(&devpriv->mite_channel_lock); in ni_alloc_private()
5964 struct ni_private *devpriv = dev->private; in _ni_get_valid_routes() local
5966 return ni_get_valid_routes(&devpriv->routing_tables, n_pairs, in _ni_get_valid_routes()
5974 struct ni_private *devpriv = dev->private; in ni_E_init() local
5978 const char *dev_family = devpriv->is_m_series ? "ni_mseries" in ni_E_init()
5984 &devpriv->routing_tables) < 0) { in ni_E_init()
6004 devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 | in ni_E_init()
6008 if (!devpriv->is_6xxx) { in ni_E_init()
6010 devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 | in ni_E_init()
6013 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG); in ni_E_init()
6024 if (!devpriv->is_611x) in ni_E_init()
6028 if (devpriv->is_m_series) in ni_E_init()
6045 if (devpriv->mite) in ni_E_init()
6060 if (devpriv->is_m_series) in ni_E_init()
6076 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) { in ni_E_init()
6083 if (!devpriv->is_m_series) in ni_E_init()
6086 if (devpriv->mite) in ni_E_init()
6090 if (devpriv->is_67xx) in ni_E_init()
6106 if (devpriv->is_m_series) { in ni_E_init()
6133 devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits); in ni_E_init()
6134 ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); in ni_E_init()
6158 if (devpriv->is_m_series) { in ni_E_init()
6163 } else if (devpriv->is_6143) { in ni_E_init()
6180 if (devpriv->is_m_series) { in ni_E_init()
6192 if (devpriv->is_m_series) { in ni_E_init()
6199 ni_writew(dev, devpriv->pfi_output_select_reg[i], in ni_E_init()
6212 if (devpriv->is_67xx) { in ni_E_init()
6233 devpriv->serial_interval_ns = 0; in ni_E_init()
6234 devpriv->serial_hw_mode = 0; in ni_E_init()
6247 devpriv->counter_dev = ni_gpct_device_construct(dev, in ni_E_init()
6250 (devpriv->is_m_series) in ni_E_init()
6255 &devpriv->routing_tables); in ni_E_init()
6256 if (!devpriv->counter_dev) in ni_E_init()
6261 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i]; in ni_E_init()
6270 s->maxdata = (devpriv->is_m_series) ? 0xffffffff in ni_E_init()
6276 if (dev->irq && devpriv->mite) { in ni_E_init()
6315 ni_writeb(dev, devpriv->ai_ao_select_reg, NI_E_DMA_AI_AO_SEL_REG); in ni_E_init()
6316 ni_writeb(dev, devpriv->g0_g1_select_reg, NI_E_DMA_G0_G1_SEL_REG); in ni_E_init()
6318 if (devpriv->is_6xxx) { in ni_E_init()
6320 } else if (devpriv->is_m_series) { in ni_E_init()
6337 struct ni_private *devpriv = dev->private; in mio_common_detach() local
6339 if (devpriv) in mio_common_detach()
6340 ni_gpct_device_destroy(devpriv->counter_dev); in mio_common_detach()