116 	switch (pvt->fam) {  in amd64_read_dct_pci_cfg()
219 	} else if (pvt->fam == 0x15 && pvt->model == 0x60) {  in __set_scrub_rate()
239 	if (pvt->fam == 0xf)  in set_scrub_rate()
242 	if (pvt->fam == 0x15) {  in set_scrub_rate()
268 	} else if (pvt->fam == 0x15) {  in get_scrub_rate()
391 	if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) {  in get_cs_base_and_mask()
402 	} else if (pvt->fam == 0x16 ||  in get_cs_base_and_mask()
403 		  (pvt->fam == 0x15 && pvt->model >= 0x30)) {  in get_cs_base_and_mask()
424 		if (pvt->fam == 0x15)  in get_cs_base_and_mask()
509 	if (pvt->fam == 0xf && pvt->ext_model < K8_REV_E) {  in get_dram_hole_info()
516 	if (pvt->fam >= 0x10 && !dhar_mem_hoist_valid(pvt)) {  in get_dram_hole_info()
548 	*hole_offset = (pvt->fam > 0xf) ? f10_dhar_offset(pvt)  in get_dram_hole_info()
827 	if (pvt->fam >= 0x10 && pvt->fam <= 0x16)  in inj_is_visible()
1019 		bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F)  in determine_edac_cap()
1053 	if (pvt->fam == 0x10)  in debug_dump_dramcfg_low()
1188 		 (pvt->fam == 0xf) ? k8_dhar_offset(pvt)  in __dump_misc_regs()
1194 	if (pvt->fam == 0xf)  in __dump_misc_regs()
1222 	if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) {  in prep_chip_selects()
1225 	} else if (pvt->fam == 0x15 && pvt->model == 0x30) {  in prep_chip_selects()
1228 	} else if (pvt->fam >= 0x17) {  in prep_chip_selects()
1315 		if (pvt->fam == 0xf)  in read_dct_base_mask()
1320 				 cs, *base1, (pvt->fam == 0x10) ? reg1  in read_dct_base_mask()
1334 		if (pvt->fam == 0xf)  in read_dct_base_mask()
1339 				 cs, *mask1, (pvt->fam == 0x10) ? reg1  in read_dct_base_mask()
1358 	switch (pvt->fam) {  in determine_memory_type()
1404 		WARN(1, KERN_ERR "%s: Family??? 0x%x\n", __func__, pvt->fam);  in determine_memory_type()
1446 	if (pvt->fam == 0xf) {  in get_error_address()
1456 	if (pvt->fam == 0x15) {  in get_error_address()
1524 	if (pvt->fam == 0xf)  in read_dram_base_limit_regs()
1534 	if (pvt->fam != 0x15)  in read_dram_base_limit_regs()
1695 	if (pvt->fam == 0x10 && (pvt->dclr0 & WIDTH_128))  in f1x_early_channel_count()
1936 	if (pvt->fam == 0xf)  in read_dram_ctl_register()
2149 			if (pvt->fam == 0x15 && pvt->model >= 0x30) {  in f1x_lookup_addr_in_dct()
2171 	if (pvt->fam == 0x10) {  in f1x_swap_interleaved_region()
2410 		if (pvt->fam == 0x15 && pvt->model >= 0x30)  in f1x_translate_sysaddr_to_cs()
2465 	if (pvt->fam == 0xf) {  in debug_display_dimm_sizes()
2473 	if (pvt->fam == 0x10) {  in debug_display_dimm_sizes()
3047 	} else if (pvt->fam >= 0x10) {  in determine_ecc_sym_sz()
3052 		if (pvt->fam != 0x16)  in determine_ecc_sym_sz()
3056 		if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25))  in determine_ecc_sym_sz()
3298 		if (pvt->fam != 0xf)  in init_csrows()
3316 		if (pvt->fam != 0xf && row_dct1) {  in init_csrows()
3621 	pvt->fam	= boot_cpu_data.x86;  in per_family_init()
3623 	switch (pvt->fam) {  in per_family_init()
3685 		if (pvt->fam == 0x18)  in per_family_init()
3722 	if (pvt->fam >= 0x17) {  in hw_info_get()
3878 		     (pvt->fam == 0xf ?  in probe_one_instance()