Lines Matching refs:m
13 static void (*decode_dram_ecc)(int node_id, struct mce *m);
643 static void decode_mc0_mce(struct mce *m) in decode_mc0_mce() argument
645 u16 ec = EC(m->status); in decode_mc0_mce()
646 u8 xec = XEC(m->status, xec_mask); in decode_mc0_mce()
753 static void decode_mc1_mce(struct mce *m) in decode_mc1_mce() argument
755 u16 ec = EC(m->status); in decode_mc1_mce()
756 u8 xec = XEC(m->status, xec_mask); in decode_mc1_mce()
764 bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58))); in decode_mc1_mce()
899 static void decode_mc2_mce(struct mce *m) in decode_mc2_mce() argument
901 u16 ec = EC(m->status); in decode_mc2_mce()
902 u8 xec = XEC(m->status, xec_mask); in decode_mc2_mce()
910 static void decode_mc3_mce(struct mce *m) in decode_mc3_mce() argument
912 u16 ec = EC(m->status); in decode_mc3_mce()
913 u8 xec = XEC(m->status, xec_mask); in decode_mc3_mce()
939 static void decode_mc4_mce(struct mce *m) in decode_mc4_mce() argument
941 unsigned int fam = x86_family(m->cpuid); in decode_mc4_mce()
942 int node_id = topology_die_id(m->extcpu); in decode_mc4_mce()
943 u16 ec = EC(m->status); in decode_mc4_mce()
944 u8 xec = XEC(m->status, 0x1f); in decode_mc4_mce()
961 decode_dram_ecc(node_id, m); in decode_mc4_mce()
997 static void decode_mc5_mce(struct mce *m) in decode_mc5_mce() argument
999 unsigned int fam = x86_family(m->cpuid); in decode_mc5_mce()
1000 u16 ec = EC(m->status); in decode_mc5_mce()
1001 u8 xec = XEC(m->status, xec_mask); in decode_mc5_mce()
1029 static void decode_mc6_mce(struct mce *m) in decode_mc6_mce() argument
1031 u8 xec = XEC(m->status, xec_mask); in decode_mc6_mce()
1046 static void decode_smca_error(struct mce *m) in decode_smca_error() argument
1051 u8 xec = XEC(m->status, xec_mask); in decode_smca_error()
1053 if (m->bank >= ARRAY_SIZE(smca_banks)) in decode_smca_error()
1056 hwid = smca_banks[m->bank].hwid; in decode_smca_error()
1063 pr_emerg(HW_ERR "Bank %d is reserved.\n", m->bank); in decode_smca_error()
1076 decode_dram_ecc(topology_die_id(m->extcpu), m); in decode_smca_error()
1103 static const char *decode_error_status(struct mce *m) in decode_error_status() argument
1105 if (m->status & MCI_STATUS_UC) { in decode_error_status()
1106 if (m->status & MCI_STATUS_PCC) in decode_error_status()
1108 if (m->mcgstatus & MCG_STATUS_RIPV) in decode_error_status()
1113 if (m->status & MCI_STATUS_DEFERRED) in decode_error_status()
1122 struct mce *m = (struct mce *)data; in amd_decode_mce() local
1123 unsigned int fam = x86_family(m->cpuid); in amd_decode_mce()
1126 if (m->kflags & MCE_HANDLED_CEC) in amd_decode_mce()
1129 pr_emerg(HW_ERR "%s\n", decode_error_status(m)); in amd_decode_mce()
1132 m->extcpu, in amd_decode_mce()
1133 fam, x86_model(m->cpuid), x86_stepping(m->cpuid), in amd_decode_mce()
1134 m->bank, in amd_decode_mce()
1135 ((m->status & MCI_STATUS_OVER) ? "Over" : "-"), in amd_decode_mce()
1136 ((m->status & MCI_STATUS_UC) ? "UE" : in amd_decode_mce()
1137 (m->status & MCI_STATUS_DEFERRED) ? "-" : "CE"), in amd_decode_mce()
1138 ((m->status & MCI_STATUS_MISCV) ? "MiscV" : "-"), in amd_decode_mce()
1139 ((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-"), in amd_decode_mce()
1140 ((m->status & MCI_STATUS_PCC) ? "PCC" : "-")); in amd_decode_mce()
1144 u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank); in amd_decode_mce()
1148 pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-")); in amd_decode_mce()
1150 pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-")); in amd_decode_mce()
1154 ecc = (m->status >> 45) & 0x3; in amd_decode_mce()
1159 pr_cont("|%s", (m->status & MCI_STATUS_DEFERRED ? "Deferred" : "-")); in amd_decode_mce()
1162 if (fam != 0x15 || m->bank != 4) in amd_decode_mce()
1163 pr_cont("|%s", (m->status & MCI_STATUS_POISON ? "Poison" : "-")); in amd_decode_mce()
1167 pr_cont("|%s", (m->status & MCI_STATUS_SCRUB ? "Scrub" : "-")); in amd_decode_mce()
1169 pr_cont("]: 0x%016llx\n", m->status); in amd_decode_mce()
1171 if (m->status & MCI_STATUS_ADDRV) in amd_decode_mce()
1172 pr_emerg(HW_ERR "Error Addr: 0x%016llx\n", m->addr); in amd_decode_mce()
1174 if (m->ppin) in amd_decode_mce()
1175 pr_emerg(HW_ERR "PPIN: 0x%016llx\n", m->ppin); in amd_decode_mce()
1178 pr_emerg(HW_ERR "IPID: 0x%016llx", m->ipid); in amd_decode_mce()
1180 if (m->status & MCI_STATUS_SYNDV) in amd_decode_mce()
1181 pr_cont(", Syndrome: 0x%016llx", m->synd); in amd_decode_mce()
1185 decode_smca_error(m); in amd_decode_mce()
1189 if (m->tsc) in amd_decode_mce()
1190 pr_emerg(HW_ERR "TSC: %llu\n", m->tsc); in amd_decode_mce()
1196 switch (m->bank) { in amd_decode_mce()
1198 decode_mc0_mce(m); in amd_decode_mce()
1202 decode_mc1_mce(m); in amd_decode_mce()
1206 decode_mc2_mce(m); in amd_decode_mce()
1210 decode_mc3_mce(m); in amd_decode_mce()
1214 decode_mc4_mce(m); in amd_decode_mce()
1218 decode_mc5_mce(m); in amd_decode_mce()
1222 decode_mc6_mce(m); in amd_decode_mce()
1230 amd_decode_err_code(m->status & 0xffff); in amd_decode_mce()
1232 m->kflags |= MCE_HANDLED_EDAC; in amd_decode_mce()