69 	adev->irq.ih.enabled = true;  in cz_ih_enable_interrupts()
91 	adev->irq.ih.enabled = false;  in cz_ih_disable_interrupts()
92 	adev->irq.ih.rptr = 0;  in cz_ih_disable_interrupts()
108 	struct amdgpu_ih_ring *ih = &adev->irq.ih;  in cz_ih_irq_init()  local
127 	WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);  in cz_ih_irq_init()
129 	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);  in cz_ih_irq_init()
138 	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));  in cz_ih_irq_init()
139 	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);  in cz_ih_irq_init()
191 			  struct amdgpu_ih_ring *ih)  in cz_ih_get_wptr()  argument
195 	wptr = le32_to_cpu(*ih->wptr_cpu);  in cz_ih_get_wptr()
213 		wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);  in cz_ih_get_wptr()
214 	ih->rptr = (wptr + 16) & ih->ptr_mask;  in cz_ih_get_wptr()
221 	return (wptr & ih->ptr_mask);  in cz_ih_get_wptr()
235 			    struct amdgpu_ih_ring *ih,  in cz_ih_decode_iv()  argument
239 	u32 ring_index = ih->rptr >> 2;  in cz_ih_decode_iv()
242 	dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);  in cz_ih_decode_iv()
243 	dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);  in cz_ih_decode_iv()
244 	dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);  in cz_ih_decode_iv()
245 	dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);  in cz_ih_decode_iv()
255 	ih->rptr += 16;  in cz_ih_decode_iv()
267 			   struct amdgpu_ih_ring *ih)  in cz_ih_set_rptr()  argument
269 	WREG32(mmIH_RB_RPTR, ih->rptr);  in cz_ih_set_rptr()
291 	r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);  in cz_ih_sw_init()