Lines Matching refs:gds
4567 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, adev->gds.gds_size); in gfx_v9_0_do_edc_gds_workarounds()
4579 adev->gds.gds_size); in gfx_v9_0_do_edc_gds_workarounds()
4801 (adev->gds.gds_size)) { in gfx_v9_0_ecc_late_init()
5427 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); in gfx_v9_0_ring_emit_ib_compute()
7090 adev->gds.gds_size = 0x10000; in gfx_v9_0_set_gds_init()
7094 adev->gds.gds_size = 0x1000; in gfx_v9_0_set_gds_init()
7100 adev->gds.gds_size = 0; in gfx_v9_0_set_gds_init()
7103 adev->gds.gds_size = 0x10000; in gfx_v9_0_set_gds_init()
7110 adev->gds.gds_compute_max_wave_id = 0x7ff; in gfx_v9_0_set_gds_init()
7113 adev->gds.gds_compute_max_wave_id = 0x27f; in gfx_v9_0_set_gds_init()
7117 adev->gds.gds_compute_max_wave_id = 0x77; /* raven2 */ in gfx_v9_0_set_gds_init()
7119 adev->gds.gds_compute_max_wave_id = 0x15f; /* raven1 */ in gfx_v9_0_set_gds_init()
7122 adev->gds.gds_compute_max_wave_id = 0xfff; in gfx_v9_0_set_gds_init()
7126 adev->gds.gds_compute_max_wave_id = 0; in gfx_v9_0_set_gds_init()
7130 adev->gds.gds_compute_max_wave_id = 0x7ff; in gfx_v9_0_set_gds_init()
7134 adev->gds.gws_size = 64; in gfx_v9_0_set_gds_init()
7135 adev->gds.oa_size = 16; in gfx_v9_0_set_gds_init()