Lines Matching refs:vmid
569 entry->src_id, entry->ring_id, entry->vmid, in gmc_v9_0_process_interrupt()
671 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, in gmc_v9_0_get_invalidate_req() argument
677 PER_VMID_INVALIDATE_REQ, 1 << vmid); in gmc_v9_0_get_invalidate_req()
711 uint8_t vmid, uint16_t *p_pasid) in gmc_v9_0_get_atc_vmid_pasid_mapping_info() argument
716 + vmid); in gmc_v9_0_get_atc_vmid_pasid_mapping_info()
739 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, in gmc_v9_0_flush_gpu_tlb() argument
758 inv_req = gmc_v9_0_get_invalidate_req(vmid, 2); in gmc_v9_0_flush_gpu_tlb()
759 inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type); in gmc_v9_0_flush_gpu_tlb()
761 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); in gmc_v9_0_flush_gpu_tlb()
775 1 << vmid); in gmc_v9_0_flush_gpu_tlb()
821 if (tmp & (1 << vmid)) in gmc_v9_0_flush_gpu_tlb()
861 int vmid, i; in gmc_v9_0_flush_gpu_tlb_pasid() local
916 for (vmid = 1; vmid < 16; vmid++) { in gmc_v9_0_flush_gpu_tlb_pasid()
918 ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, in gmc_v9_0_flush_gpu_tlb_pasid()
923 gmc_v9_0_flush_gpu_tlb(adev, vmid, in gmc_v9_0_flush_gpu_tlb_pasid()
926 gmc_v9_0_flush_gpu_tlb(adev, vmid, in gmc_v9_0_flush_gpu_tlb_pasid()
938 unsigned vmid, uint64_t pd_addr) in gmc_v9_0_emit_flush_gpu_tlb() argument
943 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); in gmc_v9_0_emit_flush_gpu_tlb()
961 (hub->ctx_addr_distance * vmid), in gmc_v9_0_emit_flush_gpu_tlb()
965 (hub->ctx_addr_distance * vmid), in gmc_v9_0_emit_flush_gpu_tlb()
972 req, 1 << vmid); in gmc_v9_0_emit_flush_gpu_tlb()
986 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, in gmc_v9_0_emit_pasid_mapping() argument
997 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; in gmc_v9_0_emit_pasid_mapping()
999 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; in gmc_v9_0_emit_pasid_mapping()