Lines Matching refs:WREG32_SOC15
229 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); in jpeg_v3_0_disable_clock_gating()
237 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); in jpeg_v3_0_disable_clock_gating()
244 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); in jpeg_v3_0_disable_clock_gating()
257 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); in jpeg_v3_0_enable_clock_gating()
341 WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, in jpeg_v3_0_start()
343 WREG32_SOC15(JPEG, 0, mmJPEG_ENC_GFX10_ADDR_CONFIG, in jpeg_v3_0_start()
355 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0); in jpeg_v3_0_start()
356 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); in jpeg_v3_0_start()
357 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, in jpeg_v3_0_start()
359 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, in jpeg_v3_0_start()
361 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0); in jpeg_v3_0_start()
362 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0); in jpeg_v3_0_start()
363 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L); in jpeg_v3_0_start()
364 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); in jpeg_v3_0_start()
445 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in jpeg_v3_0_dec_ring_set_wptr()